Add tests

921c39e2 · Tristan Gingold · 33b5a013 · 921c39e2 · 921c39e2 · 921c39e2
Commit 921c39e2 authored Jun 06, 2019 by Tristan Gingold
8 changed files
--- a/testsuite/045incl_makefile/Makefile.ref
+++ b/testsuite/045incl_makefile/Makefile.ref
+########################################
+#  This file was generated by hdlmake  #
+#  http://ohwr.org/projects/hdl-make/  #
+########################################
+
+include .
+
+TOP_MODULE := gate
+PWD := $(shell pwd)
+
+MODELSIM_INI_PATH := ../linux_fakebin/..
+
+VCOM_FLAGS := -quiet -modelsimini modelsim.ini 
+VSIM_FLAGS := 
+VLOG_FLAGS := -quiet -modelsimini modelsim.ini 
+VMAP_FLAGS := -modelsimini modelsim.ini 
+#target for performing local simulation
+local: sim_pre_cmd simulation sim_post_cmd
+
+VERILOG_SRC := 
+VERILOG_OBJ := 
+VHDL_SRC := ../files/gate.vhdl \
+
+VHDL_OBJ := work/gate/.gate_vhdl \
+
+INCLUDE_DIRS :=
+LIBS := work
+LIB_IND := work/.work
+
+simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
+$(VERILOG_OBJ) : modelsim.ini
+$(VHDL_OBJ): $(LIB_IND) modelsim.ini
+
+modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
+		cp $< . 2>&1
+work/.work:
+	(vlib work && vmap $(VMAP_FLAGS) work && touch work/.work )|| rm -rf work 
+
+
+work/gate/.gate_vhdl: ../files/gate.vhdl
+		vcom $(VCOM_FLAGS) -work work $< 
+		@mkdir -p $(dir $@) && touch $@ 
+
+
+# USER SIM COMMANDS
+sim_pre_cmd:
+		
+sim_post_cmd:
+		
+
+CLEAN_TARGETS := $(LIBS) modelsim.ini transcript
+
+clean:
+		rm -rf $(CLEAN_TARGETS)
+mrproper: clean
+		rm -rf *.vcd *.wlf
+
+.PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation
--- a/testsuite/045incl_makefile/Manifest.py
+++ b/testsuite/045incl_makefile/Manifest.py
+action = "simulation"
+
+sim_tool="modelsim"
+
+top_module = "gate"
+
+incl_makefiles = "a.mk"
+files = [ "../files/gate.vhdl" ]
--- a/testsuite/045incl_makefile/a.mk
+++ b/testsuite/045incl_makefile/a.mk
+# Makefile a
--- a/testsuite/046incl_makefiles/Makefile.ref
+++ b/testsuite/046incl_makefiles/Makefile.ref
+########################################
+#  This file was generated by hdlmake  #
+#  http://ohwr.org/projects/hdl-make/  #
+########################################
+
+include a.mk
+include b.mk
+
+TOP_MODULE := gate
+PWD := $(shell pwd)
+
+MODELSIM_INI_PATH := ../linux_fakebin/..
+
+VCOM_FLAGS := -quiet -modelsimini modelsim.ini 
+VSIM_FLAGS := 
+VLOG_FLAGS := -quiet -modelsimini modelsim.ini 
+VMAP_FLAGS := -modelsimini modelsim.ini 
+#target for performing local simulation
+local: sim_pre_cmd simulation sim_post_cmd
+
+VERILOG_SRC := 
+VERILOG_OBJ := 
+VHDL_SRC := ../files/gate.vhdl \
+
+VHDL_OBJ := work/gate/.gate_vhdl \
+
+INCLUDE_DIRS :=
+LIBS := work
+LIB_IND := work/.work
+
+simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
+$(VERILOG_OBJ) : modelsim.ini
+$(VHDL_OBJ): $(LIB_IND) modelsim.ini
+
+modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
+		cp $< . 2>&1
+work/.work:
+	(vlib work && vmap $(VMAP_FLAGS) work && touch work/.work )|| rm -rf work 
+
+
+work/gate/.gate_vhdl: ../files/gate.vhdl
+		vcom $(VCOM_FLAGS) -work work $< 
+		@mkdir -p $(dir $@) && touch $@ 
+
+
+# USER SIM COMMANDS
+sim_pre_cmd:
+		
+sim_post_cmd:
+		
+
+CLEAN_TARGETS := $(LIBS) modelsim.ini transcript
+
+clean:
+		rm -rf $(CLEAN_TARGETS)
+mrproper: clean
+		rm -rf *.vcd *.wlf
+
+.PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation
--- a/testsuite/046incl_makefiles/Manifest.py
+++ b/testsuite/046incl_makefiles/Manifest.py
+action = "simulation"
+
+sim_tool="modelsim"
+
+top_module = "gate"
+
+incl_makefiles = ["a.mk", "b.mk"]
+files = [ "../files/gate.vhdl" ]
--- a/testsuite/046incl_makefiles/a.mk
+++ b/testsuite/046incl_makefiles/a.mk
+# Makefile a
--- a/testsuite/046incl_makefiles/b.mk
+++ b/testsuite/046incl_makefiles/b.mk
+# Makefile b
--- a/testsuite/047err_abs_local/Manifest.py
+++ b/testsuite/047err_abs_local/Manifest.py
+action = "simulation"
+
+sim_tool="modelsim"
+
+top_module = "gate"
+
+#files = [ "../files/gate_tb.vhdl" ]
+modules = { 'local': [ "/tmp/sub1"]}