divide flow.py into separate file for each tool

8e433b0d · Paweł Szostek · 040b1112 · 8e433b0d · 8e433b0d · 8e433b0d
Commit 8e433b0d authored Jul 31, 2013 by Paweł Szostek
9 changed files
--- a/src/action/ise_project.py
+++ b/src/action/ise_project.py
@@ -6,11 +6,20 @@ import os
 from dependable_file import DependableFile
 import dep_solver
 from srcfile import SourceFileSet
-from flow import ISEProject
+from tools.ise import ISEProject
 from srcfile import SourceFileFactory
-
+import global_mod
+import path

 class GenerateISEProject(Action):
+    def _check_manifest(self):
+        self._check_manifest_variable_is_set("top_module")
+        self._check_manifest_variable_is_set("syn_device")
+        self._check_manifest_variable_is_set("syn_device")
+        self._check_manifest_variable_is_set("syn_grade")
+        self._check_manifest_variable_is_set("syn_package")
+
+
    def run(self):
        env = self.env
        if self.env["ise_path"] is None:
@@ -23,7 +32,7 @@ class GenerateISEProject(Action):
                              "or set")
                sys.exit("Exiting")
            else:
-                logging.info("Generating project for ISE v. %d.%d" % (env["ise_version"][0], env["ise_version"][1]))
+                logging.info("Generating project for ISE v. %s.%s" % (env["ise_version"][0], env["ise_version"][1]))
        self._check_all_fetched_or_quit()

        if os.path.exists(self.top_module.syn_project) or os.path.exists(self.top_module.syn_project + ".xise"):
@@ -42,16 +51,73 @@ class GenerateISEProject(Action):

        prj = ISEProject(ise=self.env["ise_version"],
                         top_mod=self.modules_pool.get_top_module())
+        self._write_project_vhd()
        prj.add_files(all_files)
        sff = SourceFileFactory()
        logging.debug(top_mod.vlog_opt)
-        prj.add_files([sff.new(top_mod.vlog_opt)])
+       # prj.add_files([sff.new(top_mod.vlog_opt)])
+
+        prj.add_files([sff.new(path=path.rel2abs("project.vhd"),
+                               module=self.modules_pool.get_module_by_path("."))])
        prj.add_libs(all_files.get_libs())
        if update is True:
            prj.load_xml(top_mod.syn_project)
        else:
-            prj.add_initial_properties(syn_device=top_mod.syn_device,
-                                       syn_grade=top_mod.syn_grade,
-                                       syn_package=top_mod.syn_package,
-                                       syn_top=top_mod.syn_top)
+            prj.add_initial_properties()
        prj.emit_xml(top_mod.syn_project)
+
+    def _write_project_vhd(self):
+        from string import Template
+        from datetime import date
+        import getpass
+
+        today = date.today()
+        date_string = today.strftime("%Y%m%d")
+        template = Template("""library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package sdb_meta_pkg is
+
+  ------------------------------------------------------------------------------
+  -- Meta-information sdb records
+  ------------------------------------------------------------------------------
+
+  -- Top module repository url
+  constant c_SDB_REPO_URL : t_sdb_repo_url := (
+    -- url (string, 63 char)
+    repo_url => "$repo_url");
+
+  -- Synthesis informations
+  constant c_SDB_SYNTHESIS : t_sdb_synthesis := (
+    -- Top module name (string, 16 char)
+    syn_module_name  => "$syn_module_name",
+    -- Commit ID (hex string, 128-bit = 32 char)
+    -- git log -1 --format="%H" | cut -c1-32
+    syn_commit_id    => "$syn_commit_id",
+    -- Synthesis tool name (string, 8 char)
+    syn_tool_name    => "$syn_tool_name",
+    -- Synthesis tool version (bcd encoded, 32-bit)
+    syn_tool_version => "$syn_tool_version",
+    -- Synthesis date (bcd encoded, 32-bit)
+    syn_date         => x"$syn_date",
+    -- Synthesised by (string, 15 char)
+    syn_username     => "$syn_username");
+
+end sdb_meta_pkg;
+
+package body sdb_meta_pkg is
+end sdb_meta_pkg;""")
+
+        project_vhd = open("project.vhd", 'w')
+        ise_version = "%s.%s" % (global_mod.env["ise_version"][0], global_mod.env["ise_version"][1])
+        filled_template = template.substitute(repo_url=global_mod.top_module.url,
+                                              syn_module_name=global_mod.top_module.top_module,
+                                              syn_commit_id=global_mod.top_module.revision,
+                                              syn_tool_name="ISE",
+                                              syn_tool_version=ise_version,
+                                              syn_date=date_string,
+                                              syn_username=getpass.getuser())
+        project_vhd.write(filled_template)
+        project_vhd.close()
--- a/src/action/quartus_project.py
+++ b/src/action/quartus_project.py
@@ -4,7 +4,7 @@ import os
 from dependable_file import DependableFile
 from action import Action
 import dep_solver
-from flow_altera import QuartusProject
+from tools.quartus import QuartusProject


 class GenerateQuartusProject(Action):

--- a/src/makefile_writer.py
+++ b/src/makefile_writer.py
@@ -346,7 +346,7 @@ mrproper:

    def generate_vsim_makefile(self, fileset, top_module):
        from srcfile import VerilogFile, VHDLFile, SVFile
-        from flow import ModelsiminiReader
+        from tools.modelsim import ModelsiminiReader
        make_preambule_p1 = """## variables #############################
 PWD := $(shell pwd)

@@ -470,7 +470,7 @@ clean:
 # Modification here
    def generate_isim_makefile(self, fileset, top_module):
        from srcfile import VerilogFile, VHDLFile
-        from flow import XilinxsiminiReader
+        from tools.ise import XilinxsiminiReader
        make_preambule_p1 = """## variables #############################
 PWD := $(shell pwd)
 TOP_MODULE := """ + top_module.top_module + """

--- a/src/srcfile.py
+++ b/src/srcfile.py
@@ -24,7 +24,9 @@ from dependable_file import DependableFile
 import os
 import global_mod
 import logging
-import flow
+from tools import ise
+from tools import modelsim
+from tools import quartus
 import path as path_mod
 from subprocess import Popen, PIPE

@@ -153,25 +155,23 @@ class VHDLFile(SourceFile):
        if global_mod.top_module.action == "simulation":
            try:
                if global_mod.top_module.sim_tool == "isim":
-                    std_libs = flow.XilinxsiminiReader().get_libraries()
+                    std_libs = ise.XilinxsiminiReader().get_libraries()
                elif global_mod.top_module.sim_tool == "vsim" or global_mod.top_module.sim_tool == "modelsim":
-                    std_libs = flow.ModelsiminiReader().get_libraries()
+                    std_libs = modelsim.ModelsiminiReader().get_libraries()
                elif global_mod.top_module.sim_tool == "iverilog":
-                    std_libs = flow.MODELSIM_STANDARD_LIBS
+                    std_libs = modelsim.MODELSIM_STANDARD_LIBS
                else:
                    logging.warning("Could not determine simulation tool. Defaulting to Modelsim")
-                    std_libs = flow.MODELSIM_STANDARD_LIBS
+                    std_libs = modelsim.MODELSIM_STANDARD_LIBS
            except RuntimeError as e:
-             #std_libs =  flow.MODELSIM_STANDARD_LIBS
                logging.error("I/O error: ({0})".format(e.message))
                logging.error("Picking standard Modelsim simulation libraries. Try to fix the error.")
-                std_libs = flow.MODELSIM_STARDAND_LIBS
+                std_libs = modelsim.MODELSIM_STARDAND_LIBS
        elif global_mod.top_module.action == "synthesis":
-            print("setting std libs for synthesis...")
            if global_mod.top_module.target == "xilinx":
-                std_libs = flow.ISE_STANDARD_LIBS
+                std_libs = ise.ISE_STANDARD_LIBS
            elif global_mod.top_module.target == "altera":
-                std_libs = flow.QUARTUS_STANDARD_LIBS
+                std_libs = quartus.QUARTUS_STANDARD_LIBS

        import re
        try:

--- a/src/tools/__init__.py
+++ b/src/tools/__init__.py
--- a/src/flow.py
+++ b/src/flow.py
--- a/src/tools/isim.py
+++ b/src/tools/isim.py
+ISIM_STARDAND_LIBS = ['std', 'ieee', 'ieee_proposed', 'vl', 'synopsys',
+                      'simprim', 'unisim', 'unimacro', 'aim', 'cpld',
+                      'pls', 'xilinxcorelib', 'aim_ver', 'cpld_ver',
+                      'simprims_ver', 'unisims_ver', 'uni9000_ver',
+                      'unimacro_ver', 'xilinxcorelib_ver', 'secureip']
--- a/src/tools/modelsim.py
+++ b/src/tools/modelsim.py
+#!/usr/bin/python
+# -*- coding: utf-8 -*-
+#
+# Copyright (c) 2013 CERN
+# Author: Pawel Szostek (pawel.szostek@cern.ch)
+# Modified to allow ISim simulation by Lucas Russo (lucas.russo@lnls.br)
+# Modified to allow ISim simulation by Adrian Byszuk (adrian.byszuk@lnls.br)
+#
+# This file is part of Hdlmake.
+#
+# Hdlmake is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# Hdlmake is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with Hdlmake.  If not, see <http://www.gnu.org/licenses/>.
+#
+
+from __future__ import print_function
+import xml.dom.minidom
+import xml.parsers.expat
+import os
+import re
+
+XmlImpl = xml.dom.minidom.getDOMImplementation()
+
+MODELSIM_STANDARD_LIBS = ['ieee', 'std']
+
+
+class ModelsiminiReader(object):
+    def __init__(self, path=None):
+        if path is None:
+            path = self.modelsim_ini_dir() + "/modelsim.ini"
+        self.path = path
+
+    def get_libraries(self):
+        new_section = "\[[^\[\]]+\]"
+        libs = []
+
+        try:
+            ini = open(self.path, "r")
+        except Exception:
+            return []
+
+        #p.info("Reading 'modelsim.ini' located in: '"+ str(self.path))
+
+        reading_libraries = False
+        for line in ini:
+            line = line.split(" ")[0]
+            line = line.strip()
+            if line == "":
+                continue
+            if line.lower() == "[library]":
+                reading_libraries = True
+                continue
+            if re.search(new_section, line):
+                if reading_libraries is True:
+                #reading_libraries = False
+                    break
+                else:
+                    continue
+            if reading_libraries:
+                line = line.split('=')
+                lib = line[0].strip()
+                libs.append(lib.lower())
+        return libs
+
+    @staticmethod
+    def modelsim_ini_dir():
+        vsim_path = os.popen("which vsim").read().strip()
+        bin_path = os.path.dirname(vsim_path)
+        return os.path.abspath(bin_path+"/../")
--- a/src/flow_altera.py
+++ b/src/flow_altera.py
@@ -20,6 +20,10 @@
 # along with Hdlmake.  If not, see <http://www.gnu.org/licenses/>.
 #

+
+QUARTUS_STANDARD_LIBS = ['altera', 'altera_mf', 'lpm', 'ieee', 'std']
+
+
 class _QuartusProjectProperty:
    SET_GLOBAL_INSTANCE, SET_INSTANCE_ASSIGNMENT, SET_LOCATION_ASSIGNMENT, SET_GLOBAL_ASSIGNMENT = range(4)
    t = {"set_global_instance": SET_GLOBAL_INSTANCE,
@@ -85,7 +89,7 @@ class QuartusProject:
        if self.postflow:
            post = tmp.format("POST_FLOW_SCTIPT_FILE", self.postflow.rel_path())
        return pre+'\n'+post+'\n'
-        
+
    def __emit_files(self):
        from srcfile import VHDLFile, VerilogFile, SignalTapFile, SDCFile, QIPFile, DPFFile
        tmp = "set_global_assignment -name {0} {1}"
@@ -107,7 +111,7 @@ class QuartusProject:
                continue
            ret.append(line)
        return ('\n'.join(ret))+'\n'
- 
+
    def add_property(self, val):
        #don't save files (they are unneeded)
        if val.name_type is not None and "_FILE" in val.name_type:
@@ -123,13 +127,13 @@ class QuartusProject:
            i = first_index
            ret = []
            if words[i][0] != '"':
-                return (words[i],1)
+                return (words[i], 1)
            else:
                while True:
                    ret.append(words[i])
                    if words[i][len(words[i])-1] == '"':
                        return (' '.join(ret), len(ret))
-                    i=i+1
+                    i = i + 1

        f = open(self.filename+'.qsf', "r")
        lines = [l.strip() for l in f.readlines()]
@@ -165,8 +169,12 @@ class QuartusProject:
                    what = words[i]
                    i = i+1
                    continue
-            prop = QPP(command=command, what=what, name=name,
-          name_type=name_type, from_=from_, to=to, section_id=section_id)
+            prop = QPP(command=command,
+                       what=what, name=name,
+                       name_type=name_type,
+                       from_=from_,
+                       to=to,
+                       section_id=section_id)

            self.add_property(prop)
        f.close()
@@ -174,16 +182,16 @@ class QuartusProject:
    def add_initial_properties(self, syn_device, syn_grade, syn_package, syn_top):
        import re
        family_names = {
-            "^EP2AGX.*$" : "Arria II GX",
-            "^EP3C.*$" : "Cyclone III"
-            }
+            "^EP2AGX.*$": "Arria II GX",
+            "^EP3C.*$": "Cyclone III"
+        }

        for key in family_names:
            if re.match(key, syn_device.upper()):
                family = family_names[key]
-                
-        devstring = (syn_device +syn_package+syn_grade).upper()
-        QPP =_QuartusProjectProperty
+
+        devstring = (syn_device + syn_package + syn_grade).upper()
+        QPP = _QuartusProjectProperty
        self.add_property(QPP(QPP.SET_GLOBAL_ASSIGNMENT, name_type='FAMILY', name='"'+family+'"'))
        self.add_property(QPP(QPP.SET_GLOBAL_ASSIGNMENT, name_type='DEVICE', name=devstring))
        self.add_property(QPP(QPP.SET_GLOBAL_ASSIGNMENT, name_type='TOP_LEVEL_ENTITY', name=syn_top))