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8bdf0bf6
Commit
8bdf0bf6
authored
Oct 30, 2019
by
Tristan Gingold
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Add a test for multiple satisfaction.
parent
21d32628
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4 changed files
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93 additions
and
0 deletions
+93
-0
Makefile.ref
testsuite/093multi_sat/Makefile.ref
+73
-0
Manifest.py
testsuite/093multi_sat/Manifest.py
+8
-0
lgate.vhdl
testsuite/093multi_sat/lgate.vhdl
+9
-0
test_all.py
testsuite/test_all.py
+3
-0
No files found.
testsuite/093multi_sat/Makefile.ref
0 → 100644
View file @
8bdf0bf6
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE
:=
gate3
MODELSIM_INI_PATH
:=
$(HDLMAKE_MODELSIM_PATH)
/..
VCOM_FLAGS
:=
-quiet
-modelsimini
modelsim.ini
VSIM_FLAGS
:=
VLOG_FLAGS
:=
-quiet
-modelsimini
modelsim.ini
VMAP_FLAGS
:=
-modelsimini
modelsim.ini
#target for performing local simulation
local
:
sim_pre_cmd simulation sim_post_cmd
VERILOG_SRC
:=
VERILOG_OBJ
:=
VHDL_SRC
:=
lgate.vhdl
\
../files/gate.vhdl
\
../files/gate3.vhd
\
VHDL_OBJ
:=
work/lgate/.lgate_vhdl
\
work/gate/.gate_vhdl
\
work/gate3/.gate3_vhd
\
INCLUDE_DIRS
:=
LIBS
:=
work
LIB_IND
:=
work/.work
simulation
:
modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ)
:
modelsim.ini
$(VHDL_OBJ)
:
$(LIB_IND) modelsim.ini
modelsim.ini
:
$(MODELSIM_INI_PATH)/modelsim.ini
cp
$<
.
2>&1
work/.work
:
(
vlib work
&&
vmap
$(VMAP_FLAGS)
work
&&
touch
work/.work
)||
rm
-rf
work
work/lgate/.lgate_vhdl
:
lgate.vhdl
\
work/gate/.gate_vhdl
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gate/.gate_vhdl
:
../files/gate.vhdl
\
work/lgate/.lgate_vhdl
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gate3/.gate3_vhd
:
../files/gate3.vhd
\
work/lgate/.lgate_vhdl
\
work/gate/.gate_vhdl
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
# USER SIM COMMANDS
sim_pre_cmd
:
sim_post_cmd
:
CLEAN_TARGETS
:=
$(LIBS)
modelsim.ini transcript
clean
:
rm
-rf
$(CLEAN_TARGETS)
mrproper
:
clean
rm
-rf
*
.vcd
*
.wlf
.PHONY
:
mrproper clean sim_pre_cmd sim_post_cmd simulation
testsuite/093multi_sat/Manifest.py
0 → 100644
View file @
8bdf0bf6
action
=
"simulation"
sim_tool
=
"modelsim"
sim_path
=
"fake_bin"
top_module
=
"gate3"
files
=
[
"../files/gate3.vhd"
,
"../files/gate.vhdl"
,
"lgate.vhdl"
]
testsuite/093multi_sat/lgate.vhdl
0 → 100644
View file @
8bdf0bf6
entity
gate
is
port
(
o
:
out
bit
;
i
:
in
bit
);
end
gate
;
architecture
behav
of
gate
is
begin
o
<=
not
i
;
end
behav
;
testsuite/test_all.py
View file @
8bdf0bf6
...
...
@@ -495,6 +495,9 @@ def test_err_filetype():
run
([],
path
=
"092bad_filetype"
)
assert
False
def
test_multi_sat
():
run_compare
(
path
=
"093multi_sat"
)
@
pytest
.
mark
.
xfail
def
test_xfail
():
"""This is a self-consistency test: the test is known to fail"""
...
...
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