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Hdlmake
Commits
8bd44158
Commit
8bd44158
authored
Mar 28, 2015
by
Josh Smith
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Added Aldec Riviera support for simulation.
parent
832a1f6e
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8 changed files
with
358 additions
and
163 deletions
+358
-163
__init__.py
hdlmake/tools/common/__init__.py
+1
-0
sim_makefile_support.py
hdlmake/tools/common/sim_makefile_support.py
+240
-0
modelsim.py
hdlmake/tools/modelsim/modelsim.py
+14
-163
__init__.py
hdlmake/tools/riviera/__init__.py
+0
-0
riviera.py
hdlmake/tools/riviera/riviera.py
+82
-0
Manifest.py
tests/counter/sim/riviera/verilog/Manifest.py
+9
-0
Manifest.py
tests/counter/sim/riviera/vhdl/Manifest.py
+9
-0
vsim.do
tests/counter/sim/riviera/vsim.do
+3
-0
No files found.
hdlmake/tools/common/__init__.py
0 → 100644
View file @
8bd44158
"""Common functionality shared by multiple tools."""
hdlmake/tools/common/sim_makefile_support.py
0 → 100644
View file @
8bd44158
#!/usr/bin/python
# -*- coding: utf-8 -*-
#
# Copyright (c) 2013 - 2015 CERN
# Author: Pawel Szostek (pawel.szostek@cern.ch)
# Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com)
#
# This file is part of Hdlmake.
#
# Hdlmake is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# Hdlmake is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with Hdlmake. If not, see <http://www.gnu.org/licenses/>.
#
from
makefile_writer
import
MakefileWriter
import
os
import
string
from
string
import
Template
class
VsimMakefileWriter
(
MakefileWriter
):
"""A Makefile writer for simulation suitable for vsim based simulators.
Currently used by:
- Modelsim
- Riviera
"""
def
__init__
(
self
):
# additional global flags to pass to every invocation of these commands
self
.
vcom_flags
=
[
"-quiet"
,
]
self
.
vsim_flags
=
[]
self
.
vlog_flags
=
[
"-quiet"
,
]
self
.
vmap_flags
=
[]
# These are variables that will be set in the makefile
# The key is the variable name, and the value is the variable value
self
.
custom_variables
=
{}
# Additional sim dependencies (e.g. modelsim.ini)
self
.
additional_deps
=
[]
# Additional things removed during a clean e.g. simulator temp files
self
.
additional_clean
=
[]
# These are files copied into your working directory by a make rule
# The key is the filename, the value is the file source path
self
.
copy_rules
=
{}
super
(
VsimMakefileWriter
,
self
)
.
__init__
()
def
generate_simulation_makefile
(
self
,
fileset
,
top_module
):
"""Write a properly formatted Makefile for the simulator.
The Makefile format is shared, but flags, dependencies, clean rules,
etc are defined by the specific tool.
"""
from
srcfile
import
VerilogFile
,
VHDLFile
,
SVFile
self
.
vlog_flags
.
append
(
self
.
__get_rid_of_vsim_incdirs
(
top_module
.
vlog_opt
))
tmp
=
"""## variables #############################
PWD := $(shell pwd)
"""
self
.
write
(
tmp
)
self
.
writeln
()
for
var
,
value
in
self
.
custom_variables
.
iteritems
():
self
.
writeln
(
"
%
s :=
%
s"
%
(
var
,
value
))
self
.
writeln
()
self
.
writeln
(
"VCOM_FLAGS :=
%
s"
%
(
' '
.
join
(
self
.
vcom_flags
)))
self
.
writeln
(
"VSIM_FLAGS :=
%
s"
%
(
' '
.
join
(
self
.
vsim_flags
)))
self
.
writeln
(
"VLOG_FLAGS :=
%
s"
%
(
' '
.
join
(
self
.
vlog_flags
)))
self
.
writeln
(
"VMAP_FLAGS :=
%
s"
%
(
' '
.
join
(
self
.
vmap_flags
)))
self
.
write
(
"VERILOG_SRC := "
)
for
vl
in
fileset
.
filter
(
VerilogFile
):
self
.
write
(
vl
.
rel_path
()
+
"
\\\n
"
)
self
.
write
(
"
\n
"
)
self
.
write
(
"VERILOG_OBJ := "
)
for
vl
in
fileset
.
filter
(
VerilogFile
):
# make a file compilation indicator (these .dat files are made even if
# the compilation process fails) and add an ending according to file's
# extension (.sv and .vhd files may have the same corename and this
# causes a mess
self
.
write
(
os
.
path
.
join
(
vl
.
library
,
vl
.
purename
,
"."
+
vl
.
purename
+
"_"
+
vl
.
extension
())
+
"
\\\n
"
)
self
.
write
(
'
\n
'
)
libs
=
set
(
f
.
library
for
f
in
fileset
)
self
.
write
(
"VHDL_SRC := "
)
for
vhdl
in
fileset
.
filter
(
VHDLFile
):
self
.
write
(
vhdl
.
rel_path
()
+
"
\\\n
"
)
self
.
writeln
()
# list vhdl objects (_primary.dat files)
self
.
write
(
"VHDL_OBJ := "
)
for
vhdl
in
fileset
.
filter
(
VHDLFile
):
# file compilation indicator (important: add _vhd ending)
self
.
write
(
os
.
path
.
join
(
vhdl
.
library
,
vhdl
.
purename
,
"."
+
vhdl
.
purename
+
"_"
+
vhdl
.
extension
())
+
"
\\\n
"
)
self
.
write
(
'
\n
'
)
self
.
write
(
'LIBS := '
)
self
.
write
(
' '
.
join
(
libs
))
self
.
write
(
'
\n
'
)
# tell how to make libraries
self
.
write
(
'LIB_IND := '
)
self
.
write
(
' '
.
join
([
lib
+
"/."
+
lib
for
lib
in
libs
]))
self
.
write
(
'
\n
'
)
self
.
writeln
(
"## rules #################################"
)
self
.
writeln
()
self
.
writeln
(
"local: sim_pre_cmd simulation sim_post_cmd"
)
self
.
writeln
()
self
.
writeln
(
"simulation:
%
s $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)"
%
(
' '
.
join
(
self
.
additional_deps
)),)
self
.
writeln
(
"$(VERILOG_OBJ) : "
+
' '
.
join
(
self
.
additional_deps
))
self
.
writeln
(
"$(VHDL_OBJ): $(LIB_IND) "
+
' '
.
join
(
self
.
additional_deps
))
self
.
writeln
()
simcommands
=
string
.
Template
(
"""sim_pre_cmd:
\t\t
${sim_pre_cmd}
sim_post_cmd:
\t\t
${sim_post_cmd}
"""
)
if
top_module
.
sim_pre_cmd
:
sim_pre_cmd
=
top_module
.
sim_pre_cmd
else
:
sim_pre_cmd
=
''
if
top_module
.
sim_post_cmd
:
sim_post_cmd
=
top_module
.
sim_post_cmd
else
:
sim_post_cmd
=
''
simcommands
=
simcommands
.
substitute
(
sim_pre_cmd
=
sim_pre_cmd
,
sim_post_cmd
=
sim_post_cmd
)
self
.
write
(
simcommands
)
self
.
writeln
()
for
filename
,
filesource
in
self
.
copy_rules
.
iteritems
():
self
.
write
(
self
.
__create_copy_rule
(
filename
,
filesource
))
self
.
writeln
(
"clean:"
)
tmp
=
"
\t\t
rm -rf $(LIBS) "
+
' '
.
join
(
self
.
additional_clean
)
self
.
writeln
(
tmp
)
self
.
writeln
(
".PHONY: clean sim_pre_cmd sim_post_cmd simulation"
)
self
.
writeln
()
for
lib
in
libs
:
self
.
write
(
lib
+
"/."
+
lib
+
":
\n
"
)
vmap_command
=
"vmap $(VMAP_FLAGS)"
self
.
write
(
' '
.
join
([
"
\t
(vlib"
,
lib
,
"&&"
,
vmap_command
,
lib
,
"&&"
,
"touch"
,
lib
+
"/."
+
lib
,
")"
]))
self
.
write
(
' '
.
join
([
"||"
,
"rm -rf"
,
lib
,
"
\n
"
]))
self
.
write
(
'
\n\n
'
)
# rules for all _primary.dat files for sv
for
vl
in
fileset
.
filter
(
VerilogFile
):
self
.
write
(
"
%
s:
%
s"
%
(
os
.
path
.
join
(
vl
.
library
,
vl
.
purename
,
".
%
s_
%
s"
%
(
vl
.
purename
,
vl
.
extension
())),
vl
.
rel_path
())
)
for
dep_file
in
[
dfile
for
dfile
in
vl
.
depends_on
if
dfile
is
not
vl
]:
if
dep_file
in
fileset
:
# the dep_file is compiled -> we depend on marker file
name
=
dep_file
.
purename
extension
=
dep_file
.
extension
()
self
.
write
(
"
\\\n
"
+
os
.
path
.
join
(
dep_file
.
library
,
name
,
".
%
s_
%
s"
%
(
name
,
extension
)))
else
:
#the file is included -> we depend directly on the file
self
.
write
(
"
\\\n
"
+
dep_file
.
rel_path
())
self
.
writeln
()
# ##
# self.write("\t\tvlog -work "+vl.library)
# self.write(" $(VLOG_FLAGS) ")
# if isinstance(vl, SVFile):
# self.write(" -sv ")
# incdir = "+incdir+"
# incdir += '+'.join(vl.include_dirs)
# incdir += " "
# self.write(incdir)
# self.writeln(vl.vlog_opt+" $<")
####
compile_template
=
Template
(
"
\t\t
vlog -work ${library} $$(VLOG_FLAGS) ${sv_option} +incdir+${include_dirs} ${vlog_opt} $$<"
)
compile_line
=
compile_template
.
substitute
(
library
=
vl
.
library
,
sv_option
=
"-sv"
if
isinstance
(
vl
,
SVFile
)
else
""
,
include_dirs
=
'+'
.
join
(
vl
.
include_dirs
),
vlog_opt
=
vl
.
vlog_opt
)
self
.
writeln
(
compile_line
)
self
.
write
(
"
\t\t
@mkdir -p $(dir $@)"
)
self
.
writeln
(
" && touch $@
\n\n
"
)
self
.
write
(
"
\n
"
)
# list rules for all _primary.dat files for vhdl
for
vhdl
in
fileset
.
filter
(
VHDLFile
):
lib
=
vhdl
.
library
purename
=
vhdl
.
purename
# each .dat depends on corresponding .vhd file
self
.
write
(
"
%
s:
%
s"
%
(
os
.
path
.
join
(
lib
,
purename
,
"."
+
purename
+
"_"
+
vhdl
.
extension
()),
vhdl
.
rel_path
())
)
for
dep_file
in
vhdl
.
depends_on
:
if
dep_file
in
fileset
:
# the dep_file is compiled -> we depend on marker file
name
=
dep_file
.
purename
extension
=
dep_file
.
extension
()
self
.
write
(
"
\\\n
"
+
os
.
path
.
join
(
dep_file
.
library
,
name
,
".
%
s_
%
s"
%
(
name
,
extension
)))
else
:
#the file is included -> we depend directly on the file
self
.
write
(
"
\\\n
"
+
dep_file
.
rel_path
())
self
.
writeln
()
self
.
writeln
(
' '
.
join
([
"
\t\t
vcom $(VCOM_FLAGS)"
,
vhdl
.
vcom_opt
,
"-work"
,
lib
,
"$< "
]))
self
.
writeln
(
"
\t\t
@mkdir -p $(dir $@) && touch $@
\n
"
)
self
.
writeln
()
def
__create_copy_rule
(
self
,
name
,
src
):
"""Get a Makefile rule named name, which depends on src, copying it to
the local directory."""
rule
=
"""
%
s:
%
s
\t\t
cp $< . 2>&1
"""
%
(
name
,
src
)
return
rule
def
__get_rid_of_vsim_incdirs
(
self
,
vlog_opt
=
""
):
if
not
vlog_opt
:
vlog_opt
=
""
vlogs
=
vlog_opt
.
split
(
' '
)
ret
=
[]
for
v
in
vlogs
:
if
not
v
.
startswith
(
"+incdir+"
):
ret
.
append
(
v
)
return
' '
.
join
(
ret
)
hdlmake/tools/modelsim/modelsim.py
View file @
8bd44158
...
@@ -33,15 +33,16 @@ import string
...
@@ -33,15 +33,16 @@ import string
from
string
import
Template
from
string
import
Template
import
fetch
import
fetch
from
makefile_writer
import
MakefileWriter
from
..
common
.
sim_makefile_support
import
VsimMakefileWriter
XmlImpl
=
xml
.
dom
.
minidom
.
getDOMImplementation
()
XmlImpl
=
xml
.
dom
.
minidom
.
getDOMImplementation
()
MODELSIM_STANDARD_LIBS
=
[
'ieee'
,
'std'
]
MODELSIM_STANDARD_LIBS
=
[
'ieee'
,
'std'
]
class
ToolControls
(
MakefileWriter
):
class
ToolControls
(
VsimMakefileWriter
):
def
__init__
(
self
):
super
(
ToolControls
,
self
)
.
__init__
()
def
detect_version
(
self
,
path
):
def
detect_version
(
self
,
path
):
pass
pass
...
@@ -60,167 +61,17 @@ class ToolControls(MakefileWriter):
...
@@ -60,167 +61,17 @@ class ToolControls(MakefileWriter):
return
MODELSIM_STANDARD_LIBS
return
MODELSIM_STANDARD_LIBS
def
generate_simulation_makefile
(
self
,
fileset
,
top_module
):
def
generate_simulation_makefile
(
self
,
fileset
,
top_module
):
from
srcfile
import
VerilogFile
,
VHDLFile
,
SVFile
self
.
vcom_flags
.
extend
([
"-modelsimini"
,
"modelsim.ini"
])
make_preambule_p1
=
"""## variables #############################
self
.
vlog_flags
.
extend
([
"-modelsimini"
,
"modelsim.ini"
])
PWD := $(shell pwd)
self
.
vmap_flags
.
extend
([
"-modelsimini"
,
"modelsim.ini"
])
MODELSIM_INI_PATH := {0}
VCOM_FLAGS := -quiet -modelsimini modelsim.ini
VSIM_FLAGS :=
VLOG_FLAGS := -quiet -modelsimini modelsim.ini """
+
self
.
__get_rid_of_vsim_incdirs
(
top_module
.
vlog_opt
)
+
"""
"""
if
global_mod
.
env
[
"modelsim_path"
]:
if
global_mod
.
env
[
"modelsim_path"
]:
m
ake_preambule_p1
=
make_preambule_p1
.
format
(
os
.
path
.
join
(
global_mod
.
env
[
"modelsim_path"
],
".."
)
)
m
odelsim_ini_path
=
os
.
path
.
join
(
global_mod
.
env
[
"modelsim_path"
],
".."
)
else
:
else
:
make_preambule_p1
=
make_preambule_p1
.
format
(
os
.
path
.
join
(
"$(HDLMAKE_MODELSIM_PATH)"
,
".."
))
modelsim_ini_path
=
os
.
path
.
join
(
"$(HDLMAKE_MODELSIM_PATH)"
,
".."
)
make_preambule_p2
=
string
.
Template
(
"""## rules #################################
self
.
custom_variables
[
"MODELSIM_INI_PATH"
]
=
modelsim_ini_path
self
.
additional_deps
.
append
(
"modelsim.ini"
)
local: sim_pre_cmd simulation sim_post_cmd
self
.
additional_clean
.
extend
([
"./modelsim.ini"
,
"transcript"
,
"*.vcd"
,
"*.wlf"
])
simulation: modelsim.ini $$(LIB_IND) $$(VERILOG_OBJ) $$(VHDL_OBJ)
$$(VERILOG_OBJ) : modelsim.ini
$$(VHDL_OBJ): $$(LIB_IND) modelsim.ini
sim_pre_cmd:
\t\t
${sim_pre_cmd}
sim_post_cmd:
\t\t
${sim_post_cmd}
modelsim.ini: ${modelsim_ini_path}
\t\t
cp $$< . 2>&1
clean:
\t\t
rm -rf ./modelsim.ini $$(LIBS) transcript *.vcd *.wlf
.PHONY: clean sim_pre_cmd sim_post_cmd simulation
"""
)
#open the file and write the above preambule (part 1)
self
.
write
(
make_preambule_p1
)
self
.
write
(
"VERILOG_SRC := "
)
for
vl
in
fileset
.
filter
(
VerilogFile
):
self
.
write
(
vl
.
rel_path
()
+
"
\\\n
"
)
self
.
write
(
"
\n
"
)
self
.
write
(
"VERILOG_OBJ := "
)
for
vl
in
fileset
.
filter
(
VerilogFile
):
#make a file compilation indicator (these .dat files are made even if
#the compilation process fails) and add an ending according to file's
#extension (.sv and .vhd files may have the same corename and this
#causes a mess
self
.
write
(
os
.
path
.
join
(
vl
.
library
,
vl
.
purename
,
"."
+
vl
.
purename
+
"_"
+
vl
.
extension
())
+
"
\\\n
"
)
self
.
write
(
'
\n
'
)
libs
=
set
(
f
.
library
for
f
in
fileset
)
self
.
write
(
"VHDL_SRC := "
)
for
vhdl
in
fileset
.
filter
(
VHDLFile
):
self
.
write
(
vhdl
.
rel_path
()
+
"
\\\n
"
)
self
.
writeln
()
#list vhdl objects (_primary.dat files)
self
.
write
(
"VHDL_OBJ := "
)
for
vhdl
in
fileset
.
filter
(
VHDLFile
):
#file compilation indicator (important: add _vhd ending)
self
.
write
(
os
.
path
.
join
(
vhdl
.
library
,
vhdl
.
purename
,
"."
+
vhdl
.
purename
+
"_"
+
vhdl
.
extension
())
+
"
\\\n
"
)
self
.
write
(
'
\n
'
)
self
.
write
(
'LIBS := '
)
self
.
write
(
' '
.
join
(
libs
))
self
.
write
(
'
\n
'
)
#tell how to make libraries
self
.
write
(
'LIB_IND := '
)
self
.
write
(
' '
.
join
([
lib
+
"/."
+
lib
for
lib
in
libs
]))
self
.
write
(
'
\n
'
)
if
top_module
.
sim_pre_cmd
:
sim_pre_cmd
=
top_module
.
sim_pre_cmd
else
:
sim_pre_cmd
=
''
if
top_module
.
sim_post_cmd
:
sim_post_cmd
=
top_module
.
sim_post_cmd
else
:
sim_post_cmd
=
''
make_preambule_p2
=
make_preambule_p2
.
substitute
(
sim_pre_cmd
=
sim_pre_cmd
,
sim_post_cmd
=
sim_post_cmd
,
modelsim_ini_path
=
os
.
path
.
join
(
"$(MODELSIM_INI_PATH)"
,
"modelsim.ini"
))
self
.
write
(
make_preambule_p2
)
for
lib
in
libs
:
self
.
write
(
lib
+
"/."
+
lib
+
":
\n
"
)
self
.
write
(
' '
.
join
([
"
\t
(vlib"
,
lib
,
"&&"
,
"vmap"
,
"-modelsimini modelsim.ini"
,
lib
,
"&&"
,
"touch"
,
lib
+
"/."
+
lib
,
")"
]))
self
.
write
(
' '
.
join
([
"||"
,
"rm -rf"
,
lib
,
"
\n
"
]))
self
.
write
(
'
\n
'
)
#rules for all _primary.dat files for sv
for
vl
in
fileset
.
filter
(
VerilogFile
):
self
.
write
(
"
%
s:
%
s"
%
(
os
.
path
.
join
(
vl
.
library
,
vl
.
purename
,
".
%
s_
%
s"
%
(
vl
.
purename
,
vl
.
extension
())),
vl
.
rel_path
())
)
for
dep_file
in
[
dfile
for
dfile
in
vl
.
depends_on
if
dfile
is
not
vl
]:
if
dep_file
in
fileset
:
# the dep_file is compiled -> we depend on marker file
name
=
dep_file
.
purename
extension
=
dep_file
.
extension
()
self
.
write
(
"
\\\n
"
+
os
.
path
.
join
(
dep_file
.
library
,
name
,
".
%
s_
%
s"
%
(
name
,
extension
)))
else
:
#the file is included -> we depend directly on the file
self
.
write
(
"
\\\n
"
+
dep_file
.
rel_path
())
self
.
writeln
()
###
# self.write("\t\tvlog -work "+vl.library)
# self.write(" $(VLOG_FLAGS) ")
# if isinstance(vl, SVFile):
# self.write(" -sv ")
# incdir = "+incdir+"
# incdir += '+'.join(vl.include_dirs)
# incdir += " "
# self.write(incdir)
# self.writeln(vl.vlog_opt+" $<")
####
compile_template
=
Template
(
"
\t\t
vlog -work ${library} $$(VLOG_FLAGS) ${sv_option} +incdir+${include_dirs} ${vlog_opt} $$<"
)
compile_line
=
compile_template
.
substitute
(
library
=
vl
.
library
,
sv_option
=
"-sv"
if
isinstance
(
vl
,
SVFile
)
else
""
,
include_dirs
=
'+'
.
join
(
vl
.
include_dirs
),
vlog_opt
=
vl
.
vlog_opt
)
self
.
writeln
(
compile_line
)
self
.
write
(
"
\t\t
@mkdir -p $(dir $@)"
)
self
.
writeln
(
" && touch $@
\n\n
"
)
self
.
write
(
"
\n
"
)
#list rules for all _primary.dat files for vhdl
for
vhdl
in
fileset
.
filter
(
VHDLFile
):
lib
=
vhdl
.
library
purename
=
vhdl
.
purename
#each .dat depends on corresponding .vhd file
self
.
write
(
"
%
s:
%
s"
%
(
os
.
path
.
join
(
lib
,
purename
,
"."
+
purename
+
"_"
+
vhdl
.
extension
()),
vhdl
.
rel_path
())
)
for
dep_file
in
vhdl
.
depends_on
:
if
dep_file
in
fileset
:
# the dep_file is compiled -> we depend on marker file
name
=
dep_file
.
purename
extension
=
dep_file
.
extension
()
self
.
write
(
"
\\\n
"
+
os
.
path
.
join
(
dep_file
.
library
,
name
,
".
%
s_
%
s"
%
(
name
,
extension
)))
else
:
#the file is included -> we depend directly on the file
self
.
write
(
"
\\\n
"
+
dep_file
.
rel_path
())
self
.
writeln
()
self
.
writeln
(
' '
.
join
([
"
\t\t
vcom $(VCOM_FLAGS)"
,
vhdl
.
vcom_opt
,
"-work"
,
lib
,
"$< "
]))
self
.
writeln
(
"
\t\t
@mkdir -p $(dir $@) && touch $@
\n
"
)
self
.
writeln
()
def
__get_rid_of_vsim_incdirs
(
self
,
vlog_opt
):
self
.
copy_rules
[
"modelsim.ini"
]
=
os
.
path
.
join
(
"$(MODELSIM_INI_PATH)"
,
"modelsim.ini"
)
if
not
vlog_opt
:
super
(
ToolControls
,
self
)
.
generate_simulation_makefile
(
fileset
,
top_module
)
vlog_opt
=
""
vlogs
=
vlog_opt
.
split
(
' '
)
ret
=
[]
for
v
in
vlogs
:
if
not
v
.
startswith
(
"+incdir+"
):
ret
.
append
(
v
)
return
' '
.
join
(
ret
)
hdlmake/tools/riviera/__init__.py
0 → 100644
View file @
8bd44158
hdlmake/tools/riviera/riviera.py
0 → 100644
View file @
8bd44158
#!/usr/bin/python
# -*- coding: utf-8 -*-
#
# Copyright (c) 2013 - 2015 CERN
# Author: Pawel Szostek (pawel.szostek@cern.ch)
# Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com)
# Riviera tool added by Josh Smith (joshrsmith@gmail.com)
#
# This file is part of Hdlmake.
#
# Hdlmake is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# Hdlmake is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with Hdlmake. If not, see <http://www.gnu.org/licenses/>.
#
from
__future__
import
print_function
from
..
common
.
sim_makefile_support
import
VsimMakefileWriter
# as of 2014.06, these are the standard libraries
# included in an installation
RIVIERA_STANDARD_LIBS
=
[
'ieee'
,
'std'
,
'cpld'
,
'vl'
,
'vital95'
,
'vital2000'
,
'synopsys'
,
'aldec'
,
'vtl'
,
'vtl_dbg'
,
'assertions'
,
'ieee_proposed'
,
'ovm_2_0_3'
,
'ovm_2_1_2'
,
'uvm_1_0p1'
,
'uvm_1_1d'
,
'uvm'
,
'osvvm'
,
]
# there are many vendor specific libraries available
# a few of them are listed here
RIVIERA_XILINX_VHDL_LIBRARIES
=
[
'cpld'
,
'secureip'
,
'simprim'
,
'unimacro'
,
'unisim'
,
'xilinxcorelib'
]
RIVIERA_XILINX_VLOG_LIBRARIES
=
[
'cpld_ver'
,
'secureip'
,
'simprims_ver'
,
'uni9000_ver'
,
'unimacro_ver'
,
'unisims_ver'
,
'xilinxcorelib_ver'
]
RIVIERA_STANDARD_LIBS
.
extend
(
RIVIERA_XILINX_VHDL_LIBRARIES
)
RIVIERA_STANDARD_LIBS
.
extend
(
RIVIERA_XILINX_VLOG_LIBRARIES
)
class
ToolControls
(
VsimMakefileWriter
):
def
__init__
(
self
):
super
(
ToolControls
,
self
)
.
__init__
()
self
.
vcom_flags
.
append
(
"-2008"
)
self
.
additional_clean
.
extend
([
"*.asdb"
,
"*.vcd"
,
])
def
detect_version
(
self
,
path
):
pass
def
get_keys
(
self
):
tool_info
=
{
'name'
:
'Riviera'
,
'id'
:
'riviera'
,
'windows_bin'
:
'vsim'
,
'linux_bin'
:
'vsim'
}
return
tool_info
def
get_standard_libraries
(
self
):
return
RIVIERA_STANDARD_LIBS
tests/counter/sim/riviera/verilog/Manifest.py
0 → 100644
View file @
8bd44158
action
=
"simulation"
sim_tool
=
"riviera"
top_module
=
"counter_tb"
sim_post_cmd
=
"vsim -do ../vsim.do"
modules
=
{
"local"
:
[
"../../../testbench/counter_tb/verilog"
],
}
tests/counter/sim/riviera/vhdl/Manifest.py
0 → 100644
View file @
8bd44158
action
=
"simulation"
sim_tool
=
"riviera"
top_module
=
"counter_tb"
sim_post_cmd
=
"vsim -do ../vsim.do"
modules
=
{
"local"
:
[
"../../../testbench/counter_tb/vhdl"
],
}
tests/counter/sim/riviera/vsim.do
0 → 100644
View file @
8bd44158
vsim counter_tb +access +r;
add wave *;
run 6000ns;
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