Add a demo test for Xilinx Vivado synthesis on a Zedboard platform

parent fd0f57c4
action = "synthesis"
syn_device = "xc7z020"
syn_grade = "-1"
syn_package = "clg484"
syn_top = "zedboard_top"
syn_project = "zedboard_top"
syn_tool = "vivado"
modules = {
"local" : [ "../../../top/zedboard/verilog" ],
}
action = "synthesis"
syn_device = "xc7z020"
syn_grade = "-1"
syn_package = "clg484"
syn_top = "zedboard_top"
syn_project = "zedboard_top"
syn_tool = "vivado"
modules = {
"local" : [ "../../../top/zedboard/vhdl" ],
}
files = [
"zedboard_top.v",
"../zedboard_top.xdc",
]
modules = {
"local" : [ "../../../modules/counter/verilog" ],
}
//---------------------------------------------------------------------
// Design : Counter verilog top module, Avnet Zedboard Starter Kit
// Author : Javier D. Garcia-Lasheras
//---------------------------------------------------------------------
module zedboard_top (
clear_i,
count_i,
clock_i,
led_o
);
input clear_i, count_i, clock_i;
output [7:0] led_o;
wire s_clock, s_clear, s_count;
wire [7:0] s_Q;
counter u1(
.clock(s_clock),
.clear(s_clear),
.count(s_count),
.Q(s_Q)
);
assign s_clock = clock_i;
assign s_clear = clear_i;
assign s_count = count_i;
assign led_o[7:0] = s_Q[7:0];
endmodule
files = [
"zedboard_top.vhd",
"../zedboard_top.xdc",
]
modules = {
"local" : [ "../../../modules/counter/vhdl" ],
}
-----------------------------------------------------------------------
-- Design : Counter VHDL top module, Avnet Zedboard Starter Kit
-- Author : Javier D. Garcia-Lasheras
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity zedboard_top is
port (
clear_i: in std_logic;
count_i: in std_logic;
clock_i: in std_logic;
led_o: out std_logic_vector(7 downto 0)
);
end zedboard_top;
-----------------------------------------------------------------------
architecture structure of zedboard_top is
component counter
port (
clock: in std_logic;
clear: in std_logic;
count: in std_logic;
Q: out std_logic_vector(7 downto 0)
);
end component;
signal s_clock: std_logic;
signal s_clear: std_logic;
signal s_count: std_logic;
signal s_Q: std_logic_vector(7 downto 0);
begin
U_counter: counter
port map (
clock => s_clock,
clear => s_clear,
count => s_count,
Q => s_Q
);
s_clock <= clock_i;
s_clear <= clear_i;
s_count <= count_i;
led_o <= s_Q;
end architecture structure;
----------------------------------------------------------------
# ----------------------------------------------------------------------------
# Clock Source - Bank 13
# ----------------------------------------------------------------------------
set_property PACKAGE_PIN Y9 [get_ports clock_i]
set_property IOSTANDARD LVCMOS33 [get_ports clock_i]
create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports clock_i]
# ----------------------------------------------------------------------------
# Reset - BTNC (user button center)
# ----------------------------------------------------------------------------
set_property PACKAGE_PIN P16 [get_ports {clear_i}]
set_property IOSTANDARD LVCMOS33 [get_ports {clear_i}]
# ----------------------------------------------------------------------------
# Count - BTNU (user button up)
# ----------------------------------------------------------------------------
set_property PACKAGE_PIN T18 [get_ports {count_i}]
set_property IOSTANDARD LVCMOS33 [get_ports {count_i}]
# ----------------------------------------------------------------------------
# USER LEDs
# ----------------------------------------------------------------------------
set_property PACKAGE_PIN T22 [get_ports "led_o[0]"]
set_property IOSTANDARD LVCMOS33 [get_ports "led_o[0]"]
set_property PACKAGE_PIN T21 [get_ports "led_o[1]"]
set_property IOSTANDARD LVCMOS33 [get_ports "led_o[1]"]
set_property PACKAGE_PIN U22 [get_ports "led_o[2]"]
set_property IOSTANDARD LVCMOS33 [get_ports "led_o[2]"]
set_property PACKAGE_PIN U21 [get_ports "led_o[3]"]
set_property IOSTANDARD LVCMOS33 [get_ports "led_o[3]"]
set_property PACKAGE_PIN V22 [get_ports "led_o[4]"]
set_property IOSTANDARD LVCMOS33 [get_ports "led_o[4]"]
set_property PACKAGE_PIN W22 [get_ports "led_o[5]"]
set_property IOSTANDARD LVCMOS33 [get_ports "led_o[5]"]
set_property PACKAGE_PIN U19 [get_ports "led_o[6]"]
set_property IOSTANDARD LVCMOS33 [get_ports "led_o[6]"]
set_property PACKAGE_PIN U14 [get_ports "led_o[7]"]
set_property IOSTANDARD LVCMOS33 [get_ports "led_o[7]"]
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment