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Commit 84fd1ac8 authored by Tristan Gingold's avatar Tristan Gingold
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Merge branch 'shaas-liberosoc-support' into 'master' 

Added support for Microsemi Libero SoC

See merge request !6
parents 243b27bd 368df9d9
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hdlmake/tools/liberosoc.py 0 → 100644
View file @ 84fd1ac8
#!/usr/bin/python
# -*- coding: utf-8 -*-
#
# Copyright (c) 2013 - 2019 CERN
# Author: Pawel Szostek (pawel.szostek@cern.ch)
# Adopted to LiberoSoC v12.x by Severin Haas (severin.haas@cern.ch)
# Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com)
#
# This file is part of Hdlmake.
#
# Hdlmake is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# Hdlmake is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with Hdlmake. If not, see <http://www.gnu.org/licenses/>.
#
"""Module providing support for Microsemi Libero SoC 12.x synthesis"""
from __future__ import absolute_import
from .makefilesyn import MakefileSyn
from ..sourcefiles.srcfile import VHDLFile, VerilogFile, SDCFile, PDCFile
class ToolLiberoSoC(MakefileSyn):
"""Class providing the interface for Microsemi Libero SoC 12.x synthesis"""
TOOL_INFO = {
'name': 'LiberoSoC',
'id': 'liberosoc',
'windows_bin': 'libero.exe SCRIPT:',
'linux_bin': 'libero SCRIPT:',
'project_ext': 'prjx'}
STANDARD_LIBS = ['ieee', 'std']
_LIBERO_SOURCE = 'create_links {0} $(sourcefile)'
SUPPORTED_FILES = {
SDCFile: _LIBERO_SOURCE.format('-sdc'),
PDCFile: _LIBERO_SOURCE.format('-io_pdc')}
HDL_FILES = {
VHDLFile: _LIBERO_SOURCE.format('-hdl_source'),
VerilogFile: _LIBERO_SOURCE.format('-hdl_source')}
CLEAN_TARGETS = {'clean': ["$(PROJECT)"],
'mrproper': ["*.pdb", "*.stp"]}
TCL_CONTROLS = {
'create': 'new_project -location {{./{0}}} '
'-name {{{0}}} -hdl {{{1}}} '
'-family {{{2}}} -die {{{3}}} '
'-package {{{4}}} -speed {{{5}}} ',
'open': 'open_project -file {$(PROJECT)/$(PROJECT_FILE)}',
'save': 'save_project',
'close': 'close_project',
'project': '$(TCL_CREATE)\n'
'source files.tcl\n'
'refresh\n'
'{0}\n'
'$(TCL_SAVE)\n'
'$(TCL_CLOSE)',
'bitstream': '$(TCL_OPEN)\n'
'run_tool -name {GENERATEPROGRAMMINGDATA}\n'
'file mkdir ./$(PROJECT)/bitstream\n'
'export_bitstream_file '
'-file_name {$(PROJECT)} '
'-export_dir {$(PROJECT)/bitstream} '
'-format {STP} -trusted_facility_file 1 '
'-trusted_facility_file_components {FABRIC} '
'-serialization_stapl_type {SINGLE} '
'-serialization_target_solution {FLASHPRO_3_4_5}\n'
'$(TCL_SAVE)\n'
'$(TCL_CLOSE)',
'install_source': '$(PROJECT)/designer/impl1/$(SYN_TOP).pdb'}
def __init__(self):
super(ToolLiberoSoC, self).__init__()
self._tcl_controls.update(ToolLiberoSoC.TCL_CONTROLS)
def _makefile_syn_tcl(self):
"""Create a Libero synthesis project by TCL"""
syn_project = self.manifest_dict["syn_project"]
syn_device = self.manifest_dict["syn_device"]
syn_family = self.manifest_dict["syn_family"]
syn_grade = self.manifest_dict["syn_grade"]
syn_package = self.manifest_dict["syn_package"]
syn_lang = self.manifest_dict.get("language")
# Default language is VHDL, so might not be defined by the user
if syn_lang == None:
syn_lang = "VHDL"
create_tmp = self._tcl_controls["create"]
self._tcl_controls["create"] = create_tmp.format(syn_project,
syn_lang.upper(),
syn_family,
syn_device.upper(),
syn_package.upper(),
syn_grade)
project_tmp = self._tcl_controls["project"]
synthesis_constraints = []
compilation_constraints = []
ret = []
# First stage: linking files
for file_aux in self.fileset.sort():
if isinstance(file_aux, SDCFile):
synthesis_constraints.append(file_aux)
compilation_constraints.append(file_aux)
elif isinstance(file_aux, PDCFile):
compilation_constraints.append(file_aux)
# Second stage: Organizing / activating synthesis constraints (the top
# module needs to be present!)
if synthesis_constraints:
line = 'organize_tool_files -tool {SYNTHESIZE} '
for file_aux in synthesis_constraints:
line = line + '-file {' + file_aux.rel_path() + '} '
line = line + \
'-module {$(TOP_MODULE)::work} -input_type {constraint} '
ret.append(line)
# Third stage: Organizing / activating compilation constraints (the top
# module needs to be present!)
if compilation_constraints:
line = 'organize_tool_files -tool {PLACEROUTE} '
for file_aux in compilation_constraints:
line = line + '-file {' + file_aux.rel_path() + '} '
line = line + \
'-module {$(TOP_MODULE)::work} -input_type {constraint} '
ret.append(line)
# Fourth stage: set root/top module
line = 'set_root -module {$(TOP_MODULE)::work}'
ret.append(line)
self._tcl_controls['project'] = project_tmp.format('\n'.join(ret))
super(ToolLiberoSoC, self)._makefile_syn_tcl()
hdlmake/tools/load_tool.py
View file @ 84fd1ac8
...@@ -12,6 +12,7 @@ def load_syn_tool(tool_name): ...@@ -12,6 +12,7 @@ def load_syn_tool(tool_name):
from .quartus import ToolQuartus from .quartus import ToolQuartus
from .diamond import ToolDiamond from .diamond import ToolDiamond
from .libero import ToolLibero from .libero import ToolLibero
from .liberosoc import ToolLiberoSoC
from .icestorm import ToolIcestorm from .icestorm import ToolIcestorm
available_tools = {'ise': ToolISE, available_tools = {'ise': ToolISE,
'planahead': ToolPlanAhead, 'planahead': ToolPlanAhead,
...@@ -19,6 +20,7 @@ def load_syn_tool(tool_name): ...@@ -19,6 +20,7 @@ def load_syn_tool(tool_name):
'quartus': ToolQuartus, 'quartus': ToolQuartus,
'diamond': ToolDiamond, 'diamond': ToolDiamond,
'libero': ToolLibero, 'libero': ToolLibero,
'liberosoc': ToolLiberoSoC,
'icestorm': ToolIcestorm} 'icestorm': ToolIcestorm}
if tool_name in available_tools: if tool_name in available_tools:
logging.debug("Synthesis tool to be used found: %s", tool_name) logging.debug("Synthesis tool to be used found: %s", tool_name)
......
hdlmake/tools/makefilesyn.py
View file @ 84fd1ac8
...@@ -154,7 +154,7 @@ endif""") ...@@ -154,7 +154,7 @@ endif""")
{0}: {1} {0}.tcl {0}: {1} {0}.tcl
\t\t$(SYN_PRE_{2}_CMD) \t\t$(SYN_PRE_{2}_CMD)
\t\t$(TCL_INTERPRETER) $@.tcl \t\t$(TCL_INTERPRETER)$@.tcl
\t\t$(SYN_POST_{2}_CMD) \t\t$(SYN_POST_{2}_CMD)
\t\t{4} $@ \t\t{4} $@
""".format(stage, stage_previous, stage.upper(), """.format(stage, stage_previous, stage.upper(),
......
tests/counter/syn/igloo2_libero/verilog/Manifest.py 0 → 100644
View file @ 84fd1ac8
target = "microsemi"
syn_tool = "liberosoc"
action = "synthesis"
language = "verilog"
syn_family = "IGLOO2"
syn_device = "M2GL060"
syn_grade = "-1"
syn_package = "484 FBGA"
syn_top = "igloo2_top"
syn_project = "demo"
modules = {
"local" : [ "../../../top/igloo2/verilog" ],
}
tests/counter/syn/igloo2_libero/vhdl/Manifest.py 0 → 100644
View file @ 84fd1ac8
target = "microsemi"
syn_tool = "liberosoc"
action = "synthesis"
language = "vhdl"
syn_family = "IGLOO2"
syn_device = "M2GL060"
syn_grade = "-1"
syn_package = "484 FBGA"
syn_top = "igloo2_top"
syn_project = "demo"
modules = {
"local" : [ "../../../top/igloo2/vhdl" ],
}
tests/counter/top/igloo2/igloo2_top.pdc 0 → 100644
View file @ 84fd1ac8
# Microsemi Physical design constraints file
# Family: IGLOO2, Die: M2GL060, Package: 484 FBGA, Speed grade: -1
#
# IO banks setting
#
set_iobank Bank2 -vcci 3.3 -fixed yes
set_iobank Bank4 -vcci 3.3 -fixed no
set_iobank Bank5 -vcci 3.3 -fixed yes
set_iobank Bank6 -vcci 3.3 -fixed yes
set_iobank Bank9 -vcci 3.3 -fixed yes
#
# I/O constraints
#
set_io led_o\[0\] -iostd LVTTL -pinname G3 -fixed yes -direction OUTPUT
set_io led_o\[1\] -iostd LVTTL -pinname H3 -fixed yes -direction OUTPUT
set_io led_o\[2\] -iostd LVTTL -pinname H1 -fixed yes -direction OUTPUT
set_io led_o\[3\] -iostd LVTTL -pinname G1 -fixed yes -direction OUTPUT
set_io led_o\[4\] -iostd LVTTL -pinname H4 -fixed yes -direction OUTPUT
set_io led_o\[5\] -iostd LVTTL -pinname H5 -fixed yes -direction OUTPUT
set_io led_o\[6\] -iostd LVTTL -pinname H6 -fixed yes -direction OUTPUT
set_io led_o\[7\] -iostd LVTTL -pinname J1 -fixed yes -direction OUTPUT
set_io clear_i -iostd LVTTL -pinname B1 -fixed yes
set_io count_i -iostd LVTTL -pinname C1 -fixed yes
# 40MHz clock
set_io clock_i -iostd LVTTL -pinname J20 -fixed yes
tests/counter/top/igloo2/igloo2_top.sdc 0 → 100644
View file @ 84fd1ac8
# Top Level Design Parameters
# Clocks
create_clock -name {clock_i} -period 25 -waveform {0 12.5 } [ get_ports { clock_i } ]
# False Paths Between Clocks
# False Path Constraints
# Maximum Delay Constraints
# Multicycle Constraints
# Virtual Clocks
# Output Load Constraints
# Driving Cell Constraints
# Wire Loads
# set_wire_load_mode top
# Other Constraints
tests/counter/top/igloo2/verilog/Manifest.py 0 → 100644
View file @ 84fd1ac8
files = [
"igloo2_top.v",
"../igloo2_top.pdc",
"../igloo2_top.sdc",
]
modules = {
"local" : [ "../../../modules/counter/verilog" ],
}
tests/counter/top/igloo2/verilog/igloo2_top.v 0 → 100644
View file @ 84fd1ac8
//---------------------------------------------------------------------
// Design : Counter verilog top module, Microsemi IGLOO2 M2GL060
// Author : Javier D. Garcia-Lasheras, small changes by Severin Haas
//---------------------------------------------------------------------
module igloo2_top (
clear_i,
count_i,
clock_i,
led_o
);
input clear_i, count_i, clock_i;
output [7:0] led_o;
wire s_clock, s_clear, s_count;
wire [7:0] s_Q;
counter u1(
.clock(s_clock),
.clear(s_clear),
.count(s_count),
.Q(s_Q)
);
assign s_clock = clock_i;
assign s_clear = clear_i;
assign s_count = count_i;
assign led_o[7:0] = s_Q[7:0];
endmodule
tests/counter/top/igloo2/vhdl/Manifest.py 0 → 100644
View file @ 84fd1ac8
files = [
"igloo2_top.vhd",
"../igloo2_top.pdc",
"../igloo2_top.sdc",
]
modules = {
"local" : [ "../../../modules/counter/vhdl" ],
}
tests/counter/top/igloo2/vhdl/igloo2_top.vhd 0 → 100644
View file @ 84fd1ac8
-----------------------------------------------------------------------
-- Design : Counter VHDL top module, adopted for IGLOO2 M2GL060
-- Author : Javier D. Garcia-Lasheras, small changes by Severin Haas
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity igloo2_top is
port (
clear_i: in std_logic;
count_i: in std_logic;
clock_i: in std_logic;
led_o: out std_logic_vector(7 downto 0)
);
end igloo2_top;
-----------------------------------------------------------------------
architecture structure of igloo2_top is
component counter
port (
clock: in std_logic;
clear: in std_logic;
count: in std_logic;
Q: out std_logic_vector(7 downto 0)
);
end component;
signal s_clock: std_logic;
signal s_clear: std_logic;
signal s_count: std_logic;
signal s_Q: std_logic_vector(7 downto 0);
begin
U_counter: counter
port map (
clock => s_clock,
clear => s_clear,
count => s_count,
Q => s_Q
);
s_clock <= clock_i;
s_clear <= clear_i;
s_count <= count_i;
led_o <= s_Q;
end architecture structure;
----------------------------------------------------------------
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