Update the VHDL counter test

parent feff4994
...@@ -11,6 +11,8 @@ use ieee.numeric_std.all; ...@@ -11,6 +11,8 @@ use ieee.numeric_std.all;
entity counter is entity counter is
generic (cycles_per_second : unsigned := 12000000);
port( port(
clock: in std_logic; clock: in std_logic;
clear: in std_logic; clear: in std_logic;
...@@ -22,19 +24,28 @@ end counter; ...@@ -22,19 +24,28 @@ end counter;
------------------------------------------------------- -------------------------------------------------------
architecture behv of counter is architecture behv of counter is
signal ready: std_logic;
signal Pre_Q: unsigned(7 downto 0); signal Pre_Q: unsigned(7 downto 0);
signal divider: unsigned(23 downto 0);
begin begin
process(clock, count, clear) process(clock, count, clear)
begin begin
if clear = '1' then if (clock='1' and clock'event) then
Pre_Q <= "00000000"; if ready = '1' then
elsif (clock='1' and clock'event) then if divider = cycles_per_second then
if count = '1' then divider <= (others => '0');
Pre_Q <= Pre_Q + 1; Pre_Q(7 downto 1) <= Pre_Q(6 downto 0);
end if; Pre_Q(0) <= Pre_Q(7);
else
divider <= divider + 1;
end if;
else
ready <= '1';
Pre_Q <= "00010001";
divider <= (others => '0');
end if;
end if; end if;
end process; end process;
......
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