From 7feedf4d11624810fe5918af9aed8b2d4d14eb71 Mon Sep 17 00:00:00 2001
From: Javier Garcia <jgarcia@gl-research.com>
Date: Fri, 10 Mar 2017 09:44:06 +0100
Subject: [PATCH] Update the VHDL counter test

---
 .../counter/modules/counter/vhdl/counter.vhd  | 25 +++++++++++++------
 1 file changed, 18 insertions(+), 7 deletions(-)

diff --git a/tests/counter/modules/counter/vhdl/counter.vhd b/tests/counter/modules/counter/vhdl/counter.vhd
index d196f0f..128aa5e 100644
--- a/tests/counter/modules/counter/vhdl/counter.vhd
+++ b/tests/counter/modules/counter/vhdl/counter.vhd
@@ -11,6 +11,8 @@ use ieee.numeric_std.all;
 
 entity counter is
 
+generic (cycles_per_second : unsigned := 12000000);
+
 port(	
     clock:  in std_logic;
     clear:  in std_logic;
@@ -22,19 +24,28 @@ end counter;
 -------------------------------------------------------
 
 architecture behv of counter is		 	  
-	
+    signal ready: std_logic;
     signal Pre_Q: unsigned(7 downto 0);
+    signal divider: unsigned(23 downto 0);
 
 begin
 
     process(clock, count, clear)
     begin
-	if clear = '1' then
- 	    Pre_Q <= "00000000";
-	elsif (clock='1' and clock'event) then
-	    if count = '1' then
-			Pre_Q <= Pre_Q + 1;
-	    end if;
+	if (clock='1' and clock'event) then
+            if ready = '1' then
+                if divider = cycles_per_second then
+                    divider <= (others => '0');
+                    Pre_Q(7 downto 1) <= Pre_Q(6 downto 0);
+                    Pre_Q(0) <= Pre_Q(7);
+                else
+                    divider <= divider + 1;
+                end if;
+            else
+                ready <= '1';
+                Pre_Q <= "00010001";
+                divider <= (others => '0');
+            end if;
 	end if;
     end process;
 	
-- 
2.18.1