Commit 775fa73d authored by Tristan Gingold's avatar Tristan Gingold remove duplicated attribute (file_path vs path).

parent 573ef26e
......@@ -142,10 +142,9 @@ class DepFile(File):
"""Class that serves as base to all those HDL files that can be
parsed and solved (Verilog, SystemVerilog, VHDL)"""
def __init__(self, file_path, module):
assert isinstance(file_path, six.string_types)
File.__init__(self, path=file_path, module=module)
self.file_path = file_path
def __init__(self, path, module):
assert isinstance(path, six.string_types)
File.__init__(self, path=path, module=module)
self.rels = set()
self.depends_on = set()
self.dep_level = None
......@@ -181,5 +180,5 @@ class DepFile(File):
logging.warning("Probably run into a circular reference of file "
"dependencies. It appears %s depends on itself, "
"indirectly via atleast one other file.",
return self.dep_level
......@@ -116,7 +116,7 @@ def make_dependency_sorted_list(fileset):
All files that another depends on will be earlier in the list."""
dependable = [f for f in fileset if isinstance(f, DepFile)]
non_dependable = [f for f in fileset if not isinstance(f, DepFile)]
dependable.sort(key=lambda f: f.file_path.lower())
dependable.sort(key=lambda f: f.path.lower())
# Not necessary, but will tend to group files more nicely
# in the output.
......@@ -44,7 +44,7 @@ class SourceFile(DepFile):
self.library = library
if not library:
self.library = "work"
DepFile.__init__(self, file_path=path, module=module)
DepFile.__init__(self, path=path, module=module)
def __hash__(self):
return hash(self.path + self.library)
......@@ -42,16 +42,15 @@ class VHDLParser(DepParser):
"""Parse the provided VHDL file and add the detected relations to it"""
from .dep_file import DepRelation
assert not dep_file.is_parsed
logging.debug("Parsing %s", dep_file.path)
def _preprocess(vhdl_file):
"""Preprocess the supplied VHDL file instance"""
file_path = vhdl_file.file_path
buf = open(file_path, "r").read()
buf = open(vhdl_file.path, "r").read()
"preprocess file %s (of length %d) in library %s",
file_path, len(buf), vhdl_file.library)
vhdl_file.path, len(buf), vhdl_file.library)
# Remove the comments and strings from the VHDL code
pattern = re.compile('--.*?$|".?"', re.DOTALL | re.MULTILINE)
return re.sub(pattern, "", buf)
......@@ -78,7 +78,7 @@ class VerilogPreprocessor(object):
if os.path.isfile(probable_file):
return os.path.abspath(probable_file)
raise Exception("Can't find {} for {} in any of the include "
"directories: {}".format(filename, self.vlog_file.file_path,
"directories: {}".format(filename, self.vlog_file.path,
', '.join(self.vlog_file.include_dirs)))
def _preprocess_file(self, file_content, file_name, library):
......@@ -242,10 +242,9 @@ class VerilogPreprocessor(object):
# assert isinstance(vlog_file, VerilogFile)
# assert isinstance(vlog_file, DepFile)
self.vlog_file = vlog_file
file_path = vlog_file.file_path
buf = open(file_path, "r").read()
buf = open(vlog_file.path, "r").read()
return self._preprocess_file(file_content=buf,
......@@ -108,7 +108,7 @@ TOP_MODULE := {top_module}
if isinstance(file_aux, tuple(self.HDL_FILES)):
self.write("{}: {}".format(self.get_stamp_file(file_aux), file_aux.rel_path()))
# list dependencies, do not include the target file
for dep_file in sorted(file_aux.depends_on, key=(lambda x: x.file_path)):
for dep_file in sorted(file_aux.depends_on, key=(lambda x: x.path)):
if dep_file is file_aux:
# Do not depend on itself.
......@@ -138,7 +138,7 @@ class MakefileVsim(MakefileSim):
# list dependencies, do not include the target file
for dep_file in sorted([dfile for dfile
in vlog.depends_on if dfile is not vlog],
key=(lambda x: x.file_path)):
key=(lambda x: x.path)):
if dep_file in fileset and not dep_file.is_include:
name = dep_file.purename
extension = dep_file.extension()
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