Improve coding style at srcfile package

parent 2bf4b530
......@@ -142,8 +142,7 @@ class ModuleCore(ModuleConfig):
Build a Source File Set containing the files indicated by the
provided list of paths
"""
from hdlmake.srcfile import SourceFileFactory, SourceFileSet
sff = SourceFileFactory()
from hdlmake.srcfile import create_source_file, SourceFileSet
srcs = SourceFileSet()
for path_aux in paths:
if os.path.isdir(path_aux):
......@@ -151,11 +150,11 @@ class ModuleCore(ModuleConfig):
for f_dir in dir_:
f_dir = os.path.join(self.path, path_aux, f_dir)
if not os.path.isdir(f_dir):
srcs.add(sff.new(path=f_dir,
module=self,
library=self.library))
srcs.add(create_source_file(path=f_dir,
module=self,
library=self.library))
else:
srcs.add(sff.new(path=path_aux,
srcs.add(create_source_file(path=path_aux,
module=self,
library=self.library))
return srcs
This diff is collapsed.
......@@ -33,7 +33,7 @@ import logging
from .new_dep_solver import DepParser
from .dep_file import DepRelation
from .srcfile import SourceFileFactory
from hdlmake.srcfile import create_source_file
class VerilogPreprocessor(object):
......@@ -576,10 +576,8 @@ class VerilogParser(DepParser):
dep_file.path + dep_file.library]
for file_aux in includes:
dep_file.depends_on.add(
SourceFileFactory(
).new(
path=file_aux,
module=dep_file.module))
create_source_file(path=file_aux,
module=dep_file.module))
logging.debug("%s has %d includes.",
str(dep_file), len(includes))
except KeyError:
......
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