Commit 6de42805 authored by Tristan Gingold's avatar Tristan Gingold

Add a test for libraries.

parent 65332188
...@@ -100,7 +100,7 @@ class MakefileVsim(MakefileSim): ...@@ -100,7 +100,7 @@ class MakefileVsim(MakefileSim):
('+'.join(self.manifest_dict.get("include_dirs")))) ('+'.join(self.manifest_dict.get("include_dirs"))))
libs = set(f.library for f in fileset) libs = set(f.library for f in fileset)
self.write('LIBS := ') self.write('LIBS := ')
self.write(' '.join(libs)) self.write(' '.join(sorted(libs)))
self.write('\n') self.write('\n')
# tell how to make libraries # tell how to make libraries
self.write('LIB_IND := ') self.write('LIB_IND := ')
......
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := gate3
MODELSIM_INI_PATH := $(HDLMAKE_MODELSIM_PATH)/..
VCOM_FLAGS := -quiet -modelsimini modelsim.ini
VSIM_FLAGS :=
VLOG_FLAGS := -quiet -modelsimini modelsim.ini
VMAP_FLAGS := -modelsimini modelsim.ini
#target for performing local simulation
local: sim_pre_cmd simulation sim_post_cmd
VERILOG_SRC :=
VERILOG_OBJ :=
VHDL_SRC := gate3.vhd \
../files/gate.vhdl \
VHDL_OBJ := work/gate3/.gate3_vhd \
sublib/gate/.gate_vhdl \
INCLUDE_DIRS :=
LIBS := sublib work
LIB_IND := sublib/.sublib work/.work
simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ) : modelsim.ini
$(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
cp $< . 2>&1
sublib/.sublib:
(vlib sublib && vmap $(VMAP_FLAGS) sublib && touch sublib/.sublib )|| rm -rf sublib
work/.work:
(vlib work && vmap $(VMAP_FLAGS) work && touch work/.work )|| rm -rf work
work/gate3/.gate3_vhd: gate3.vhd \
sublib/gate/.gate_vhdl
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
sublib/gate/.gate_vhdl: ../files/gate.vhdl
vcom $(VCOM_FLAGS) -work sublib $<
@mkdir -p $(dir $@) && touch $@
# USER SIM COMMANDS
sim_pre_cmd:
sim_post_cmd:
CLEAN_TARGETS := $(LIBS) modelsim.ini transcript
clean:
rm -rf $(CLEAN_TARGETS)
mrproper: clean
rm -rf *.vcd *.wlf
.PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation
action = "simulation"
sim_tool="modelsim"
sim_path="fake_bin"
top_module = "gate3"
files = [ "gate3.vhd" ]
modules = { 'local': 'gates'}
library sublib;
entity gate3 is
port (i : in bit;
o : out bit);
end gate3;
architecture behav of gate3 is
begin
inst: entity sublib.gate
port map (i, o);
end behav;
library = 'sublib'
files = [ '../../files/gate.vhdl']
...@@ -487,6 +487,9 @@ def test_err_missing_module(): ...@@ -487,6 +487,9 @@ def test_err_missing_module():
run([], path="090missing_module") run([], path="090missing_module")
assert False assert False
def test_library():
run_compare(path="091library")
@pytest.mark.xfail @pytest.mark.xfail
def test_xfail(): def test_xfail():
"""This is a self-consistency test: the test is known to fail""" """This is a self-consistency test: the test is known to fail"""
......
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