Commit 67cfd90b authored by Tristan Gingold's avatar Tristan Gingold

module.py: reorder and add tests.

parent 903d3803
...@@ -129,6 +129,23 @@ class Module(object): ...@@ -129,6 +129,23 @@ class Module(object):
logging.debug("Module %s (parent: %s) is NOT fetched.", logging.debug("Module %s (parent: %s) is NOT fetched.",
url, self.parent.path) url, self.parent.path)
def process_manifest(self):
"""Process the content section of the manifest_dict"""
logging.debug("Process manifest at: " + os.path.dirname(self.path))
self._process_manifest_universal()
self._process_manifest_files()
self._process_manifest_modules()
self._process_manifest_makefiles()
def _process_manifest_universal(self):
"""Method processing the universal manifest directives;
set library (inherited if not set)."""
# Libraries
if "library" in self.manifest_dict:
self.library = self.manifest_dict["library"]
elif self.parent:
self.library = self.parent.library
def _check_filepath(self, filepath): def _check_filepath(self, filepath):
"""Check the provided filepath against several conditions""" """Check the provided filepath against several conditions"""
if filepath: if filepath:
...@@ -150,23 +167,6 @@ class Module(object): ...@@ -150,23 +167,6 @@ class Module(object):
self.path, filepath) self.path, filepath)
return True return True
def process_manifest(self):
"""Process the content section of the manifest_dict"""
logging.debug("Process manifest at: " + os.path.dirname(self.path))
self._process_manifest_universal()
self._process_manifest_files()
self._process_manifest_modules()
self._process_manifest_makefiles()
def _process_manifest_universal(self):
"""Method processing the universal manifest directives;
set library (inherited if not set)."""
# Libraries
if "library" in self.manifest_dict:
self.library = self.manifest_dict["library"]
elif self.parent:
self.library = self.parent.library
def _make_list_of_paths(self, list_of_paths): def _make_list_of_paths(self, list_of_paths):
"""Get a list with only the valid absolute paths from the provided""" """Get a list with only the valid absolute paths from the provided"""
paths = [] paths = []
...@@ -211,17 +211,19 @@ class Module(object): ...@@ -211,17 +211,19 @@ class Module(object):
"""Process the files instantiated by the HDLMake module""" """Process the files instantiated by the HDLMake module"""
from ..sourcefiles.sourcefileset import SourceFileSet from ..sourcefiles.sourcefileset import SourceFileSet
# HDL files provided by the module # HDL files provided by the module
if "files" not in self.manifest_dict: files = self.manifest_dict.get('files')
if files is None:
self.files = SourceFileSet() self.files = SourceFileSet()
logging.debug("No files in the manifest at %s", self.path or '?') logging.debug("No files in the manifest at %s", self.path or '?')
else: else:
self.manifest_dict["files"] = path_mod.flatten_list( # Be sure it is a list.
self.manifest_dict["files"]) files = path_mod.flatten_list(files)
self.manifest_dict["files"] = files
logging.debug("Files in %s: %s to library %s" , logging.debug("Files in %s: %s to library %s" ,
self.path, self.path,
str(self.manifest_dict["files"]), str(self.manifest_dict["files"]),
self.library) self.library)
paths = self._make_list_of_paths(self.manifest_dict["files"]) paths = self._make_list_of_paths(files)
self.files = self._create_file_list_from_paths(paths=paths) self.files = self._create_file_list_from_paths(paths=paths)
def fetchto(self): def fetchto(self):
......
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := gate
MODELSIM_INI_PATH := $(HDLMAKE_MODELSIM_PATH)/..
VCOM_FLAGS := -quiet -modelsimini modelsim.ini
VSIM_FLAGS :=
VLOG_FLAGS := -quiet -modelsimini modelsim.ini
VMAP_FLAGS := -modelsimini modelsim.ini
#target for performing local simulation
local: sim_pre_cmd simulation sim_post_cmd
VERILOG_SRC :=
VERILOG_OBJ :=
VHDL_SRC := ../files/gate.vhdl \
VHDL_OBJ := work/gate/.gate_vhdl \
INCLUDE_DIRS :=
LIBS := work
LIB_IND := work/.work
simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ) : modelsim.ini
$(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
cp $< . 2>&1
work/.work:
(vlib work && vmap $(VMAP_FLAGS) work && touch work/.work )|| rm -rf work
work/gate/.gate_vhdl: ../files/gate.vhdl
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
# USER SIM COMMANDS
sim_pre_cmd:
sim_post_cmd:
CLEAN_TARGETS := $(LIBS) modelsim.ini transcript
clean:
rm -rf $(CLEAN_TARGETS)
mrproper: clean
rm -rf *.vcd *.wlf
.PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation
action = "simulation"
sim_tool="modelsim"
sim_path="fake_bin"
top_module = "gate"
files = [ "/ignore/abs/file.vhdl", "../files/gate.vhdl" ]
action = "simulation"
sim_tool="modelsim"
sim_path="fake_bin"
top_module = "gate"
files = [ "missing_gate.vhdl" ]
...@@ -474,6 +474,14 @@ def test_err_ise_no_family(): ...@@ -474,6 +474,14 @@ def test_err_ise_no_family():
def test_many_modules(): def test_many_modules():
run_compare(path="087many_modules") run_compare(path="087many_modules")
def test_file_abs():
run_compare(path="088bad_file_abs")
def test_err_missing_file():
with pytest.raises(SystemExit) as _:
run([], path="089missing_file")
assert False
@pytest.mark.xfail @pytest.mark.xfail
def test_xfail(): def test_xfail():
"""This is a self-consistency test: the test is known to fail""" """This is a self-consistency test: the test is known to fail"""
......
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