Commit 62de78de authored by Will Kamp's avatar Will Kamp

Fixing false positive missing relation warnings.

Instances can be created without generic maps or port maps, in the form LABEL : entity. The existing regex captures these, but also finds false positives in component, record, and function definition sections, such as generic_name : natrual. new_dep_solver then compains that work.natural is not satisfied by any source file.
This commit creates regex patterns for component, function, and record definitions to remove them from the input buffer strings. The buf variable is reassigned after each re.sub call, to affect the removal.
Replacement strings are added to the buf, when a regex has matched - to help with debugging.
Finally, re.subn() replaced with re.sub() for simplicity.
parent c79d7b83
......@@ -71,28 +71,31 @@ class VHDLParser(DepParser):
else :
logging.debug("use package %s.%s" % (s.group(1), s.group(2)) )
dep_file.add_relation(DepRelation("%s.%s" % (s.group(1).lower(), s.group(2).lower()), DepRelation.USE, DepRelation.PACKAGE))
re.subn(use_pattern, do_use, buf)
return "<hdlmake use_pattern %s.%s>" % (s.group(1), s.group(2))
buf = re.sub(use_pattern, do_use, buf)
#new entity
entity_pattern = re.compile("^\s*entity\s+(\w+)\s+is\s+(?:port|generic|end)", re.DOTALL | re.MULTILINE | re.IGNORECASE )
entity_pattern = re.compile("^\s*entity\s+(?P<name>\w+)\s+is\s+(?:port|generic|end).*?(?P=name)\s*;", re.DOTALL | re.MULTILINE | re.IGNORECASE )
def do_entity(s) :
logging.debug("found entity %s.%s" % ( dep_file.library, s.group(1) ) )
dep_file.add_relation(DepRelation("%s.%s" % (dep_file.library, s.group(1).lower()),
DepRelation.PROVIDE,
DepRelation.ENTITY))
re.subn(entity_pattern, do_entity, buf)
return "<hdlmake entity_pattern %s.%s>" % (dep_file.library, s.group(1))
buf = re.sub(entity_pattern, do_entity, buf)
#new architecture
architecture_pattern = re.compile("^\s*architecture\s+(\w+)\s+of\s+(\w+)\s+is", re.DOTALL | re.MULTILINE | re.IGNORECASE )
def do_architecture(s) :
logging.debug("found architecture %s of entity %s.%s" % ( s.group(1), dep_file.library, s.group(2) ) )
dep_file.add_relation(DepRelation("%s.%s" % (dep_file.library, s.group(2).lower()),
DepRelation.USE,
DepRelation.ENTITY))
dep_file.add_relation(DepRelation("%s.%s" % (dep_file.library, s.group(2).lower()),
DepRelation.PROVIDE,
DepRelation.ARCHITECTURE))
re.subn(architecture_pattern, do_architecture, buf)
dep_file.add_relation(DepRelation("%s.%s" % (dep_file.library, s.group(2).lower()),
DepRelation.USE,
DepRelation.ENTITY))
return "<hdlmake architecture %s.%s>" % (dep_file.library, s.group(2))
buf = re.sub(architecture_pattern, do_architecture, buf)
#new package
package_pattern = re.compile("^\s*package\s+(\w+)\s+is", re.DOTALL | re.MULTILINE | re.IGNORECASE )
......@@ -101,11 +104,33 @@ class VHDLParser(DepParser):
dep_file.add_relation(DepRelation("%s.%s" % (dep_file.library, s.group(1).lower()),
DepRelation.PROVIDE,
DepRelation.PACKAGE))
re.subn(package_pattern, do_package, buf)
return "<hdlmake package %s.%s>" % (dep_file.library, s.group(1))
buf = re.sub(package_pattern, do_package, buf)
#component declaration
component_pattern = re.compile("^\s*component\s+(\w+).*?end\s+component.*?;", re.DOTALL | re.MULTILINE | re.IGNORECASE )
def do_component(s):
logging.debug("found component declaration %s" % s.group(1))
return "<hdlmake component %s>" % s.group(1)
buf = re.sub(component_pattern, do_component, buf)
#record declaration
record_pattern = re.compile("^\s*type\s+(\w+)\s+is\s+record.*?end\s+record.*?;", re.DOTALL | re.MULTILINE | re.IGNORECASE )
def do_record(s):
logging.debug("found record declaration %s" % s.group(1))
return "<hdlmake record %s>" % s.group(1)
buf = re.sub(record_pattern, do_record, buf)
#function declaration
function_pattern = re.compile("^\s*function\s+(\w+).*?return.*?(?:is|;)", re.DOTALL | re.MULTILINE | re.IGNORECASE )
def do_function(s):
logging.debug("found function declaration %s" % s.group(1))
return "<hdlmake function %s>" % s.group(1)
buf = re.sub(function_pattern, do_function, buf)
#intantions
instance_pattern = re.compile("^\s*(\w+)\s*\:\s*(\w+)\s*(?:port\s+map|generic\s+map|\s*;)", re.DOTALL | re.MULTILINE | re.IGNORECASE )
instance_from_library_pattern = re.compile("^\s*(\w+)\s*\:\s*entity\s*(\w+)\s*\.\s*(\w+)\s*(?:port\s+map|generic\s+map|\s*;)", re.DOTALL | re.MULTILINE | re.IGNORECASE )
instance_pattern = re.compile("^\s*(\w+)\s*\:\s*(\w+)\s*(?:port\s+map.*?;|generic\s+map.*?;|\s*;)", re.DOTALL | re.MULTILINE | re.IGNORECASE )
instance_from_library_pattern = re.compile("^\s*(\w+)\s*\:\s*entity\s*(\w+)\s*\.\s*(\w+)\s*(?:port\s+map.*?;|generic\s+map.*?;|\s*;)", re.DOTALL | re.MULTILINE | re.IGNORECASE )
libraries = set([dep_file.library])
def do_instance(s) :
for lib in libraries :
......@@ -113,6 +138,7 @@ class VHDLParser(DepParser):
dep_file.add_relation(DepRelation("%s.%s" % (lib, s.group(2).lower()),
DepRelation.USE,
DepRelation.ARCHITECTURE))
return "<hdlmake instance %s|%s>" % (s.group(1), s.group(2))
def do_instance_from_library(s) :
if ( s.group(2).lower() == "work" ) : #work is the current library in VHDL
logging.debug("-> instantiates %s.%s as %s" % (dep_file.library, s.group(3), s.group(1)) )
......@@ -124,13 +150,18 @@ class VHDLParser(DepParser):
dep_file.add_relation(DepRelation("%s.%s" % (s.group(2).lower(), s.group(3).lower()),
DepRelation.USE,
DepRelation.ARCHITECTURE))
re.subn(instance_pattern, do_instance, buf)
re.subn(instance_from_library_pattern, do_instance_from_library, buf)
return "<hdlmake instance_from_library %s|%s>" % (s.group(1), s.group(3))
buf = re.sub(instance_pattern, do_instance, buf)
buf = re.sub(instance_from_library_pattern, do_instance_from_library, buf)
#libraries
library_pattern = re.compile("^\s*library\s*(\w+)\s*;", re.DOTALL | re.MULTILINE | re.IGNORECASE )
def do_library(s) :
logging.debug("use library %s" % s.group(1))
libraries.add(s.group(1).lower())
re.subn(library_pattern, do_library, buf)
return "<hdlmake library %s>" % s.group(1)
buf = re.sub(library_pattern, do_library, buf)
#logging.debug("\n" + buf) # print modified buffer.
dep_file.is_parsed = True
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