Commit 5a293d83 authored by Adrian Fiergolski's avatar Adrian Fiergolski Committed by Javier D. Garcia-Lasheras

Test for UVM and SystemVerilog support on Questa

parent ae3eb417
*~
work
certe_dump.xml
modelsim.ini
transcript
vsim.wlf
The hdlmake should be called from: sim/tests/
\ No newline at end of file
include_dirs = "include"
files = "ipcore.sv"
// -*- Mode: Verilog -*-
// Filename : ipcoreInclude.sv
// Description : Example ipcoreinclude
// Author : Adrian Fiergolski
// Created On : Thu Sep 18 11:01:31 2014
// Last Modified By: Adrian Fiergolski
// Last Modified On: Thu Sep 18 11:01:31 2014
// Update Count : 0
// Status : Unknown, Use with caution!
module ipcoreInclude;
endmodule // ipcoreinclude
// -*- Mode: Verilog -*-
// Filename : ipcore.sv
// Description : Example ipcore
// Author : Adrian Fiergolski
// Created On : Thu Sep 18 11:00:12 2014
// Last Modified By: Adrian Fiergolski
// Last Modified On: Thu Sep 18 11:00:12 2014
// Update Count : 0
// Status : Unknown, Use with caution!
`include "ipcoreInclude.sv"
module ipcore;
ipcoreInclude incl();
endmodule // ipcore
/*****************************************************************************
*
* Copyright 2008 Mentor Graphics Corporation
* All Rights Reserved.
*
* THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
* MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
*
*****************************************************************************/
`ifdef MVC_NO_DEPRECATED
// This entire file is deprecated. Testbenches should no longer even include this file.
`__FILE__
`else
`include "uvm_macros.svh"
`define get_interface( _if ) _if
`define DEFINE_VIF_TYPE( IF_NAME ) virtual mgc_``IF_NAME
`define mvc_report_info( id , mess ) `uvm_info( id , mess , UVM_MEDIUM )
`define mvc_report_warning( id , mess ) `uvm_warning( id , mess )
`define mvc_report_error( id , mess ) `uvm_error( id , mess )
`define mvc_report_fatal( id , mess ) `uvm_fatal( id , mess )
`ifdef MODEL_TECH
`undef m_uvm_get_type_name_func
`define m_uvm_get_type_name_func(T) \
`uvm_get_type_name_func(T)
`define uvm_get_type_name_func(T) \
localparam string type_name = `"T`"; \
virtual function string get_type_name (); \
return type_name; \
endfunction
`define mvc_get_type_name_func( specialization ) \
localparam type_name = specialization; \
virtual function string get_type_name(); \
return type_name; \
endfunction \
//
// The name is a user supplied string unique to this specialization T of a parameterized class
//
`define mvc_object_param_utils( T , name ) \
`uvm_object_registry(T, name) \
`mvc_get_type_name_func( name ) \
`uvm_field_utils_begin(T) \
`uvm_object_utils_end
//
// The name is a user supplied string unique to this specialization T of a parameterized class
//
`define mvc_component_param_utils( T , name ) \
`uvm_component_registry(T, name) \
`mvc_get_type_name_func( name ) \
`uvm_field_utils_begin(T) \
`uvm_object_utils_end
`else
`define mvc_object_param_utils( T , name ) \
`uvm_object_param_utils( T )
`define mvc_component_param_utils( T , name ) \
`uvm_component_param_utils( T )
`endif
`endif
\ No newline at end of file
/*****************************************************************************
*
* Copyright 2007-2014 Mentor Graphics Corporation
* All Rights Reserved.
*
* THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
* MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
*
*****************************************************************************/
package mvc_pkg;
endpackage
include_dirs = "./include"
files = ["include/includeModule.sv",
"RTL_SVPackage.sv",
"RTLTopModuleSV.sv",
"RTLTopModuleVerilogSimulationModel.vo",
"RTLTopModuleVHDL.vhdl"]
modules = { "local" : ["../ipcores/ipcore"]}
// -*- Mode: Verilog -*-
// Filename : RTLTopModuleSV.sv
// Description : RTL top module (DUT).
// Author : Adrian Fiergolski
// Created On : Thu Sep 18 10:50:28 2014
// Last Modified By: Adrian Fiergolski
// Last Modified On: Thu Sep 18 10:50:28 2014
// Update Count : 0
// Status : Unknown, Use with caution!
module RTLTopModuleSV;
logic l1a;
initial
l1a <= RTL_SVPackage::CONST;
includeModule incl();
ipcore ip();
endmodule // RTLTopModuleSV
-------------------------------------------------------------------------------
-- Title : RTLTopModuleVHDL
-- Project :
-------------------------------------------------------------------------------
-- File : RTLTopModuleVHDL.vhdl
-- Author : Adrian Fiergolski <Adrian.Fiergolski@cern.ch>
-- Company : CERN
-- Created : 2014-09-26
-- Last update: 2014-09-26
-- Platform :
-- Standard : VHDL'2008
-------------------------------------------------------------------------------
-- Description: The module to test HDLMake
-------------------------------------------------------------------------------
-- Copyright (c) 2014 CERN
--
-- This file is part of .
--
-- is free firmware: you can redistribute it and/or modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation, either version 3 of the License, or any later version.
--
-- is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with . If not, see http://www.gnu.org/licenses/.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-09-26 1.0 afiergol Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity RTLTopModuleVHDL is
end entity RTLTopModuleVHDL;
architecture Behavioral of RTLTopModuleVHDL is
signal probe : STD_LOGIC;
begin -- architecture Behavioral
probe <= '1';
end architecture Behavioral;
module RTLTopModuleVerilogSimulationModel;
endmodule
package RTL_SVPackage;
localparam CONST = 0;
endpackage // RTL_SVPackage
// -*- Mode: Verilog -*-
// Filename : includeModule.sv
// Description : Included submodule
// Author : Adrian Fiergolski
// Created On : Thu Sep 18 10:51:41 2014
// Last Modified By: Adrian Fiergolski
// Last Modified On: Thu Sep 18 10:51:41 2014
// Update Count : 0
// Status : Unknown, Use with caution!
module includeModule;
endmodule // includeModule
// -*- Mode: Verilog -*-
// Filename : Env_pkg.sv
// Description : Package containing environment's components.
// Author : Adrian Fiergolski
// Created On : Thu Sep 18 10:48:26 2014
// Last Modified By: Adrian Fiergolski
// Last Modified On: Thu Sep 18 10:48:26 2014
// Update Count : 0
// Status : Unknown, Use with caution!
`ifndef ENG_PKG_SV
`define ENG_PKG_SV
`include <mvc_macros.svh>
`include <mvc_pkg.sv>
package Env_pkg;
import uvm_pkg::*;
`include <uvm_macros.svh>
`include "env.sv"
endpackage // Env_pkg
`endif
// -*- Mode: Verilog -*-
// Filename : env.sv
// Description : Example UVM environment
// Author : Adrian Fiergolski
// Created On : Thu Sep 18 11:04:56 2014
// Last Modified By: Adrian Fiergolski
// Last Modified On: Thu Sep 18 11:04:56 2014
// Update Count : 0
// Status : Unknown, Use with caution!
class env extends uvm_env;
`uvm_component_utils_begin(env)
`uvm_component_utils_end
//Function: new
//Creates a new <env> with the given ~name~ and ~parent~.
function new(string name="", uvm_component parent);
super.new(name, parent);
endfunction // new
endclass // env
// -*- Mode: Verilog -*-
// Filename : top.sv
// Description : Top simulation module.
// Author : Adrian Fiergolski
// Created On : Thu Sep 18 10:47:27 2014
// Last Modified By: Adrian Fiergolski
// Last Modified On: Thu Sep 18 10:47:27 2014
// Update Count : 0
// Status : Unknown, Use with caution!
module automatic top;
timeunit 1ns;
timeprecision 1ps;
RTLTopModuleSV sv();
RTLTopModuleVHDL vhdl();
RTLTopModuleVerilogSimulationModel vsm();
initial
run_test("genericTest");
endmodule // top
// -*- Mode: Verilog -*-
// Filename : sequence.sv
// Description : An example sequence item.
// Author : Adrian Fiergolski
// Created On : Thu Sep 18 10:47:00 2014
// Last Modified By: Adrian Fiergolski
// Last Modified On: Thu Sep 18 10:47:00 2014
// Update Count : 0
// Status : Unknown, Use with caution!
class sequenceA extends uvm_sequence_item;
`uvm_object_utils_begin(sequenceA)
`uvm_object_utils_end
//Function: new
//Creates a new <sequenceA> with the given ~name~..
function new(string name="");
super.new(name);
endfunction // new
endclass // sequenceA
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
## variables #############################
PWD := $(shell pwd)
MODELSIM_INI_PATH := /opt/questa_sv_afv_10.3c_1/questasim//bin/..
VCOM_FLAGS := -quiet -modelsimini modelsim.ini
VSIM_FLAGS :=
VLOG_FLAGS := -quiet -modelsimini modelsim.ini
VERILOG_SRC := ../../rtl/RTL_SVPackage.sv \
../../rtl/include/includeModule.sv \
../../ipcores/ipcore/ipcore.sv \
../../rtl/RTLTopModuleSV.sv \
../../rtl/RTLTopModuleVerilogSimulationModel.vo \
src/genericTest.sv \
VERILOG_OBJ := work/RTL_SVPackage/.RTL_SVPackage_sv \
work/includeModule/.includeModule_sv \
work/ipcore/.ipcore_sv \
work/RTLTopModuleSV/.RTLTopModuleSV_sv \
work/RTLTopModuleVerilogSimulationModel/.RTLTopModuleVerilogSimulationModel_vo \
work/genericTest/.genericTest_sv \
VHDL_SRC := ../../rtl/RTLTopModuleVHDL.vhdl \
VHDL_OBJ := work/RTLTopModuleVHDL/.RTLTopModuleVHDL_vhdl \
LIBS := work
LIB_IND := work/.work
## rules #################################
sim: sim_pre_cmd modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ): $(VHDL_OBJ)
$(VHDL_OBJ): $(LIB_IND) modelsim.ini
sim_pre_cmd:
sim_post_cmd: sim
modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
cp $< . 2>&1
clean:
rm -rf ./modelsim.ini $(LIBS)
.PHONY: clean sim_pre_cmd sim_post_cmd
work/.work:
(vlib work && vmap -modelsimini modelsim.ini work && touch work/.work )|| rm -rf work
work/RTL_SVPackage/.RTL_SVPackage_sv: ../../rtl/RTL_SVPackage.sv
vlog -work work $(VLOG_FLAGS) -sv +incdir+../../rtl/include+../../rtl $<
@mkdir -p $(dir $@) && touch $@
work/includeModule/.includeModule_sv: ../../rtl/include/includeModule.sv
vlog -work work $(VLOG_FLAGS) -sv +incdir+../../rtl/include+../../rtl/include $<
@mkdir -p $(dir $@) && touch $@
work/ipcore/.ipcore_sv: ../../ipcores/ipcore/ipcore.sv \
../../ipcores/ipcore/include/ipcoreInclude.sv
vlog -work work $(VLOG_FLAGS) -sv +incdir+../../ipcores/ipcore/include+../../ipcores/ipcore $<
@mkdir -p $(dir $@) && touch $@
work/RTLTopModuleSV/.RTLTopModuleSV_sv: ../../rtl/RTLTopModuleSV.sv \
work/RTL_SVPackage/.RTL_SVPackage_sv \
work/includeModule/.includeModule_sv \
work/ipcore/.ipcore_sv
vlog -work work $(VLOG_FLAGS) -sv +incdir+../../rtl/include+../../rtl $<
@mkdir -p $(dir $@) && touch $@
work/RTLTopModuleVerilogSimulationModel/.RTLTopModuleVerilogSimulationModel_vo: ../../rtl/RTLTopModuleVerilogSimulationModel.vo
vlog -work work $(VLOG_FLAGS) +incdir+../../rtl/include+../../rtl $<
@mkdir -p $(dir $@) && touch $@
work/genericTest/.genericTest_sv: src/genericTest.sv \
../sequences/sequence.sv \
../environment/Env_pkg.sv \
../environment/env.sv \
work/RTLTopModuleSV/.RTLTopModuleSV_sv \
work/RTLTopModuleVerilogSimulationModel/.RTLTopModuleVerilogSimulationModel_vo \
../environment/top.sv \
src/FullTest_pkg.sv
vlog -work work $(VLOG_FLAGS) -sv +incdir+../environment+../sequences+src +incdir+../../mvc//questa_mvc_src/sv+../../mvc/questa_mvc_src/sv/mvc_base+../../mvc/include+../../uvm-1.1d/src $<
@mkdir -p $(dir $@) && touch $@
work/RTLTopModuleVHDL/.RTLTopModuleVHDL_vhdl: ../../rtl/RTLTopModuleVHDL.vhdl
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
action = "simulation"
include_dirs = [ "../environment/",
"../sequences/"]
vlog_opt = '+incdir+' + \
'../../mvc//questa_mvc_src/sv+' + \
'../../mvc/questa_mvc_src/sv/mvc_base+' + \
'../../mvc/include+' +\
'../../uvm-1.1d/src'
top_module = "top"
sim_tool = "vsim"
files = ["src/genericTest.sv"]
modules = { "local" : ["../../rtl"] }
quit -sim
make
vsim -classdebug -uvmcontrol=all -msgmode both -t ps -novopt work.top
run -all
// -*- Mode: Verilog -*-
// Filename : FullTest_pkg.sv
// Description : The package contains custom sequences
// Author : Adrian Fiergolski
// Created On : Thu Sep 18 10:35:56 2014
// Last Modified By: Adrian Fiergolski
// Last Modified On: Thu Sep 18 10:35:56 2014
// Update Count : 0
// Status : Unknown, Use with caution!
`ifndef FULLTEST_PKG_SV
`define FULLTEST_PKG_SV
//Title: FullTest_pkg
//Package: FullTest_pkg
//The package contains sequences available for full tests.
package FullTest_pkg;
import uvm_pkg::*;
`include <uvm_macros.svh>
`include "sequence.sv"
endpackage // FullTest_pkg
`endif
// -*- Mode: Verilog -*-
// Filename : genericTest.sv
// Description : The generic test
// Author : Adrian Fiergolski
// Created On : Thu Sep 18 10:34:01 2014
// Last Modified By: Adrian Fiergolski
// Last Modified On: Thu Sep 18 10:34:01 2014
// Update Count : 0
// Status : Unknown, Use with caution!
timeunit 1ns;
timeprecision 1ps;
import uvm_pkg::*;
`include <uvm_macros.svh>
`include "Env_pkg.sv"
`include "FullTest_pkg.sv"
`include "top.sv"
import Env_pkg::*;
import FullTest_pkg::*;
//Class: genericTest
class genericTest extends uvm_test;
env i_env;
`uvm_component_utils_begin(genericTest)
`uvm_component_utils_end
//Function: new
//Creates a new <genericTest> with the given ~name~ and ~parent~.
function new(string name="", uvm_component parent);
super.new(name, parent);
endfunction // new
function void build_phase(uvm_phase phase);
super.build_phase(phase);
i_env = env::type_id::create("env", this);
endfunction
endclass // genericTest
Tue Aug 26 19:51:35 PDT 2014
This diff is collapsed.
=========================================================================
== NOTICE file corresponding to section 4(d) of the Apache License, ==
== Version 2.0, in this case for the Apache Geronimo distribution. ==
=========================================================================
=========================================================================
== UVM Mentor Graphics Notice ==
=========================================================================
Portions of the UVM Reference Library were developed by
Mentor Graphics Corporation.
Copyright (c) 2007-2012, Mentor Graphics Corporation
All rights reserved.
=========================================================================
== UVM Cadence Design Systems Notice ==
=========================================================================
Portions of the UVM Reference Library were developed by
Cadence Design Systems, Inc.
Copyright (c) 2007-2012, Cadence Design Systems, Inc.
All rights reserved.
=========================================================================
== UVM Synopsys Notice ==
=========================================================================
Portions of the UVM Reference Library were developed by
Synopsys, Inc.
Copyright (c) 2006-2012, Synopsys, Inc.
All rights reserved.
=========================================================================
== UVM Cypress Semiconductor Notice ==
=========================================================================
Portions of the UVM Reference Library were developed by
Cypress Semiconductor Corp.
Copyright (c) 2012, Cypress Semiconductor Corp.
All rights reserved.
Accellera Universal Verification Methodology
version 1.1c
(C) Copyright 2007-2012 Mentor Graphics Corporation
(C) Copyright 2007-2012 Cadence Design Systems, Incorporated
(C) Copyright 2006-2012 Synopsys Inc.
(C) Copyright 2012 Cypress Semiconductor Corp.
All Rights Reserved Worldwide
The UVM kit is licensed under the Apache-2.0 license. The full text of
the licese is provided in this kit in the file LICENSE.txt
Installing the kit
------------------
Installation of UVM requires first unpacking the kit in a convenient
location.
% mkdir path/to/convenient/location
% cd path/to/convenient/location
% gunzip -c path/to/UVM/distribution/tar.gz | tar xvf -
You should define the $UVM_HOME environment variable to that
convenient location using an absolute path name. The following
instructions assume that this variable is appropriately set.
% setenv UVM_HOME /absolute/path/to/convenient/location
You must then obtain from your SystemVerilog tool vendor a tool-specific
distribution overlay. That overlay may be specific to the machine
architecture and/or operating system you are using. Make sure you provide
the output of the '$UVM_HOME/bin/uvm_os_name' script as well as the version
of the simulator you are using when requesting a UVM overlay from your vendor.
% $UVM_HOME/bin/uvm_os_name
IUS: % irun -version
Questa: % vlog -version
VCS: % vcs -ID
Follow the installation instructions provided by your tool vendor for
installing the overlay in your UVM installation.
Note to EDA vendors: to support multiple tool-specific overlays in the
same UVM distribution, please locate any tool-specific files in a
tool-specific sub-directory.
Using the UVM
-------------
You must compile the file $UVM_HOME/src/uvm.sv first. You will need
to specify the location of $UVM_HOME/src as a include directory in your
compilation command line using the +incdir+ command-line option.
You can then make the UVM library accessible to your SystemVerilog
code by importing the package 'uvm_pkg' in the appropriate scope.
import uvm_pkg::*;
To use the UVM short-hand macros, it is necessary to include the file
"uvm_macros.svh". This will also necessitate that you specify the
location of $UVM_HOME/src as a include directory.
`include "uvm_macros.svh"
You will also need to compile the file $UVM_HOME/src/dpi/uvm_dpi.cc
and/or specify the location of the resulting UVM DPI shared library to
your simulator. This is a simulator-specific process. Please refer to
your simulator documentation.
Prerequisites
-------------
- IEEE1800 compliant SV simulator
- gmake-compliant make to execute Makefile based examples
- C compiler to compile the DPI code (if not otherwise provided by tool vendor)
Running the examples
--------------------
The examples assume the following steps to be completed:
- The Compiler/Simulator environment has been setup according to the vendors
instruction and you can execute compile/simulation on the commandline.
To run any of the examples:
1. change to the example dir (ex: cd examples/trivial)
2. execute "make -f Makefile.{ius|vcs|questa}" depending upon your simulator vendor to run the example.
The makefiles assume a gmake compiliant make tool.
optional:
- to see the commands and steps executed use "make -f Makefile.{ius|vcs|questa} -n"
- to run against an uvm installation in a different location override the makefile variable UVM_HOME
make -f Makefile.ius UVM_HOME=`ncroot`/tools/uvm
------------------------------------------------------------------------
eval 'exec perl -S $0 ${1+"$@"}'
if 0;
# -*- mode: cperl -*-
#----------------------------------------------------------------------
# Copyright 2007-2010 Cadence Design Systems, Inc.
# Copyright 2010-2011 Synopsys Inc.
# Copyright 2010 Mentor Graphics Corporation
# All Rights Reserved Worldwide
#
# Licensed under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in
# compliance with the License. You may obtain a copy of
# the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in
# writing, software distributed under the License is
# distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
# CONDITIONS OF ANY KIND, either express or implied. See
# the License for the specific language governing
# permissions and limitations under the License.
#----------------------------------------------------------------------
#use strict;
use warnings;
use Getopt::Long;
use File::Find;
use Cwd;
use Fcntl;
use File::Temp qw/tempfile tempdir/;
use File::Path;
use File::Copy;
use Data::Dumper;
use File::stat;
# Tar module may not be available
if (eval {require Archive::Tar; 1;}) {
$Tar_Pm = 1;
}
my @all_files=();
my %content=();
local $opt_marker="-*-";
local $opt_help;
local $opt_backup;
local $opt_write;
local $opt_tar_exec="tar";
# regexp to match sv files (can be overriden using --sv_ext)
local $opt_sv_ext="\.(s?vh?|inc)\$";
# regexp of mime types for files considered for a change with the --all option
local $text_file_mime_regexp="(text\/|application\/x-shellscript|regular file)";
# ignore pattern
local $file_ignore_pattern="(/(.hg|.git|INCA_libs|.daidir|.vdb|simv|csrc|DVEfiles)\/|[#~]\$|\.(zip|gz|bz2|orig|diff|patch)\$)";
my $VerID='-*- $Id: ovm2uvm.pl,v d60c9fc172de 2010/10/13 14:58:52 accellera $ -*-';
my @Options=(
["help","this help screen"],
["top_dir=s","the top directory name containing the files to translate"],
["backup","if specified make a backup of all files handled by the script"],
["write","really write the changed files back to disk (by default it runs in dry mode)"],
["marker=s", "use the marker supplied instead of the default marker [$opt_marker]"],
["sv_ext=s","a regexp matching all sv files default:[$opt_sv_ext]"],
["tar_exec=s","the script assume a gtar compatible tar, if your gtar compatible tar is not avail point to it via --tar_exec"]
);
if(!GetOptions(map ( @$_[0], @Options))) {
ErrorMessage("Error during option parsing");
}
if (defined $opt_help) { PrintUsage(@Options); exit(1);}
if(!$opt_top_dir) { $opt_top_dir= getcwd;}
$opt_top_dir =~ s/\/$//;
$DUMMY='-' x 80;
NoteMessage("$DUMMY");
NoteMessage("$VerID");
NoteMessage("traversing directory [$opt_top_dir] to find files");
NoteMessage("-*- this script requires a gtar compatible tar to make backups -*-");
search_all_relevant_files($opt_top_dir);
#
#
#
foreach my $file (@all_files) {
if($file =~ /${opt_sv_ext}/) {
print "handling sv [$file]\n";
$content{$file}=FixMantis3770($file);
} else {
print "skipping $file ...\n";
}
}
write_back_files(%content);
# determines if the file is one of requested mime types
sub matches_mime_type {
my($file) = @_;
my($mime)=qx{file -i $file};
if($mime =~ /:\s+${text_file_mime_regexp}/) {
return 1;
} else {
return 0;
}
}
# writes back the contents of the files
sub write_back_files {
my(%content)=@_;
# now write it back
my $tempdir=tempdir(CLEANUP => 1);
NoteMessage("writing file to new top_dir $tempdir");
foreach $f (keys %content) {
my($nfile)=$f;
$nfile=~ s/^$opt_top_dir/$tempdir/;
my ($volume,$directories,$file) = File::Spec->splitpath( $nfile );
mkpath($directories, 0);
open(OUT,">$nfile") || die("error opening $nfile fullfile:$f for write [$!]");
print OUT $content{$f};
close(OUT);
}
NoteMessage("the patch is avail as [Mantis3770_$$.patch] for inspection");
system("diff -r $opt_top_dir $tempdir > Mantis3770_$$.patch");
if($opt_backup) {
NoteMessage("making backup of current files before writing back in [Mantis3770_back_$$.tar.gz]");
if ($Tar_Pm) {
my $tar=Archive::Tar->new;
$tar->add_files(keys(%content));
$tar->write("Mantis3770_back_$$.tar.gz",COMPRESS_GZIP);
} else {
my($fh,$fname) = tempfile();
print $fh join("\n",keys(%content));
system "$opt_tar_exec cf - -T $fname | gzip -9v > Mantis3770_back_$$.tar.gz";
}
}
if($opt_write) {
NoteMessage("now writing back to changes");
foreach $f (keys %content) {
my($nfile)=$f;
$nfile=~ s/^$opt_top_dir//;
my($mod_nfile)=$nfile;
my($target)=$f;
my($source)=$f;
$source=~ s/^$opt_top_dir/$tempdir/;
if($mod_nfile ne $nfile) {
WarnMessage("filename of [$f]=top_dir[$opt_top_dir][$nfile] got changed, its now [$opt_top_dir][$mod_nfile]");
unlink $f;
$target=$opt_top_dir . $mod_nfile;
}
warn("target file $target is not writeable and in the way") if (-e $target && !(-w $target));
#NoteMessage("moving [$source] to [$target]");
move($source,$target);
}
}
}
sub search_all_relevant_files {
my ($dir) = @_;
finddepth({ wanted => \&pattern, no_chdir => 1 }, $dir);
}
sub fix_mantis_3770{
my($t,$fname) = @_;
$t =~ s/class\s+(\S+)\s+extends endclass//ge;
$t;
}
sub pattern {
my($filename)= $File::Find::name;
my($st) =stat($filename) || die "error: $filename: $!";
# print "[$filename][$st]";
# print Dumper($filename);
# print Dumper($st),"\n";
# NOTE directories are not handled (a directory ovm_bla has to be renamed manually)
return 0 if (-d $filename);
warn("file $filename is a link and may lead to strange results") if -l $filename;
return 0 if $filename =~ /${file_ignore_pattern}/;
# return unless $filename =~ /\.s?vh?$/;
# replace_string($filename);
push @all_files,$filename;
}
sub PrintUsage {
my(@Options)=@_;
while(<DATA>){
print $_;
}
my($txt);
print "supported transformations\n";
$txt = ReadFileAsText($0);
while($txt =~ /#\s+(FIX|MARKER|TODO)(.*?)\n/gs) {
print "action:$1\t\tdescription: $2\n";
}
print "\n\noptions:\n\n";
foreach $i (@Options) {
printf("\t--%-20s\t\t@$i[1]\n",@$i[0]);
}
}
sub FixMantis3770 {
my($FILENAME)=@_;
my(@FILES)=();
my($FILE,$TEXT,$CLASS,$NEW,$UVM_OBJECT,$_);
local(*INFILE);
# DebugMessage("1trying to read text-file [$FILENAME]");
$TEXT="";
foreach $FILE (glob($FILENAME)) {
# DebugMessage("2trying to read text-file [$FILE]");
open(INFILE,$FILE) || WarnMessage("can't open file [$FILE]");
undef $CLASS;
while ($_ = <INFILE>) {
if (m/class\s+(\S+)\b/) {
$CLASS = $1;
undef $NEW;
undef $UVM_OBJECT;
undef $CLASS if m/typedef\s+class\s/;
} elsif (m/\`uvm_object_utils/ ||
m/\`uvm_object_param_utils/ ||
m/\`uvm_sequence_utils/) {
$UVM_OBJECT = 1;
} elsif (m/function\s+new\b/) {
$NEW = 1;
} elsif (m/endclass/) {
if ($CLASS && $UVM_OBJECT && !$NEW) {
$TEXT .= "\n function new(string name=\"$CLASS\");\n";
$TEXT .= " super.new(name);\n";
$TEXT .= " endfunction\n\n";
}
undef $CLASS;
undef $NEW;
}
$TEXT .= $_;
}
close(INFILE);
}
return ($TEXT);
}
sub ReadFileAsText {
my($FILENAME)=@_;
my(@FILES)=();
my($FILE,$TEXT);
local(*INFILE);
# DebugMessage("1trying to read text-file [$FILENAME]");
$TEXT="";
foreach $FILE (glob($FILENAME)) {
# DebugMessage("2trying to read text-file [$FILE]");
open(INFILE,$FILE) || WarnMessage("can't open file [$FILE]");
undef $/;
$TEXT .= <INFILE>;
$/ = "\n";
close(INFILE);
}
return ($TEXT);
}
sub WarnMessage{
my($Line)=@_;
Message("warning",$Line);
}
sub ErrorMessage{
my($Line)=@_;
Message("error",$Line);
die "$0 stopped\n";
}
sub NoteMessage{
my($Line)=@_;
Message("note",$Line);
}
sub Message {
my($Level,$Line)=@_;
print STDERR "$Level $Line\n";
}
__DATA__
This scripts walks through all files under the --top_dir hierarchy and makes modifications
so that the OVM code fragments are changed to their UVM counterparts. As it is based on perl/regexps rather
then a full parsing some of the replacements might be inaccurate or it might not find all occurences required
to change. however it is expected that ~90%+ of the changes required in a conversion are completed by the script.
standard usage model sv files only:
1. run the script with the --top_dir option
2. inspect the changes made in the produced *.patch file
3. enable automatic write-back by supplying --write to the command invocation
(under some circumstances filenames get changed (when they contain either *ovm* or *OVM*))
4. inspect the MARKERS
usage: add_uvm_object_new.pl options* args*
example: add_uvm_object_new.pl --top_dir /xyz/abc/src
This diff is collapsed.
#!/bin/sh
##----------------------------------------------------------------------
## Copyright 2010 Cadence, Inc.
## Copyright 2011 Mentor Graphics Corporation
## All Rights Reserved Worldwide
##
## Licensed under the Apache License, Version 2.0 (the
## "License"); you may not use this file except in
## compliance with the License. You may obtain a copy of
## the License at
##
## http://www.apache.org/licenses/LICENSE-2.0
##
## Unless required by applicable law or agreed to in
## writing, software distributed under the License is
## distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
## CONDITIONS OF ANY KIND, either express or implied. See
## the License for the specific language governing
## permissions and limitations under the License.
##----------------------------------------------------------------------
for i in "$@" ; do
case $i in
-tool) OPT_TOOL=1
shift ;;
--) shift ; break ;;
esac
done
function checkPath() {
IFS=':'
for dir in $PATH ; do if [ -x "$dir/$1" ];then return 0; fi ; done
return 1
}
arch=`dirname $0`/uvm_os_name
arch=`$arch`
if [ "x" != "x${MTI_HOME}" ]; then
tool="questa"
elif checkPath ncroot; then
tool="ius"
elif [ "x" != "x${VCS_HOME}" ]; then
tool="vcs"
else
tool="unknown"
fi
if [ $OPT_TOOL ]; then
echo $tool
else
relpath=`dirname $0`/../lib/$arch/libuvm_$tool.so
D=`dirname "$relpath"`
B=`basename "$relpath"`
abspath="`cd \"$D\" 2>/dev/null && pwd || echo \"$D\"`/$B"
echo $abspath
fi
#! /bin/sh
echo `/bin/uname -s`_`/bin/uname -m`
Accellera UVM 1.1d Release Notes
================================
January 25, 2013
General Overview
----------------
This is release 1.1d of the Universal Verification Methodology (UVM) reference implementation from Accellera.  This distribution includes a SystemVerilog based class library, examples, User's Guide, and an updated Reference in HTML form. The UVM Standard Reference PDF is not included in this release. It will not be updated until the next major release, i.e. UVM 1.2.
The class library is a reference implementation of the standard. It, the examples, and User Guide provide guidance to users of the standard. For additional information on the Accellera standard, see
http://www.accellera.org/activities/vip
A good source for information, answers, and resources is http://www.uvmworld.org.  It contains forums on methodology, tool specific issues, and commercial announcements.  It also has links to additional resources, Accellera sponsored events, and other UVM events.
What's Changed
--------------
Release 1.1d contains fixes to errata. Some errata involve changes to the UVM reference documentation in cases where the stated behavior was unclear or did not comply with intended behavior. Such changes will only be reflected in the HTML documentation included with the distribution. Changes to the actual standard PDF document will not occur until the next numbered release, i.e. UVM 1.2.
UVM 1.1d fixes the following issues reported under the Mantis bug-tracking system. Issues affecting the reference documentation (API changes or semantic changes) are preceded with an asterisk (*).
For detailed information on a specific issue, refer to the Mantis database at http://www.eda.org/svdb/view.php?id=<id>, where <id> is the Mantis id.
Mantis 3477, fixed issue where a uvm_heartbeat object being started twice, where first start was provided an event and second start was not provided an event, caused simulation to crash.
Mantis 3568, fixed issue with `uvm_do_obj_callbacks_exit_on macro having a System Verilog function “return” statement where the macro does not need to be called from a function. The fixed macro now just exits the loop without calling “return”.
Mantis 3786, fixed potential race issue between two static initializations and usage. The issue is with the uvm_callbacks#(uvm_report_object,uvm_callback)::m_t_inst.m_tw_cb_q variable that is static initialized in the library and could be used by a user statically initialized object.
Mantis 3967, provided better UVM_FATAL message when multiple threads invoke get_next_item() simultaneously.
Mantis 4073, fixed issue where uvm_report_catcher deadlocks when callback_mode is 0.
Mantis 4161, fixed issue where uvm_re_match function used a string index outside the string index range.
Mantis 4165, changed documentation for uvm_report_server constructor. Documentation stated incorrectly that uvm_report_server was a singleton. This statement was removed.
Mantis 4168, fixed issue where bit bash ignores access rights (i.e. uvm_reg_map::add_reg(.rights())) when there is only one register map. It was ignored due to an incorrect optimization.
Mantis 4190, fixed issue where simple sequence example was not really using a simple sequence approach. The example distrib/examples/simple/sequence/basic_read_write_sequence/top.sv was fixed.
Mantis 4214, fixed issue with usage of generic name "max" as a globally scoped variable. Variable was placed within the uvm_spell_chkr class scope.
Mantis 4235 fixed issue with vendor dependent code for uvm_record_attribute macro, which would not get defined for a simulator that is not from Mentor, Synopsys or Cadence.
Mantis 4251, fixed issue with specifying length of burst reads.
Mantis 4256, fixed issue with macro UVM_SEQ_ITEM_PULL_IMP being defined twice. One of the definitions was removed.
Mantis 4268, fixed issue where registers that have the attribute WSRC and WCRS are not properly being predicted for read operations. Write operations were fine.
Mantis 4297, fixed issue, with use of set_auto_predict(1) where the return status from accesses on the BFM will get overwritten and replaced by UVM_IS_OK. Errors on the bus which is in the uvm_reg_adapter::bus2reg() are set to rw.status = UVM_NOT_OK or UVM_HAS_X and will never be seen by callers or the reporting system.
Mantis 4299, fixed documentation for uvm_sequence_base::kill. There was an incomplete sentence.
Mantis 4301, fixed documentation for uvm_config_db::set. The documentation was unclear on how the search scope is created from the instance name and context.
Mantis 4313, fixed issue where the uvm_component::apply_config_settings method silently failed when the type of the configuration object is not supported. The issue happens when $cast call fails within the method.
Mantis 4315, fixed issue where config_db setting precedence was not working according to specification when called in a descendent object.
Mantis 4316, fixed documentation, clarified the differences between UVM_ALL_ON and UVM_DEFAULT used in the uvm_object_util macros.
Mantis 4322, fixed issue where the "uvm_rand_send*" group of macros did not work when the sequence_item executes on another type of sequencer. The code failed when doing a $cast to the inappropriate type.
Mantis 4323, did a general cleanup. Thoroughly went through the UVM code removing old workarounds due to tool limitations.
Mantis 4324, fixed issue where extra long data in columns of a table printer destroys the formatting of the rest of the table.
Mantis 4327, added instructions on how to run the examples in the released tar ball.
Mantis 4329, fixed issue where large timeout values were not honored correctly. The issue was with numbers that required more than 32 bits to represent.
Mantis 4331, fixed documentation, added a description for the UVM_CB_TRACE_ON flag used in the callback functions.
Mantis 4333, fixed issue with register library where, set, followed by mirror with CHECK caused false errors.
Mantis 4341, fixed issue where uvm_printer_knobs::separator variable was not used. The variable was removed.
Mantis 4342, fixed issue where dpi compile on AIX resulted in warning messages.
Mantis 4344, fixed documentation, showed how to use “uvm_sequence_base::wait_for_sequence_state()“ for waiting on a sequence state, previously an incorrect/bad way was used.
(*) Mantis 4345, fixed issue where uvm_sequence_base::wait_for_sequence_state() did not support waiting for more than one state.
Mantis 4347, fixed issue where register map warning for, different bus sizes between parent and child maps, was incorrect.
Mantis 4351, added documentation to use uvm_root::get() instead of uvm_top when accessing top level in the logical hierarchy. This is a safer way to access a static variable and not to be dependent on the initialization order.
Mantis 4380, fixed issue with incorrect formatting sizes in uvm_table_printer. The table sizes where not cleared between two calculations.
(*) Mantis 4383, added a generic report method in the uvm_report_object class. This simplifies writing user code that overrides the behavior of the different report methods.
Mantis 4388, fixed issue where the objection mechanism was not robust against in-determinant process order.
Mantis 4423, fixed issue with broken HTML source links.
Mantis 4465, added support to disable resource converter and use VCS native conversion
//
//------------------------------------------------------------------------------
// Copyright 2007-2010 Mentor Graphics Corporation
// Copyright 2007-2010 Cadence Design Systems, Inc.
// Copyright 2010 Synopsys, Inc.
// All Rights Reserved Worldwide
//
// Licensed under the Apache License, Version 2.0 (the
// "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of
// the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in
// writing, software distributed under the License is
// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See
// the License for the specific language governing
// permissions and limitations under the License.
//------------------------------------------------------------------------------
//-----------------------------------------------------------------------------
//
// CLASS: uvm_barrier
//
// The uvm_barrier class provides a multiprocess synchronization mechanism.
// It enables a set of processes to block until the desired number of processes
// get to the synchronization point, at which time all of the processes are
// released.
//-----------------------------------------------------------------------------
class uvm_barrier extends uvm_object;
local int threshold;
local int num_waiters;
local bit at_threshold;
local bit auto_reset;
local uvm_event m_event;
// Function: new
//
// Creates a new barrier object.
function new (string name="", int threshold=0);
uvm_event e;
super.new(name);
e = new({"barrier_",name});
this.threshold = threshold;
m_event = e;
num_waiters = 0;
auto_reset = 1;
at_threshold = 0;
endfunction
// Task: wait_for
//
// Waits for enough processes to reach the barrier before continuing.
//
// The number of processes to wait for is set by the <set_threshold> method.
virtual task wait_for();
if (at_threshold)
return;
num_waiters++;
if (num_waiters >= threshold) begin
if (!auto_reset)
at_threshold=1;
m_trigger();
return;
end
m_event.wait_trigger();
endtask
// Function: reset
//
// Resets the barrier. This sets the waiter count back to zero.
//
// The threshold is unchanged. After reset, the barrier will force processes
// to wait for the threshold again.
//
// If the ~wakeup~ bit is set, any currently waiting processes will
// be activated.
virtual function void reset (bit wakeup=1);
at_threshold = 0;
if (num_waiters) begin
if (wakeup)
m_event.trigger();
else
m_event.reset();
end
num_waiters = 0;
endfunction
// Function: set_auto_reset
//
// Determines if the barrier should reset itself after the threshold is
// reached.
//
// The default is on, so when a barrier hits its threshold it will reset, and
// new processes will block until the threshold is reached again.
//
// If auto reset is off, then once the threshold is achieved, new processes
// pass through without being blocked until the barrier is reset.
virtual function void set_auto_reset (bit value=1);
at_threshold = 0;
auto_reset = value;
endfunction
// Function: set_threshold
//
// Sets the process threshold.
//
// This determines how many processes must be waiting on the barrier before
// the processes may proceed.
//
// Once the ~threshold~ is reached, all waiting processes are activated.
//
// If ~threshold~ is set to a value less than the number of currently
// waiting processes, then the barrier is reset and waiting processes are
// activated.
virtual function void set_threshold (int threshold);
this.threshold = threshold;
if (threshold <= num_waiters)
reset(1);
endfunction
// Function: get_threshold
//
// Gets the current threshold setting for the barrier.
virtual function int get_threshold ();
return threshold;
endfunction
// Function: get_num_waiters
//
// Returns the number of processes currently waiting at the barrier.
virtual function int get_num_waiters ();
return num_waiters;
endfunction
// Function: cancel
//
// Decrements the waiter count by one. This is used when a process that is
// waiting on the barrier is killed or activated by some other means.
virtual function void cancel ();
m_event.cancel();
num_waiters = m_event.get_num_waiters();
endfunction
const static string type_name = "uvm_barrier";
virtual function uvm_object create(string name="");
uvm_barrier v;
v=new(name);
return v;
endfunction
virtual function string get_type_name();
return type_name;
endfunction
local task m_trigger();
m_event.trigger();
num_waiters=0;
#0; //this process was last to wait; allow other procs to resume first
endtask
virtual function void do_print (uvm_printer printer);
printer.print_int("threshold", threshold, $bits(threshold), UVM_DEC, ".", "int");
printer.print_int("num_waiters", num_waiters, $bits(num_waiters), UVM_DEC, ".", "int");
printer.print_int("at_threshold", at_threshold, $bits(at_threshold), UVM_BIN, ".", "bit");
printer.print_int("auto_reset", auto_reset, $bits(auto_reset), UVM_BIN, ".", "bit");
endfunction
virtual function void do_copy (uvm_object rhs);
uvm_barrier b;
super.do_copy(rhs);
if(!$cast(b, rhs) || (b==null)) return;
threshold = b.threshold;
num_waiters = b.num_waiters;
at_threshold = b.at_threshold;
auto_reset = b.auto_reset;
m_event = b.m_event;
endfunction
endclass
//
//----------------------------------------------------------------------
// Copyright 2007-2011 Mentor Graphics Corporation
// Copyright 2007-2010 Cadence Design Systems, Inc.
// Copyright 2010 Synopsys, Inc.
// All Rights Reserved Worldwide
//
// Licensed under the Apache License, Version 2.0 (the
// "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of
// the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in
// writing, software distributed under the License is
// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See
// the License for the specific language governing
// permissions and limitations under the License.
//----------------------------------------------------------------------
`ifndef UVM_BASE_SVH
`define UVM_BASE_SVH
typedef class uvm_cmdline_processor;
// Miscellaneous classes and functions. uvm_void is defined in uvm_misc,
// along with some auxillary functions that UVM needs but are not really
// part of UVM.
`include "base/uvm_version.svh"
`include "base/uvm_object_globals.svh"
`include "base/uvm_misc.svh"
// The base object element. Contains data methods (copy/compare etc) and
// factory creation methods (create). Also includes control classes.
`include "base/uvm_object.svh"
`include "base/uvm_pool.svh"
`include "base/uvm_queue.svh"
`include "base/uvm_factory.svh"
`include "base/uvm_registry.svh"
// Resources/configuration facility
`include "base/uvm_spell_chkr.svh"
`include "base/uvm_resource.svh"
`ifdef UVM_USE_RESOURCE_CONVERTER
`include "deprecated/uvm_resource_converter.svh"
`endif
`include "base/uvm_resource_specializations.svh"
`include "base/uvm_resource_db.svh"
`include "base/uvm_config_db.svh"
// Policies
`include "base/uvm_printer.svh"
`include "base/uvm_comparer.svh"
`include "base/uvm_packer.svh"
`include "base/uvm_recorder.svh"
// Event interface
`include "base/uvm_event_callback.svh"
`include "base/uvm_event.svh"
`include "base/uvm_barrier.svh"
// Callback interface
`include "base/uvm_callback.svh"
// Reporting interface
`include "base/uvm_report_catcher.svh"
`include "base/uvm_report_server.svh"
`include "base/uvm_report_handler.svh"
`include "base/uvm_report_object.svh"
// Base transaction object
`include "base/uvm_transaction.svh"
// The phase declarations
`include "base/uvm_phase.svh"
`include "base/uvm_domain.svh"
`include "base/uvm_bottomup_phase.svh"
`include "base/uvm_topdown_phase.svh"
`include "base/uvm_task_phase.svh"
`include "base/uvm_common_phases.svh"
`include "base/uvm_runtime_phases.svh"
`include "base/uvm_component.svh"
// Objection interface
`include "base/uvm_objection.svh"
`include "base/uvm_heartbeat.svh"
`include "base/uvm_globals.svh"
// Command Line Processor
`include "base/uvm_cmdline_processor.svh"
`endif // UVM_BASE_SVH
//
//----------------------------------------------------------------------
// Copyright 2007-2011 Mentor Graphics Corporation
// Copyright 2007-2010 Cadence Design Systems, Inc.
// Copyright 2010 Synopsys, Inc.
// All Rights Reserved Worldwide
//
// Licensed under the Apache License, Version 2.0 (the
// "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of
// the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in
// writing, software distributed under the License is
// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See
// the License for the specific language governing
// permissions and limitations under the License.
//----------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// Class: uvm_bottomup_phase
//
//------------------------------------------------------------------------------
// Virtual base class for function phases that operate bottom-up.
// The pure virtual function execute() is called for each component.
// This is the default traversal so is included only for naming.
//
// A bottom-up function phase completes when the <execute()> method
// has been called and returned on all applicable components
// in the hierarchy.
virtual class uvm_bottomup_phase extends uvm_phase;
// Function: new
//
// Create a new instance of a bottom-up phase.
//
function new(string name);
super.new(name,UVM_PHASE_IMP);
endfunction
// Function: traverse
//
// Traverses the component tree in bottom-up order, calling <execute> for
// each component.
//
virtual function void traverse(uvm_component comp,
uvm_phase phase,
uvm_phase_state state);
string name;
uvm_domain phase_domain =phase.get_domain();
uvm_domain comp_domain = comp.get_domain();
if (comp.get_first_child(name))
do
traverse(comp.get_child(name), phase, state);
while(comp.get_next_child(name));
if (m_phase_trace)
`uvm_info("PH_TRACE",$sformatf("bottomup-phase phase=%s state=%s comp=%s comp.domain=%s phase.domain=%s",
phase.get_name(), state.name(), comp.get_full_name(),comp_domain.get_name(),phase_domain.get_name()),
UVM_DEBUG)
if (phase_domain == uvm_domain::get_common_domain() ||
phase_domain == comp_domain) begin
case (state)
UVM_PHASE_STARTED: begin
comp.m_current_phase = phase;
comp.m_apply_verbosity_settings(phase);
comp.phase_started(phase);
end
UVM_PHASE_EXECUTING: begin
uvm_phase ph = this;
if (comp.m_phase_imps.exists(this))
ph = comp.m_phase_imps[this];
ph.execute(comp, phase);
end
UVM_PHASE_READY_TO_END: begin
comp.phase_ready_to_end(phase);
end
UVM_PHASE_ENDED: begin
comp.phase_ended(phase);
comp.m_current_phase = null;
end
default:
`uvm_fatal("PH_BADEXEC","bottomup phase traverse internal error")
endcase
end
endfunction
// Function: execute
//
// Executes the bottom-up phase ~phase~ for the component ~comp~.
//
virtual function void execute(uvm_component comp,
uvm_phase phase);
// reseed this process for random stability
process proc = process::self();
proc.srandom(uvm_create_random_seed(phase.get_type_name(), comp.get_full_name()));
comp.m_current_phase = phase;
exec_func(comp,phase);
endfunction
endclass
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//
//----------------------------------------------------------------------
// Copyright 2007-2011 Mentor Graphics Corporation
// Copyright 2007-2010 Cadence Design Systems, Inc.
// Copyright 2010 Synopsys, Inc.
// All Rights Reserved Worldwide
//
// Licensed under the Apache License, Version 2.0 (the
// "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of
// the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in
// writing, software distributed under the License is
// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See
// the License for the specific language governing
// permissions and limitations under the License.
//----------------------------------------------------------------------
typedef class uvm_build_phase;
typedef class uvm_connect_phase;
typedef class uvm_end_of_elaboration_phase;
typedef class uvm_start_of_simulation_phase;
typedef class uvm_run_phase;
typedef class uvm_extract_phase;
typedef class uvm_check_phase;
typedef class uvm_report_phase;
typedef class uvm_final_phase;
typedef class uvm_pre_reset_phase;
typedef class uvm_reset_phase;
typedef class uvm_post_reset_phase;
typedef class uvm_pre_configure_phase;
typedef class uvm_configure_phase;
typedef class uvm_post_configure_phase;
typedef class uvm_pre_main_phase;
typedef class uvm_main_phase;
typedef class uvm_post_main_phase;
typedef class uvm_pre_shutdown_phase;
typedef class uvm_shutdown_phase;
typedef class uvm_post_shutdown_phase;
uvm_phase build_ph;
uvm_phase connect_ph;
uvm_phase end_of_elaboration_ph;
uvm_phase start_of_simulation_ph;
uvm_phase run_ph;
uvm_phase extract_ph;
uvm_phase check_ph;
uvm_phase report_ph;
//------------------------------------------------------------------------------
//
// Class: uvm_domain
//
//------------------------------------------------------------------------------
//
// Phasing schedule node representing an independent branch of the schedule.
// Handle used to assign domains to components or hierarchies in the testbench
//
class uvm_domain extends uvm_phase;
static local uvm_domain m_common_domain;
static local uvm_domain m_uvm_domain; // run-time phases
static local uvm_domain m_domains[string];
static local uvm_phase m_uvm_schedule;
// Function: get_domains
//
// Provides a list of all domains in the provided ~domains~ argument.
//
static function void get_domains(output uvm_domain domains[string]);
domains = m_domains;
endfunction
// Function: get_uvm_schedule
//
// Get the "UVM" schedule, which consists of the run-time phases that
// all components execute when participating in the "UVM" domain.
//
static function uvm_phase get_uvm_schedule();
void'(get_uvm_domain());
return m_uvm_schedule;
endfunction
// Function: get_common_domain
//
// Get the "common" domain, which consists of the common phases that
// all components execute in sync with each other. Phases in the "common"
// domain are build, connect, end_of_elaboration, start_of_simulation, run,
// extract, check, report, and final.
//
static function uvm_domain get_common_domain();
uvm_domain domain;
uvm_phase schedule;
if (m_common_domain != null)
return m_common_domain;
domain = new("common");
domain.add(uvm_build_phase::get());
domain.add(uvm_connect_phase::get());
domain.add(uvm_end_of_elaboration_phase::get());
domain.add(uvm_start_of_simulation_phase::get());
domain.add(uvm_run_phase::get());
domain.add(uvm_extract_phase::get());
domain.add(uvm_check_phase::get());
domain.add(uvm_report_phase::get());
domain.add(uvm_final_phase::get());
m_domains["common"] = domain;
// for backward compatibility, make common phases visible;
// same as uvm_<name>_phase::get().
build_ph = domain.find(uvm_build_phase::get());
connect_ph = domain.find(uvm_connect_phase::get());
end_of_elaboration_ph = domain.find(uvm_end_of_elaboration_phase::get());
start_of_simulation_ph = domain.find(uvm_start_of_simulation_phase::get());
run_ph = domain.find(uvm_run_phase::get());
extract_ph = domain.find(uvm_extract_phase::get());
check_ph = domain.find(uvm_check_phase::get());
report_ph = domain.find(uvm_report_phase::get());
m_common_domain = domain;
domain = get_uvm_domain();
m_common_domain.add(domain,
.with_phase(m_common_domain.find(uvm_run_phase::get())));
return m_common_domain;
endfunction
// Function: add_uvm_phases
//
// Appends to the given ~schedule~ the built-in UVM phases.
//
static function void add_uvm_phases(uvm_phase schedule);
schedule.add(uvm_pre_reset_phase::get());
schedule.add(uvm_reset_phase::get());
schedule.add(uvm_post_reset_phase::get());
schedule.add(uvm_pre_configure_phase::get());
schedule.add(uvm_configure_phase::get());
schedule.add(uvm_post_configure_phase::get());
schedule.add(uvm_pre_main_phase::get());
schedule.add(uvm_main_phase::get());
schedule.add(uvm_post_main_phase::get());
schedule.add(uvm_pre_shutdown_phase::get());
schedule.add(uvm_shutdown_phase::get());
schedule.add(uvm_post_shutdown_phase::get());
endfunction
// Function: get_uvm_domain
//
// Get a handle to the singleton ~uvm~ domain
//
static function uvm_domain get_uvm_domain();
if (m_uvm_domain == null) begin
m_uvm_domain = new("uvm");
m_uvm_schedule = new("uvm_sched", UVM_PHASE_SCHEDULE);
add_uvm_phases(m_uvm_schedule);
m_uvm_domain.add(m_uvm_schedule);
end
return m_uvm_domain;
endfunction
// Function: new
//
// Create a new instance of a phase domain.
function new(string name);
super.new(name,UVM_PHASE_DOMAIN);
if (m_domains.exists(name))
`uvm_error("UNIQDOMNAM", $sformatf("Domain created with non-unique name '%s'", name))
m_domains[name] = this;
endfunction
// Function: jump
//
// jumps all active phases of this domain to to-phase if
// there is a path between active-phase and to-phase
function void jump(uvm_phase phase);
uvm_phase phases[$];
m_get_transitive_children(phases);
phases = phases.find(item) with (item.get_state() inside {[UVM_PHASE_STARTED:UVM_PHASE_CLEANUP]});
foreach(phases[idx])
if(phases[idx].is_before(phase) || phases[idx].is_after(phase))
phases[idx].jump(phase);
endfunction
// jump_all
// --------
static function void jump_all(uvm_phase phase);
uvm_domain domains[string];
uvm_domain::get_domains(domains);
foreach(domains[idx])
domains[idx].jump(phase);
endfunction
endclass
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//
//------------------------------------------------------------------------------
// Copyright 2007-2010 Mentor Graphics Corporation
// Copyright 2007-2010 Cadence Design Systems, Inc.
// Copyright 2010 Synopsys, Inc.
// All Rights Reserved Worldwide
//
// Licensed under the Apache License, Version 2.0 (the
// "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of
// the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in
// writing, software distributed under the License is
// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See
// the License for the specific language governing
// permissions and limitations under the License.
//------------------------------------------------------------------------------
typedef class uvm_object;
typedef class uvm_event;
//------------------------------------------------------------------------------
//
// CLASS: uvm_event_callback
//
// The uvm_event_callback class is an abstract class that is used to create
// callback objects which may be attached to <uvm_events>. To use, you
// derive a new class and override any or both <pre_trigger> and <post_trigger>.
//
// Callbacks are an alternative to using processes that wait on events. When a
// callback is attached to an event, that callback object's callback function
// is called each time the event is triggered.
//
//------------------------------------------------------------------------------
virtual class uvm_event_callback extends uvm_object;
// Function: new
//
// Creates a new callback object.
function new (string name="");
super.new(name);
endfunction
// Function: pre_trigger
//
// This callback is called just before triggering the associated event.
// In a derived class, override this method to implement any pre-trigger
// functionality.
//
// If your callback returns 1, then the event will not trigger and the
// post-trigger callback is not called. This provides a way for a callback
// to prevent the event from triggering.
//
// In the function, ~e~ is the <uvm_event> that is being triggered, and ~data~
// is the optional data associated with the event trigger.
virtual function bit pre_trigger (uvm_event e, uvm_object data=null);
return 0;
endfunction
// Function: post_trigger
//
// This callback is called after triggering the associated event.
// In a derived class, override this method to implement any post-trigger
// functionality.
//
//
// In the function, ~e~ is the <uvm_event> that is being triggered, and ~data~
// is the optional data associated with the event trigger.
virtual function void post_trigger (uvm_event e, uvm_object data=null);
return;
endfunction
virtual function uvm_object create (string name="");
return null;
endfunction
endclass
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