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Commit 573ef26e authored by Tristan Gingold's avatar Tristan Gingold
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Improve coverage of libero.

parent 4ebfaf4f
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Showing with 8 additions and 7 deletions
hdlmake/sourcefiles/sourcefileset.py
View file @ 573ef26e
......@@ -59,5 +59,5 @@ class SourceFileSet(set):
def sort(self):
"""Return a sorted list of the fileset. This is useful to have always
the same output"""
return sorted(self, key=(lambda x: x.file_path))
return sorted(self, key=(lambda x: x.path))
hdlmake/tools/libero.py
View file @ 573ef26e
......@@ -94,7 +94,7 @@ class ToolLibero(MakefileSyn):
compilation_constraints = []
ret = []
# First stage: linking files
for file_aux in self.fileset:
for file_aux in self.fileset.sort():
if isinstance(file_aux, SDCFile):
synthesis_constraints.append(file_aux)
compilation_constraints.append(file_aux)
......
testsuite/013libero/Makefile.ref
View file @ 573ef26e
......@@ -34,9 +34,13 @@ SOURCES_VHDLFile := \
SOURCES_SDCFile := \
syn.sdc
SOURCES_PDCFile := \
comp.pdc
files.tcl:
@$(foreach sourcefile, $(SOURCES_VHDLFile), echo "create_links -hdl_source $(sourcefile)" >> $@ &)
@$(foreach sourcefile, $(SOURCES_SDCFile), echo "create_links -sdc $(sourcefile)" >> $@ &)
@$(foreach sourcefile, $(SOURCES_PDCFile), echo "create_links -pdc $(sourcefile)" >> $@ &)
SYN_PRE_PROJECT_CMD :=
SYN_POST_PROJECT_CMD :=
......@@ -48,7 +52,7 @@ project.tcl:
echo $(TCL_CREATE) >> $@
echo source files.tcl >> $@
echo organize_tool_files -tool {SYNTHESIZE} -file {syn.sdc} -module {$(TOP_MODULE)::work} -input_type {constraint} >> $@
echo organize_tool_files -tool {COMPILE} -file {syn.sdc} -module {$(TOP_MODULE)::work} -input_type {constraint} >> $@
echo organize_tool_files -tool {COMPILE} -file {comp.pdc} -file {syn.sdc} -module {$(TOP_MODULE)::work} -input_type {constraint} >> $@
echo set_root -module {$(TOP_MODULE)::work} >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
......
testsuite/013libero/Manifest.py
View file @ 573ef26e
......@@ -8,7 +8,4 @@ syn_project="gate"
top_module = "gate"
# Not reliable.
#files = [ "../files/gate.vhdl", "syn.sdc", "comp.pdc" ]
files = [ "../files/gate.vhdl", "syn.sdc" ]
files = [ "../files/gate.vhdl", "syn.sdc", "comp.pdc" ]
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