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Hdlmake
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4b2b141b
Commit
4b2b141b
authored
May 31, 2019
by
Tristan Gingold
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testsuite: improve testing of quartus module.
parent
6012a665
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12 changed files
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385 additions
and
0 deletions
+385
-0
Makefile.ref
testsuite/033quartus/Makefile.ref
+81
-0
Manifest.py
testsuite/033quartus/Manifest.py
+17
-0
none.tcl
testsuite/033quartus/none.tcl
+1
-0
Makefile
testsuite/034quartus_prop/Makefile
+81
-0
Makefile.ref
testsuite/034quartus_prop/Makefile.ref
+81
-0
Manifest.py
testsuite/034quartus_prop/Manifest.py
+19
-0
Manifest.py
testsuite/035quartus_err/Manifest.py
+15
-0
Manifest.py
testsuite/036quartus_err/Manifest.py
+15
-0
Manifest.py
testsuite/037quartus_err/Manifest.py
+15
-0
Manifest.py
testsuite/038quartus_err/Manifest.py
+15
-0
Manifest.py
testsuite/039quartus_err/Manifest.py
+13
-0
test_all.py
testsuite/test_all.py
+32
-0
No files found.
testsuite/033quartus/Makefile.ref
0 → 100644
View file @
4b2b141b
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE
:=
gate
PWD
:=
$(
shell
pwd
)
PROJECT
:=
gate_prj
PROJECT_FILE
:=
$(PROJECT)
.qpf
TOOL_PATH
:=
TCL_INTERPRETER
:=
quartus_sh
-t
ifneq
($(strip
$(TOOL_PATH)),)
TCL_INTERPRETER
:=
$(TOOL_PATH)
/
$(TCL_INTERPRETER)
endif
SYN_FAMILY
:=
Arria V
SYN_DEVICE
:=
5agxmb1g4f40c4
SYN_PACKAGE
:=
40
SYN_GRADE
:=
c4
TCL_CREATE
:=
project_new
$(PROJECT)
TCL_OPEN
:=
project_open
$(PROJECT)
ifneq
($(wildcard
$(PROJECT_FILE)),)
TCL_CREATE
:=
$(TCL_OPEN)
endif
#target for performing local synthesis
all
:
bitstream
SOURCES_VHDLFile
:=
\
../files/gate.vhdl
files.tcl
:
@
echo
set_global_assignment
-name
PRE_FLOW_SCRIPT_FILE
\"
"quartus_sh:none.tcl"
\"
>>
$@
@
echo
set_global_assignment
-name
POST_MODULE_SCRIPT_FILE
\"
"quartus_sh:none.tcl"
\"
>>
$@
@
echo
set_global_assignment
-name
POST_FLOW_SCRIPT_FILE
\"
"quartus_sh:none.tcl"
\"
>>
$@
@
$
(
foreach sourcefile,
$(SOURCES_VHDLFile)
,
echo
"set_global_assignment -name VHDL_FILE
$(sourcefile)
-library work"
>>
$@
&
)
SYN_PRE_PROJECT_CMD
:=
SYN_POST_PROJECT_CMD
:=
SYN_PRE_BITSTREAM_CMD
:=
SYN_POST_BITSTREAM_CMD
:=
project.tcl
:
echo
load_package flow
>>
$@
echo
$(TCL_CREATE)
>>
$@
echo
remove_all_global_assignments
-name
*
_FILE
>>
$@
echo source
files.tcl
>>
$@
echo
set_global_assignment
-name
FAMILY
\"
$(SYN_FAMILY)
\"
>>
$@
echo
set_global_assignment
-name
DEVICE
\"
$(SYN_DEVICE)
\"
>>
$@
echo
set_global_assignment
-name
TOP_LEVEL_ENTITY
\"
$(TOP_MODULE)
\"
>>
$@
project
:
files.tcl project.tcl
$(SYN_PRE_PROJECT_CMD)
$(TCL_INTERPRETER)
$@
.tcl
$(SYN_POST_PROJECT_CMD)
touch
$@
bitstream.tcl
:
echo
load_package flow
>>
$@
echo
$(TCL_OPEN)
>>
$@
echo
execute_flow
-compile
>>
$@
bitstream
:
project bitstream.tcl
$(SYN_PRE_BITSTREAM_CMD)
$(TCL_INTERPRETER)
$@
.tcl
$(SYN_POST_BITSTREAM_CMD)
touch
$@
CLEAN_TARGETS
:=
$(LIBS)
*
.rpt
*
.smsg
*
.summary
*
.done
*
.jdi
*
.pin
*
.qws db incremental_db
$(PROJECT)
.qsf
*
.qpf
clean
:
rm
-rf
$(CLEAN_TARGETS)
rm
-rf
project synthesize translate map par bitstream
rm
-rf
project.tcl synthesize.tcl translate.tcl map.tcl par.tcl bitstream.tcl files.tcl
mrproper
:
clean
rm
-rf
*
.sof
*
.pof
*
.jam
*
.jbc
*
.ekp
*
.jic
.PHONY
:
mrproper clean all
testsuite/033quartus/Manifest.py
0 → 100644
View file @
4b2b141b
action
=
"synthesis"
language
=
"vhdl"
syn_family
=
"Arria V"
syn_device
=
"5agxmb1g4f"
syn_grade
=
"c4"
syn_package
=
"40"
syn_top
=
"gate"
syn_project
=
"gate_prj"
syn_tool
=
"quartus"
quartus_preflow
=
'none.tcl'
quartus_postmodule
=
'none.tcl'
quartus_postflow
=
'none.tcl'
files
=
[
"../files/gate.vhdl"
]
testsuite/033quartus/none.tcl
0 → 100644
View file @
4b2b141b
testsuite/034quartus_prop/Makefile
0 → 100644
View file @
4b2b141b
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE
:=
gate
PWD
:=
$(
shell
pwd
)
PROJECT
:=
gate_prj
PROJECT_FILE
:=
$(PROJECT)
.qpf
TOOL_PATH
:=
TCL_INTERPRETER
:=
quartus_sh
-t
ifneq
($(strip
$(TOOL_PATH)),)
TCL_INTERPRETER
:=
$(TOOL_PATH)
/
$(TCL_INTERPRETER)
endif
SYN_FAMILY
:=
Arria V
SYN_DEVICE
:=
5agxmb1g4f40c4
SYN_PACKAGE
:=
40
SYN_GRADE
:=
c4
TCL_CREATE
:=
project_new
$(PROJECT)
TCL_OPEN
:=
project_open
$(PROJECT)
ifneq
($(wildcard
$(PROJECT_FILE)),)
TCL_CREATE
:=
$(TCL_OPEN)
endif
#target for performing local synthesis
all
:
bitstream
SOURCES_VHDLFile
:=
\
../files/gate.vhdl
files.tcl
:
@
echo
>>
$@
@
$
(
foreach sourcefile,
$(SOURCES_VHDLFile)
,
echo
"set_global_assignment -name VHDL_FILE
$(sourcefile)
-library work"
>>
$@
&
)
SYN_PRE_PROJECT_CMD
:=
SYN_POST_PROJECT_CMD
:=
SYN_PRE_BITSTREAM_CMD
:=
SYN_POST_BITSTREAM_CMD
:=
project.tcl
:
echo
load_package flow
>>
$@
echo
$(TCL_CREATE)
>>
$@
echo
remove_all_global_assignments
-name
*
_FILE
>>
$@
echo source
files.tcl
>>
$@
echo
set_global_assignment
-name
FAMILY
\"
$(SYN_FAMILY)
\"
>>
$@
echo
set_global_assignment
-name
DEVICE
\"
$(SYN_DEVICE)
\"
>>
$@
echo
set_global_assignment
-name
TOP_LEVEL_ENTITY
\"
$(TOP_MODULE)
\"
>>
$@
echo
set_global_assignment vwaht
-name
vname
\"
vval
\"
-from
vfrom
-tag
vtag
-to
vto
-section_id
vsid
>>
$@
echo
set_global_assignment
-name
SEARCH_PATH
\"
.
\"
>>
$@
project
:
files.tcl project.tcl
$(SYN_PRE_PROJECT_CMD)
$(TCL_INTERPRETER)
$@
.tcl
$(SYN_POST_PROJECT_CMD)
touch
$@
bitstream.tcl
:
echo
load_package flow
>>
$@
echo
$(TCL_OPEN)
>>
$@
echo
execute_flow
-compile
>>
$@
bitstream
:
project bitstream.tcl
$(SYN_PRE_BITSTREAM_CMD)
$(TCL_INTERPRETER)
$@
.tcl
$(SYN_POST_BITSTREAM_CMD)
touch
$@
CLEAN_TARGETS
:=
$(LIBS)
*
.rpt
*
.smsg
*
.summary
*
.done
*
.jdi
*
.pin
*
.qws db incremental_db
$(PROJECT)
.qsf
*
.qpf
clean
:
rm
-rf
$(CLEAN_TARGETS)
rm
-rf
project synthesize translate map par bitstream
rm
-rf
project.tcl synthesize.tcl translate.tcl map.tcl par.tcl bitstream.tcl files.tcl
mrproper
:
clean
rm
-rf
*
.sof
*
.pof
*
.jam
*
.jbc
*
.ekp
*
.jic
.PHONY
:
mrproper clean all
testsuite/034quartus_prop/Makefile.ref
0 → 100644
View file @
4b2b141b
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE
:=
gate
PWD
:=
$(
shell
pwd
)
PROJECT
:=
gate_prj
PROJECT_FILE
:=
$(PROJECT)
.qpf
TOOL_PATH
:=
TCL_INTERPRETER
:=
quartus_sh
-t
ifneq
($(strip
$(TOOL_PATH)),)
TCL_INTERPRETER
:=
$(TOOL_PATH)
/
$(TCL_INTERPRETER)
endif
SYN_FAMILY
:=
Arria V
SYN_DEVICE
:=
5agxmb1g4f40c4
SYN_PACKAGE
:=
40
SYN_GRADE
:=
c4
TCL_CREATE
:=
project_new
$(PROJECT)
TCL_OPEN
:=
project_open
$(PROJECT)
ifneq
($(wildcard
$(PROJECT_FILE)),)
TCL_CREATE
:=
$(TCL_OPEN)
endif
#target for performing local synthesis
all
:
bitstream
SOURCES_VHDLFile
:=
\
../files/gate.vhdl
files.tcl
:
@
echo
>>
$@
@
$
(
foreach sourcefile,
$(SOURCES_VHDLFile)
,
echo
"set_global_assignment -name VHDL_FILE
$(sourcefile)
-library work"
>>
$@
&
)
SYN_PRE_PROJECT_CMD
:=
SYN_POST_PROJECT_CMD
:=
SYN_PRE_BITSTREAM_CMD
:=
SYN_POST_BITSTREAM_CMD
:=
project.tcl
:
echo
load_package flow
>>
$@
echo
$(TCL_CREATE)
>>
$@
echo
remove_all_global_assignments
-name
*
_FILE
>>
$@
echo source
files.tcl
>>
$@
echo
set_global_assignment
-name
FAMILY
\"
$(SYN_FAMILY)
\"
>>
$@
echo
set_global_assignment
-name
DEVICE
\"
$(SYN_DEVICE)
\"
>>
$@
echo
set_global_assignment
-name
TOP_LEVEL_ENTITY
\"
$(TOP_MODULE)
\"
>>
$@
echo
set_global_assignment
-name
vname
\"
vval
\"
-from
vfrom
-tag
vtag
-to
vto
-section_id
vsid
>>
$@
echo
set_global_assignment
-name
SEARCH_PATH
\"
.
\"
>>
$@
project
:
files.tcl project.tcl
$(SYN_PRE_PROJECT_CMD)
$(TCL_INTERPRETER)
$@
.tcl
$(SYN_POST_PROJECT_CMD)
touch
$@
bitstream.tcl
:
echo
load_package flow
>>
$@
echo
$(TCL_OPEN)
>>
$@
echo
execute_flow
-compile
>>
$@
bitstream
:
project bitstream.tcl
$(SYN_PRE_BITSTREAM_CMD)
$(TCL_INTERPRETER)
$@
.tcl
$(SYN_POST_BITSTREAM_CMD)
touch
$@
CLEAN_TARGETS
:=
$(LIBS)
*
.rpt
*
.smsg
*
.summary
*
.done
*
.jdi
*
.pin
*
.qws db incremental_db
$(PROJECT)
.qsf
*
.qpf
clean
:
rm
-rf
$(CLEAN_TARGETS)
rm
-rf
project synthesize translate map par bitstream
rm
-rf
project.tcl synthesize.tcl translate.tcl map.tcl par.tcl bitstream.tcl files.tcl
mrproper
:
clean
rm
-rf
*
.sof
*
.pof
*
.jam
*
.jbc
*
.ekp
*
.jic
.PHONY
:
mrproper clean all
testsuite/034quartus_prop/Manifest.py
0 → 100644
View file @
4b2b141b
action
=
"synthesis"
language
=
"vhdl"
syn_family
=
"Arria V"
syn_device
=
"5agxmb1g4f"
syn_grade
=
"c4"
syn_package
=
"40"
syn_top
=
"gate"
syn_project
=
"gate_prj"
syn_tool
=
"quartus"
include_dirs
=
[
'.'
]
syn_properties
=
[{
'what'
:
'vwaht'
,
'name'
:
'vname'
,
'from'
:
'vfrom'
,
'value'
:
'vval'
,
'tag'
:
'vtag'
,
'to'
:
'vto'
,
'section_id'
:
'vsid'
}]
files
=
[
"../files/gate.vhdl"
]
testsuite/035quartus_err/Manifest.py
0 → 100644
View file @
4b2b141b
action
=
"synthesis"
language
=
"vhdl"
syn_family
=
"Arria V"
syn_device
=
"5agxmb1g4f"
syn_grade
=
"c4"
syn_package
=
"40"
syn_top
=
"gate"
syn_project
=
"gate_prj"
syn_tool
=
"quartus"
quartus_preflow
=
'err.tcl'
files
=
[
"../files/gate.vhdl"
]
testsuite/036quartus_err/Manifest.py
0 → 100644
View file @
4b2b141b
action
=
"synthesis"
language
=
"vhdl"
syn_family
=
"Arria V"
syn_device
=
"5agxmb1g4f"
syn_grade
=
"c4"
syn_package
=
"40"
syn_top
=
"gate"
syn_project
=
"gate_prj"
syn_tool
=
"quartus"
quartus_postflow
=
'err.tcl'
files
=
[
"../files/gate.vhdl"
]
testsuite/037quartus_err/Manifest.py
0 → 100644
View file @
4b2b141b
action
=
"synthesis"
language
=
"vhdl"
syn_family
=
"Arria V"
syn_device
=
"5agxmb1g4f"
syn_grade
=
"c4"
syn_package
=
"40"
syn_top
=
"gate"
syn_project
=
"gate_prj"
syn_tool
=
"quartus"
quartus_postmodule
=
'err.tcl'
files
=
[
"../files/gate.vhdl"
]
testsuite/038quartus_err/Manifest.py
0 → 100644
View file @
4b2b141b
action
=
"synthesis"
language
=
"vhdl"
syn_family
=
"Arria V"
syn_device
=
"5agxmb1g4f"
syn_grade
=
"c4"
syn_package
=
"40"
syn_top
=
"gate"
syn_project
=
"gate_prj"
syn_tool
=
"quartus"
syn_properties
=
[[]]
files
=
[
"../files/gate.vhdl"
]
testsuite/039quartus_err/Manifest.py
0 → 100644
View file @
4b2b141b
action
=
"synthesis"
language
=
"vhdl"
syn_device
=
"unknown"
syn_grade
=
"c4"
syn_package
=
"40"
syn_top
=
"gate"
syn_project
=
"gate_prj"
syn_tool
=
"quartus"
files
=
[
"../files/gate.vhdl"
]
testsuite/test_all.py
View file @
4b2b141b
...
...
@@ -110,6 +110,38 @@ def test_quartus():
def
test_quartus016
():
run_compare
(
path
=
"016quartus_nofam"
)
def
test_quartus033
():
run_compare
(
path
=
"033quartus"
)
def
test_quartus034
():
run
([],
path
=
"034quartus_prop"
)
def
test_quartus035
():
with
pytest
.
raises
(
SystemExit
)
as
_
:
run
([],
path
=
"035quartus_err"
)
print
(
os
.
getcwd
())
os
.
remove
(
'035quartus_err/Makefile'
)
def
test_quartus036
():
with
pytest
.
raises
(
SystemExit
)
as
_
:
run
([],
path
=
"036quartus_err"
)
os
.
remove
(
'036quartus_err/Makefile'
)
def
test_quartus037
():
with
pytest
.
raises
(
SystemExit
)
as
_
:
run
([],
path
=
"037quartus_err"
)
os
.
remove
(
'037quartus_err/Makefile'
)
def
test_quartus038
():
with
pytest
.
raises
(
SystemExit
)
as
_
:
run
([],
path
=
"038quartus_err"
)
os
.
remove
(
'038quartus_err/Makefile'
)
def
test_quartus039
():
with
pytest
.
raises
(
SystemExit
)
as
_
:
run
([],
path
=
"039quartus_err"
)
#os.remove('039quartus_err/Makefile')
def
test_riviera
():
run_compare
(
path
=
"017riviera"
)
...
...
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