testsuite: add a test for quartus QIP

44bef590 · Tristan Gingold · 5d71c1e7 · 44bef590 · 44bef590 · 44bef590
Commit 44bef590 authored Aug 23, 2022 by Tristan Gingold
Showing with 93 additions and 0 deletions

Makefile.ref testsuite/122quartus_qip/Makefile.ref +75 -0

Manifest.py testsuite/122quartus_qip/Manifest.py +14 -0

gate.qip testsuite/122quartus_qip/gate.qip +1 -0

test_all.py testsuite/test_all.py +3 -0

No files found.
--- a/testsuite/122quartus_qip/Makefile.ref
+++ b/testsuite/122quartus_qip/Makefile.ref
+########################################
+#  This file was generated by hdlmake  #
+#  http://ohwr.org/projects/hdl-make/  #
+########################################
+
+TOP_MODULE := gate3
+PROJECT := gate3_prj
+PROJECT_FILE := $(PROJECT).qpf
+TOOL_PATH := 
+TCL_INTERPRETER := quartus_sh -t
+ifneq ($(strip $(TOOL_PATH)),)
+TCL_INTERPRETER := $(TOOL_PATH)/$(TCL_INTERPRETER)
+endif
+
+SYN_FAMILY := Arria V
+SYN_DEVICE := 5agxmb1g4f40c4
+SYN_PACKAGE := 40
+SYN_GRADE := c4
+
+TCL_CREATE := project_new $(PROJECT)
+TCL_OPEN := project_open $(PROJECT)
+ifneq ($(wildcard $(PROJECT).qpf $(PROJECT).qsf),)
+TCL_CREATE := $(TCL_OPEN)
+endif
+
+#target for performing local synthesis
+all: bitstream
+
+files.tcl:
+		echo 'set_global_assignment -name QIP_FILE gate.qip' >> $@
+		echo 'set_global_assignment -name VHDL_FILE ../files/gate3.vhd -library work' >> $@
+
+SYN_PRE_PROJECT_CMD := 
+SYN_POST_PROJECT_CMD := 
+
+SYN_PRE_BITSTREAM_CMD := 
+SYN_POST_BITSTREAM_CMD := 
+
+project.tcl:
+		echo load_package flow >> $@
+		echo $(TCL_CREATE) >> $@
+		echo remove_all_global_assignments -name *_FILE >> $@
+		echo source files.tcl >> $@
+		echo set_global_assignment -name FAMILY \"$(SYN_FAMILY)\" >> $@
+		echo set_global_assignment -name DEVICE \"$(SYN_DEVICE)\" >> $@
+		echo set_global_assignment -name TOP_LEVEL_ENTITY \"$(TOP_MODULE)\" >> $@
+
+project: files.tcl project.tcl
+		$(SYN_PRE_PROJECT_CMD)
+		$(TCL_INTERPRETER) $@.tcl
+		$(SYN_POST_PROJECT_CMD)
+		touch $@
+
+bitstream.tcl:
+		echo load_package flow >> $@
+		echo $(TCL_OPEN) >> $@
+		echo execute_flow -compile >> $@
+
+bitstream: project bitstream.tcl
+		$(SYN_PRE_BITSTREAM_CMD)
+		$(TCL_INTERPRETER) $@.tcl
+		$(SYN_POST_BITSTREAM_CMD)
+		touch $@
+
+CLEAN_TARGETS := $(LIBS) *.rpt *.smsg *.summary *.done *.jdi *.pin *.qws db incremental_db a5_pin_model_dump.txt $(PROJECT).qsf *.sld *.qpf
+
+clean:
+		rm -rf $(CLEAN_TARGETS)
+		rm -rf project bitstream
+		rm -rf project.tcl bitstream.tcl files.tcl
+
+mrproper: clean
+		rm -rf *.sof *.pof *.jam *.jbc *.ekp *.jic
+
+.PHONY: mrproper clean all
--- a/testsuite/122quartus_qip/Manifest.py
+++ b/testsuite/122quartus_qip/Manifest.py
+action = "synthesis"
+language = "vhdl"
+
+syn_family  = "Arria V"
+syn_device  = "5agxmb1g4f"
+syn_grade   = "c4"
+syn_package = "40"
+
+syn_top = "gate3"
+syn_project = "gate3_prj"
+
+syn_tool = "quartus"
+
+files = [ "../files/gate3.vhd", ("gate.qip", "gate") ]
--- a/testsuite/122quartus_qip/gate.qip
+++ b/testsuite/122quartus_qip/gate.qip
+# Definition of module gate
--- a/testsuite/test_all.py
+++ b/testsuite/test_all.py
@@ -571,6 +571,9 @@ def test_explicit_dep_120():
 def test_explicit_err_121():
    run_compare(path="121explicit_err")

+def test_quartus_qip_122():
+    run_compare(path="122quartus_qip")
+
 @pytest.mark.xfail
 def test_xfail():
    """This is a self-consistency test: the test is known to fail"""