Commit 3cb452e2 authored by Tristan Gingold's avatar Tristan Gingold

*_parser.py: file is not parsed when parse() is called.

parent e915ea6f
...@@ -41,8 +41,8 @@ class VHDLParser(DepParser): ...@@ -41,8 +41,8 @@ class VHDLParser(DepParser):
def parse(self, dep_file): def parse(self, dep_file):
"""Parse the provided VHDL file and add the detected relations to it""" """Parse the provided VHDL file and add the detected relations to it"""
from .dep_file import DepRelation from .dep_file import DepRelation
if dep_file.is_parsed: assert not dep_file.is_parsed
return
logging.debug("Parsing %s", dep_file.path) logging.debug("Parsing %s", dep_file.path)
def _preprocess(vhdl_file): def _preprocess(vhdl_file):
......
...@@ -501,8 +501,7 @@ class VerilogParser(DepParser): ...@@ -501,8 +501,7 @@ class VerilogParser(DepParser):
def parse(self, dep_file): def parse(self, dep_file):
"""Parse the provided Verilog file and add to its properties """Parse the provided Verilog file and add to its properties
all of the detected dependency relations""" all of the detected dependency relations"""
if dep_file.is_parsed: assert not dep_file.is_parsed
return
logging.debug("Parsing %s", dep_file.path) logging.debug("Parsing %s", dep_file.path)
# assert isinstance(dep_file, DepFile), print("unexpected type: " + # assert isinstance(dep_file, DepFile), print("unexpected type: " +
# str(type(dep_file))) # str(type(dep_file)))
......
...@@ -38,8 +38,7 @@ class XCIParser(DepParser): ...@@ -38,8 +38,7 @@ class XCIParser(DepParser):
def parse(self, dep_file): def parse(self, dep_file):
"""Parse a Xilinx XCI IP description file to determine the provided module(s)""" """Parse a Xilinx XCI IP description file to determine the provided module(s)"""
if dep_file.is_parsed: assert not dep_file.is_parsed
return
logging.debug("Parsing %s", dep_file.path) logging.debug("Parsing %s", dep_file.path)
with open(dep_file.path) as f: with open(dep_file.path) as f:
......
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