Commit 38242bac authored by Tristan Gingold's avatar Tristan Gingold

Simplify code, determinism.

parent 6de42805
......@@ -326,15 +326,14 @@ def create_source_file(path, module, library=None,
include_dirs=None, is_include=False):
"""Function that analyzes the given arguments and returns a new HDL source
file of the appropriated type"""
if path is None or path == "":
raise RuntimeError("Expected a file path, got: " + str(path))
if not os.path.isabs(path):
path = os.path.abspath(path)
tmp = path.rsplit('.')
extension = tmp[len(tmp) - 1]
assert path
assert os.path.isabs(path)
_, extension = os.path.splitext(path)
assert extension[0] == '.'
# Remove '.'
extension = extension[1:]
logging.debug("add file " + path)
new_file = None
if extension in ['vhd', 'vhdl', 'vho']:
new_file = VHDLFile(path=path,
module=module,
......
......@@ -105,7 +105,7 @@ class MakefileVsim(MakefileSim):
# tell how to make libraries
self.write('LIB_IND := ')
self.write(' '.join([lib + shell.makefile_slash_char() +
"." + lib for lib in libs]))
"." + lib for lib in sorted(libs)]))
self.write('\n')
self.writeln()
self.writeln(
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment