@@ -42,7 +42,7 @@ We have a mailing list located at:
If you are seeking for consultancy and training services on advanced ``hdlmake`` use cases, you can get **commercial support from GL Research**, the company on charge of maintaining and developing the tool.
- **Company web site**: https://gl-research.com
- **Project manager**: Javier Garcia <jgarcia@gl-research.com>
- **Project manager**: Javier Garcia Lasheras <jgarcia@gl-research.com>
.. figure:: images/gl_research.*
:scale: 100
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@@ -1196,10 +1196,28 @@ If you want to use a different Intel Quartus version, you will need to fix the I
hdlmake supported actions/commands
==================================
Makefile generation (``makefile``)
----------------------------------
This is the default command for ``hdlmake`` and its basic behaviour will be defined by the value of the ``action`` manifest parameter in the hierachy ``Manifest.py``. ``action`` can be set to ``simulation`` or ``synthesis``, and the associated command sequence will be:
- **simulation**: generate a simulation makefile including all the files required for the defined testbench
- **synthesis**: generate a synthesis makefile including all the files required for bitstream generation
By using the ``-f FILENAME``, ``--filename FILENAME`` optional argument for the ``makefile`` command, we can choose the name of the synthesis or simulation Makefile that will be generated by ``hdlmake``.
In order to allow for a more agile development, we have included these shortcuts when using the ``hdlmake makefile`` command:
.. code-block:: bash
# These commands are equivalent
hdlmake makefile
hdlmake
# These commands are equivalent
hdlmake makefile -f FILENAME
hdlmake -f FILENAME
.. note:: in any case, it's supposed that all the required modules have been previously fetched. Otherwise, the process will fail.
Fetching submodules for a top module (``fetch``)
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@@ -1282,58 +1300,15 @@ The DELIMITER is defaulted to a white space, but it can be defined by using the
.. note:: the file list will be built considering that the Manifest.py stored in the folder from which we are launching the command is the root one.
Merge the different cores of a project (``merge-cores``)
Merges the entire synthesizable content of an project into a pair of VHDL/Verilog files
Create/update an FPGA project (``project``)
-------------------------------------------
When a top manifest has been written for synthesis, ``hdlmake`` reads the targeted tool and creates
a new specific project by adding both the whole file set from the module tree and the appropriated project properties.
In order to build the file list, ``hdlmake`` will parse the HDL files to find the required dependencies that a **top entity** needs to be successfuly compiled. We can configure the name of the HDL module that will be considered as the top entity to build the required file hierarchy by using the ``--top TOP`` optional argument to the ``list-files`` command. If no top entity is defined, all of the design files will be listed.
The project will be specific for the targeted synthesis tool and, if this already exists, the ``hdlmake`` will update its contents with the ones derived from the module/files hierachy in the Manifest tree.
Finally, by using the ``--reverse`` optional argument we are able to reverse the order of the listed files.
Currently, the following FPGA IDEs are supported:
+----------------------------+----------------+
| Vendor | FPGA IDE |
+============================+================+
| Xilinx | ISE |
+----------------------------+----------------+
| Xilinx | PlanAhead |
+----------------------------+----------------+
| Altera | Quartus II |
+----------------------------+----------------+
| Lattice Semi. | Diamond IDE |
+----------------------------+----------------+
| Microsemi (formerly Actel) | Libero IDE/SoC |
+----------------------------+----------------+
.. note:: both ``ise-project`` and ``quartus-project`` commands has been mantained in the code for backwards compatiblity. In any case, when any of these are found, the general ``project`` action is launched.
Makefile generation (``makefile``)
----------------------------------
This is the default command for ``hdlmake`` and its basic behaviour will be defined by the value of the ``action`` manifest parameter in the hierachy ``Manifest.py``. ``action`` can be set to ``simulation`` or ``synthesis``, and the associated command sequence will be:
- **simulation**: generate a simulation makefile including all the files required for the defined testbench
- **synthesis**: generate a synthesis makefile including all the files required for bitstream generation
By using the ``-f FILENAME``, ``--filename FILENAME`` optional argument for the ``makefile`` command, we can choose the name of the synthesis or simulation Makefile that will be generated by ``hdlmake``.
In order to allow for a more agile development, we have included these shortcuts when using the ``hdlmake makefile`` command:
