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Hdlmake
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32db68e1
Commit
32db68e1
authored
Feb 07, 2015
by
Garcia-Lasheras
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Add test counter example for Vivado
parent
dc0e2dd8
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Manifest.py
tests/counter/syn/spec_v4_vivado/verilog/Manifest.py
+14
-0
Manifest.py
tests/counter/syn/spec_v4_vivado/vhdl/Manifest.py
+14
-0
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tests/counter/syn/spec_v4_vivado/verilog/Manifest.py
0 → 100644
View file @
32db68e1
target
=
"xilinx"
action
=
"synthesis"
syn_device
=
"xc6slx45t"
syn_grade
=
"-3"
syn_package
=
"fgg484"
syn_top
=
"spec_top"
syn_project
=
"demo"
syn_tool
=
"vivado"
modules
=
{
"local"
:
[
"../../../top/spec_v4/verilog"
],
}
tests/counter/syn/spec_v4_vivado/vhdl/Manifest.py
0 → 100644
View file @
32db68e1
target
=
"xilinx"
action
=
"synthesis"
syn_device
=
"xc6slx45t"
syn_grade
=
"-3"
syn_package
=
"fgg484"
syn_top
=
"spec_top"
syn_project
=
"demo"
syn_tool
=
"vivado"
modules
=
{
"local"
:
[
"../../../top/spec_v4/vhdl"
],
}
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