Add the -g2012 option to the VHDL demo for IVerilog

parent 3ef43942
......@@ -2,6 +2,8 @@ action = "simulation"
sim_tool = "iverilog"
sim_top = "counter_tb"
iverilog_opt = "-g2012"
sim_pre_cmd ="echo IMPORTANT, IVerilog always needs a Verilog testbench, no matter if the DUT is written in VHDL!"
sim_post_cmd = "vvp counter_tb.vvp; gtkwave counter_tb.vcd"
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