Promote 'check_all_fetched_or_quit' to public method

parent 421036fe
......@@ -73,11 +73,11 @@ class Action(list):
return new_module
def _check_all_fetched_or_quit(self):
def check_all_fetched_or_quit(self):
"""Check if every module in the pool is fetched"""
if not self.is_everything_fetched():
logging.error(
"Fetching must be done before makefile generation.\n"
"Fetching must be done before continuing.\n"
"The following modules remains unfetched:\n"
"%s",
"\n".join([str(m) for m in self if not m.isfetched])
......
......@@ -131,7 +131,7 @@ class ActionCore(Action):
def merge_cores(self):
"""Merge the design into a single VHDL and a single Verilog file"""
self._check_all_fetched_or_quit()
self.check_all_fetched_or_quit()
logging.info("Merging all cores into one source file per language.")
flist = self.build_file_set()
base = self.env.options.dest
......
......@@ -39,8 +39,8 @@ class WriterSim(object):
def simulation_makefile(self):
"""Execute the simulation action"""
self.pool._check_all_fetched_or_quit()
self._check_simulation_makefile()
self.pool.check_all_fetched_or_quit()
tool_name = self.pool.get_top_module().manifest_dict["sim_tool"]
tool_dict = {"iverilog": self.iverilog,
"isim": self.isim,
......@@ -129,8 +129,8 @@ class WriterSyn(object):
def synthesis_project(self):
"""Generate a project for the specific synthesis tool"""
self.pool._check_all_fetched_or_quit()
self._check_synthesis_project()
self.pool.check_all_fetched_or_quit()
tool_object = self._load_synthesis_tool()
tool_info = tool_object.TOOL_INFO
path_key = tool_info['id'] + '_path'
......
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