Fix incl_makefiles being ignored at synthesis and simulation

parent 4043e15b
......@@ -1402,7 +1402,7 @@ Top Manifest variables
+================+==============+=================================================================+===========+
| action | str | What is the action that should be taken (simulation/synthesis) | "" |
+----------------+--------------+-----------------------------------------------------------------+-----------+
| incl_makefiles | list, str | List of .mk files appended to toplevel makefile | [] |
| incl_makefiles | list | List of .mk files included in the generated makefile | [] |
+----------------+--------------+-----------------------------------------------------------------+-----------+
| language | str | Select the default HDL language if required (verilog, vhdl) | "vhdl" |
+----------------+--------------+-----------------------------------------------------------------+-----------+
......
......@@ -34,6 +34,7 @@ class ToolSim(ToolMakefile):
_check_simulation_manifest(config)
self.makefile_setup(config, fileset, filename=filename)
self.makefile_check_tool('sim_path')
self.makefile_includes()
self._makefile_sim_top()
self._makefile_sim_options()
self._makefile_sim_local()
......
......@@ -133,10 +133,11 @@ class ToolMakefile(object):
def makefile_includes(self):
"""Add the included makefiles that need to be previously loaded"""
#for file_aux in self.top_module.incl_makefiles:
# if os.path.exists(file_aux):
# self.write("include %s\n" % file_aux)
pass
if self.manifest_dict.get("incl_makefiles") is not None:
for file_aux in self.manifest_dict["incl_makefiles"]:
if os.path.exists(file_aux):
self.writeln("include %s" % file_aux)
self.writeln()
def makefile_clean(self):
"""Print the Makefile target for cleaning intermediate files"""
......
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