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Hdlmake
Commit 24de6c34 authored by Tristan Gingold's avatar Tristan Gingold
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tools: use class attribute SIMULATOR_CONTROLS directly.

parent 6d5d5fc0
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Showing with 7 additions and 9 deletions
hdlmake/tools/ghdl.py
View file @ 24de6c34
......@@ -53,7 +53,6 @@ class ToolGHDL(MakefileSim):
def __init__(self):
super(ToolGHDL, self).__init__()
self._simulator_controls.update(ToolGHDL.SIMULATOR_CONTROLS)
def _makefile_sim_options(self):
"""Print the GHDL options to the Makefile"""
......@@ -67,6 +66,6 @@ class ToolGHDL(MakefileSim):
def _makefile_sim_compilation(self):
"""Print the GDHL simulation compilation target"""
self.writeln("simulation: $(VERILOG_OBJ) $(VHDL_OBJ)")
self.writeln("\t\t" + self._simulator_controls['compiler'])
self.writeln("\t\t" + self.SIMULATOR_CONTROLS['compiler'])
self.writeln('\n')
self._makefile_sim_dep_files()
hdlmake/tools/iverilog.py
View file @ 24de6c34
......@@ -56,12 +56,11 @@ class ToolIVerilog(MakefileSim):
def __init__(self):
super(ToolIVerilog, self).__init__()
self._simulator_controls.update(ToolIVerilog.SIMULATOR_CONTROLS)
def _makefile_sim_compilation(self):
"""Generate compile simulation Makefile target for IVerilog"""
self.writeln("simulation: include_dirs $(VERILOG_OBJ) $(VHDL_OBJ)")
self.writeln("\t\t" + self._simulator_controls['compiler'])
self.writeln("\t\t" + self.SIMULATOR_CONTROLS['compiler'])
self.writeln()
self.writeln("include_dirs:")
self.writeln("\t\techo \"# IVerilog command file,"
......
hdlmake/tools/makefilesim.py
View file @ 24de6c34
......@@ -20,9 +20,10 @@ class MakefileSim(ToolMakefile):
"""Class that provides the Makefile writing methods and status"""
SIMULATOR_CONTROLS = {}
def __init__(self):
super(MakefileSim, self).__init__()
self._simulator_controls = {}
def write_makefile(self, config, fileset, filename=None):
"""Execute the simulation action"""
......@@ -126,7 +127,7 @@ TOP_MODULE := {top_module}
command_key = 'vlog'
if is_include:
continue
self.writeln("\t\t" + self._simulator_controls[command_key])
self.writeln("\t\t" + self.SIMULATOR_CONTROLS[command_key])
self.write("\t\t@" + shell.mkdir_command() + " $(dir $@)")
self.writeln(" && " + shell.touch_command() + " $@ \n")
self.writeln()
......
hdlmake/tools/vivado_sim.py
View file @ 24de6c34
......@@ -54,11 +54,10 @@ class ToolVivadoSim(MakefileSim):
def __init__(self):
super(ToolVivadoSim, self).__init__()
self._simulator_controls.update(ToolVivadoSim.SIMULATOR_CONTROLS)
def _makefile_sim_compilation(self):
"""Generate compile simulation Makefile target for Vivado Simulator"""
self.writeln("simulation: $(VERILOG_OBJ) $(VHDL_OBJ)")
self.writeln("\t\t" + ToolVivadoSim.SIMULATOR_CONTROLS['compiler'])
self.writeln("\t\t" + self.SIMULATOR_CONTROLS['compiler'])
self.writeln()
self._makefile_sim_dep_files()
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