Fix Active-HDL support in Windows Cmd and PowerShell

parent 13f5d20e
...@@ -56,31 +56,31 @@ class ToolActiveHDL(ToolSim): ...@@ -56,31 +56,31 @@ class ToolActiveHDL(ToolSim):
"""Print Makefile compilation target for Aldec Active-HDL simulator""" """Print Makefile compilation target for Aldec Active-HDL simulator"""
fileset = self.fileset fileset = self.fileset
self.writeln("simulation:") self.writeln("simulation:")
self.writeln("\t\techo \"# Active-HDL command file," self.writeln("\t\techo # Active-HDL command file,"
" generated by HDLMake\" > run.command") " generated by HDLMake > run.command")
self.writeln() self.writeln()
self.writeln("\t\techo \"# Create library and set as" self.writeln("\t\techo # Create library and set as"
" default target\" >> run.command") " default target >> run.command")
self.writeln("\t\techo \"alib work\" >> run.command") self.writeln("\t\techo alib work >> run.command")
self.writeln("\t\techo \"set worklib work\" >> run.command") self.writeln("\t\techo set worklib work >> run.command")
self.writeln() self.writeln()
self.writeln( self.writeln(
"\t\techo \"# Compiling HDL source files\" >> run.command") "\t\techo # Compiling HDL source files >> run.command")
for vl_file in fileset.filter(VerilogFile): for vl_file in fileset.filter(VerilogFile):
self.writeln( self.writeln(
"\t\techo \"alog " + "\t\techo alog \"" +
vl_file.rel_path( vl_file.rel_path(
) + ) +
"\" >> run.command") "\" >> run.command")
for sv_file in fileset.filter(SVFile): for sv_file in fileset.filter(SVFile):
self.writeln( self.writeln(
"\t\techo \"alog " + "\t\techo alog \"" +
sv_file.rel_path( sv_file.rel_path(
) + ) +
"\" >> run.command") "\" >> run.command")
for vhdl_file in fileset.filter(VHDLFile): for vhdl_file in fileset.filter(VHDLFile):
self.writeln( self.writeln(
"\t\techo \"acom " + "\t\techo acom \"" +
vhdl_file.rel_path( vhdl_file.rel_path(
) + ) +
"\" >> run.command") "\" >> run.command")
......
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