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Commit 21d32628 authored by Tristan Gingold's avatar Tristan Gingold
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makefilevsim.py: add more determinism.

parent 9f8c7189
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hdlmake/tools/makefilevsim.py
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...@@ -166,8 +166,9 @@ class MakefileVsim(MakefileSim): ...@@ -166,8 +166,9 @@ class MakefileVsim(MakefileSim):
lib, purename, "." + purename + "_" + vhdl.extension()), lib, purename, "." + purename + "_" + vhdl.extension()),
vhdl.rel_path())) vhdl.rel_path()))
# list dependencies, do not include the target file # list dependencies, do not include the target file
for dep_file in [dfile for dfile in vhdl.depends_on for dep_file in sorted([dfile for dfile in vhdl.depends_on
if dfile is not vhdl]: if dfile is not vhdl],
key=(lambda x: x.path)):
if dep_file in fileset: if dep_file in fileset:
name = dep_file.purename name = dep_file.purename
extension = dep_file.extension() extension = dep_file.extension()
......
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