Commit 1f6dad04 authored by Tristan Gingold's avatar Tristan Gingold

dep_file: remove unused include dependency.

parent 6d968e95
...@@ -35,17 +35,16 @@ class DepRelation(object): ...@@ -35,17 +35,16 @@ class DepRelation(object):
"""Class used to create instances representing HDL dependency relations""" """Class used to create instances representing HDL dependency relations"""
# rel_type # rel_type
# Architecture is never required.
ENTITY = 1 ENTITY = 1
PACKAGE = 2 PACKAGE = 2
INCLUDE = 3 ARCHITECTURE = 3
ARCHITECTURE = 4
MODULE = ENTITY MODULE = ENTITY
def __init__(self, obj_name, lib_name, rel_type): def __init__(self, obj_name, lib_name, rel_type):
assert rel_type in [ assert rel_type in [
DepRelation.ENTITY, DepRelation.ENTITY,
DepRelation.PACKAGE, DepRelation.PACKAGE,
DepRelation.INCLUDE,
DepRelation.ARCHITECTURE, DepRelation.ARCHITECTURE,
DepRelation.MODULE] DepRelation.MODULE]
self.rel_type = rel_type self.rel_type = rel_type
...@@ -62,7 +61,6 @@ class DepRelation(object): ...@@ -62,7 +61,6 @@ class DepRelation(object):
ostr = { ostr = {
self.ENTITY: "entity", self.ENTITY: "entity",
self.PACKAGE: "package", self.PACKAGE: "package",
self.INCLUDE: "include/header",
self.ARCHITECTURE: "architecture", self.ARCHITECTURE: "architecture",
self.MODULE: "module"} self.MODULE: "module"}
return "%s '%s.%s'" % (ostr[self.rel_type], return "%s '%s.%s'" % (ostr[self.rel_type],
......
...@@ -76,6 +76,7 @@ class VHDLParser(DepParser): ...@@ -76,6 +76,7 @@ class VHDLParser(DepParser):
DepRelation(pkg_name, lib_name, DepRelation.PACKAGE)) DepRelation(pkg_name, lib_name, DepRelation.PACKAGE))
return "<hdlmake use_pattern %s.%s>" % (lib_name, pkg_name) return "<hdlmake use_pattern %s.%s>" % (lib_name, pkg_name)
buf = re.sub(use_pattern, do_use, buf) buf = re.sub(use_pattern, do_use, buf)
# new entity # new entity
entity_pattern = re.compile( entity_pattern = re.compile(
r"^\s*entity\s+(?P<name>\w+)\s+is\s+(?:port|generic|end)" r"^\s*entity\s+(?P<name>\w+)\s+is\s+(?:port|generic|end)"
...@@ -214,7 +215,7 @@ class VHDLParser(DepParser): ...@@ -214,7 +215,7 @@ class VHDLParser(DepParser):
buf = re.sub(function_pattern, do_function, buf) buf = re.sub(function_pattern, do_function, buf)
# instantions # instantiations
libraries = set([dep_file.library]) libraries = set([dep_file.library])
instance_pattern = re.compile( instance_pattern = re.compile(
r"^\s*(?P<LABEL>\w+)\s*:" r"^\s*(?P<LABEL>\w+)\s*:"
......
...@@ -588,6 +588,4 @@ class VerilogParser(DepParser): ...@@ -588,6 +588,4 @@ class VerilogParser(DepParser):
if match: if match:
do_inst(match) do_inst(match)
m_inside_module.subn(do_module, buf) m_inside_module.subn(do_module, buf)
dep_file.add_provide(
DepRelation(dep_file.path, None, DepRelation.INCLUDE))
dep_file.is_parsed = True dep_file.is_parsed = True
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