Add the counter test for IceStorm synthesis

parent 852c1f43
action = "synthesis"
syn_device = "1k"
syn_grade = "dummy"
syn_package = "tq144"
syn_top = "icestick_top"
syn_project = "demo"
syn_tool = "icestorm"
modules = {
"local" : [ "../../../top/icestick/verilog" ]
}
set_io led_o_0 99
set_io led_o_1 98
set_io led_o_2 97
set_io led_o_3 96
set_io led_o_4 95
set_io clock_i 21
files = [ "icestick_top.v", "../icestick.pcf" ]
modules = {
"local" : [ "../../../modules/counter/verilog" ],
}
//---------------------------------------------------------------------
// Design : Counter verilog top module, iCEstick (Lattice iCE40)
// Author : Javier D. Garcia-Lasheras
//---------------------------------------------------------------------
module icestick_top (
clock_i,
led_o_0,
led_o_1,
led_o_2,
led_o_3,
led_o_4,
);
input clock_i;
output led_o_0, led_o_1, led_o_2, led_o_3, led_o_4;
wire s_clock, s_clear, s_count;
wire [7:0] s_Q;
counter u1(
.clock(s_clock),
.clear(s_clear),
.count(s_count),
.Q(s_Q)
);
assign s_clock = clock_i;
assign s_clear = 0;
assign s_count = 1;
assign led_o_4 = s_Q[7];
assign led_o_3 = s_Q[6];
assign led_o_2 = s_Q[5];
assign led_o_1 = s_Q[4];
assign led_o_0 = s_Q[3];
endmodule
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