Commit 15f18ae4 authored by Tristan Gingold's avatar Tristan Gingold

Add a test for extra_modules.

parent 8c6c008f
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := gate_tb
PWD := $(shell pwd)
MODELSIM_INI_PATH := ../linux_fakebin/..
VCOM_FLAGS := -quiet -modelsimini modelsim.ini
VSIM_FLAGS :=
VLOG_FLAGS := -quiet -modelsimini modelsim.ini
VMAP_FLAGS := -modelsimini modelsim.ini
#target for performing local simulation
local: sim_pre_cmd simulation sim_post_cmd
VERILOG_SRC := ../files/gate_tb.v \
VERILOG_OBJ := work/gate_tb/.gate_tb_v \
VHDL_SRC :=
VHDL_OBJ :=
INCLUDE_DIRS :=
LIBS := work
LIB_IND := work/.work
simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ) : modelsim.ini
$(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
cp $< . 2>&1
work/.work:
(vlib work && vmap $(VMAP_FLAGS) work && touch work/.work )|| rm -rf work
work/gate_tb/.gate_tb_v: ../files/gate_tb.v
vlog -work work $(VLOG_FLAGS) ${INCLUDE_DIRS} $<
@mkdir -p $(dir $@) && touch $@
# USER SIM COMMANDS
sim_pre_cmd:
sim_post_cmd:
CLEAN_TARGETS := $(LIBS) modelsim.ini transcript
clean:
rm -rf $(CLEAN_TARGETS)
mrproper: clean
rm -rf *.vcd *.wlf
.PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation
action = "simulation"
sim_tool="modelsim"
top_module = "gate_tb"
files = [ "../files/gate_tb.v" ]
extra_modules = [ "../files/gate.vhdl" ]
......@@ -417,6 +417,9 @@ def test_err_syn_package():
def test_err_syn_top():
run_compare(path="070err_syntop")
def test_extra_modules():
run_compare(path="076extra_modules")
@pytest.mark.xfail
def test_xfail():
"""This is a self-consistency test: the test is known to fail"""
......
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