Bitfile_target is only used in the unused old iverilog recipe

parent 0df84159
......@@ -130,10 +130,6 @@ class ManifestParser(ConfigParser):
# Disallow certain files in Xilinx Synthesis flow but use in simulation
self.add_option('sim_only_files', default=[], help="List of files that are used only in simulation", type=[])
self.add_type('sim_only_files', type='')
# Adding .bit targets, sort of like having multiple syn_top for LBNL
# xil_syn workflow
self.add_option('bit_file_targets', default=[], help="List of files that are used only in simulation", type=[])
self.add_type('bit_file_targets', type='')
def add_manifest(self, manifest):
return self.add_config_file(manifest.path)
......
......@@ -232,7 +232,6 @@ class Module(ModuleSynthesis, ModuleSimulation):
del extra_context["include_dirs"]
del extra_context["sim_only_files"]
del extra_context["incl_makefiles"]
del extra_context["bit_file_targets"]
del extra_context["library"]
extra_context["__manifest"] = self.path
......@@ -253,7 +252,6 @@ class Module(ModuleSynthesis, ModuleSimulation):
self._process_manifest_files()
self._process_manifest_modules()
self._process_manifest_altera()
self._process_manifest_bitfile_targets()
self._process_manifest_force_tool()
self._process_manifest_included_makefiles()
......@@ -402,15 +400,6 @@ class Module(ModuleSynthesis, ModuleSimulation):
self.hw_tcl_filename = self.manifest_dict["hw_tcl_filename"]
def _process_manifest_bitfile_targets(self):
from .srcfile import SourceFileSet
# Bit file targets
self.bit_file_targets = SourceFileSet()
if len(self.manifest_dict["bit_file_targets"]) != 0:
paths = self._make_list_of_paths(self.manifest_dict["bit_file_targets"])
self.bit_file_targets = self._create_file_list_from_paths(paths=paths)
def _process_manifest_force_tool(self):
if self.manifest_dict["force_tool"]:
ft = self.manifest_dict["force_tool"]
......
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