Commit 01f1b753 authored by Paweł Szostek's avatar Paweł Szostek

implement force_tool option in ise synthesis

parent b7e8f38e
......@@ -29,7 +29,7 @@ import sys
from manifest_parser import ManifestParser
from module_pool import ModulePool
from env import Env
from action import (CleanModules, FetchModules, GenerateFetchMakefile,
from action import (CheckCondition, CleanModules, FetchModules, GenerateFetchMakefile,
GenerateISEMakefile, GenerateISEProject, ListFiles,
ListModules, MergeCores, GenerateQuartusProject,
GenerateRemoteSynthesisMakefile, GenerateSimulationMakefile)
......@@ -40,7 +40,7 @@ except:
def main():
parser = argparse.ArgumentParser("hdlmake")
parser = argparse.ArgumentParser("hdlmake", formatter_class=argparse.ArgumentDefaultsHelpFormatter)
subparsers = parser.add_subparsers(title="commands", dest="command")
check_env = subparsers.add_parser("check-env", help="check environment for HDLMAKE-related settings")
......@@ -48,6 +48,7 @@ def main():
check_manifest.add_argument("--top", help="indicate path to the top manifest", default=None)
manifest_help = subparsers.add_parser("manifest-help", help="print manifest file variables description")
auto = subparsers.add_parser("auto", help="default action for hdlmake. Run when no args are given")
auto.add_argument("--noprune", help="prevent hdlmake from pruning unneeded files", default=False, action="store_true")
fetch = subparsers.add_parser("fetch", help="fetch and/or update remote modules listed in Manifest")
fetch.add_argument("--flatten", help="`flatten' modules' hierarchy by storing everything in top module's fetchto direactoru",
default=False, action="store_true")
......@@ -61,6 +62,11 @@ def main():
merge_cores.add_argument("--dest", help="name for output merged file", dest="dest", default=None)
ise_proj = subparsers.add_parser("ise-project", help="create/update an ise project including list of project")
quartus_proj = subparsers.add_parser("quartus-project", help="create/update a quartus project including list of project")
condition_check = argparse.ArgumentParser()
condition_check.add_argument("--tool", dest="tool", required=True)
condition_check.add_argument("--reference", dest="reference", required=True)
condition_check.add_argument("--condition", dest="condition", required=True)
# version = subparsers.add_parser("version", help="print version id of this Hdlmake build")
parser.add_argument("--py", dest="arbitrary_code",
......@@ -71,6 +77,12 @@ def main():
if len(sys.argv) < 2:
options = parser.parse_args(['auto'])
elif sys.argv[1] == "_conditioncheck":
options = condition_check.parse_args(sys.argv[2:])
env = Env(options)
env.check_env()
CheckCondition(modules_pool=None, options=options, env=env).run()
quit()
else:
options = parser.parse_args(sys.argv[1:])
global_mod.options = options
......@@ -155,11 +167,9 @@ def main():
action = ListFiles
elif options.command == "merge-cores":
action = MergeCores
elif options.command == "quartus-project":
action = GenerateQuartusProject
action_instance = action(modules_pool=modules_pool, options=options, env=env)
try:
......
......@@ -19,6 +19,7 @@
# You should have received a copy of the GNU General Public License
# along with Hdlmake. If not, see <http://www.gnu.org/licenses/>.
from check_condition import CheckCondition
from check_manifest import CheckManifest
from clean import CleanModules
from default import Default
......
#!/usr/bin/python
# -*- coding: utf-8 -*-
#
# Copyright (c) 2013 CERN
# Author: Pawel Szostek (pawel.szostek@cern.ch)
#
# This file is part of Hdlmake.
#
# Hdlmake is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# Hdlmake is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with Hdlmake. If not, see <http://www.gnu.org/licenses/>.
from __future__ import print_function
import logging
import sys
from action import Action
import re
class CheckCondition(Action):
def _compare(self, local, reference, cond):
if cond == "==":
return local == reference
elif cond == "<":
return local < reference
elif cond == ">":
return local > reference
elif cond == "<=":
return local <= reference
elif cond == ">=":
return local >= reference
else:
sys.exit(1)
def run(self):
tool = self.options.tool
if tool == "ise":
ver = self.env["ise_version"]
if not ver:
sys.exit(1)
ref = self.options.reference
ver = float(ver)
ref = float(ref)
elif tool == "quartus":
ver = self.env["quartus_version"]
if not ver:
sys.exit(1)
ref = self.options.reference
elif tool == "modelsim":
ver = self.env["modelsim_version"]
if not ver:
sys.exit(1)
ref = self.options.reference
elif tool == "iverilog":
ver = self.env["iverilog_version"]
if not ver:
sys.exit(1)
ref = self.options.reference
ver = int(ver.replace('.', ''))
ref = int(ref.replace('.', ''))
elif tool == "isim":
ver = self.env["ise_version"]
if not ver:
sys.exit(1)
ref = self.options.reference
ver = re.sub("[a-zA-Z]", '', ver)
ref = re.sub("[a-zA-Z]", '', ref)
else:
logging.error("Unknown tool: %s" % tool)
sys.exit("\nExiting")
comparison = self._compare(ver, ref, self.options.condition)
sys.exit(int(not comparison))
......@@ -287,8 +287,6 @@ class Env(dict):
else:
print("To use screen, set it to '1'.")
def _get(self, name):
assert not name.startswith("HDLMAKE_")
assert isinstance(name, basestring)
......
......@@ -92,15 +92,15 @@ class MakefileWriter(object):
user_tmpl = user_tmpl.format("$(HDLMAKE_RSYNTH_USER)#take the value from the environment")
test_tmpl = """__test_for_remote_synthesis_variables:
ifeq (x$(USER),x)
\t@echo "Remote synthesis user is not set.
\t@echo "Remote synthesis user is not set.\
You can set it by editing variable USER in the makefile or setting env. variable HDLMAKE_RSYNTH_USER." && false
endif
ifeq (x$(SERVER),x)
\t@echo "Remote synthesis server is not set.
\t@echo "Remote synthesis server is not set.\
You can set it by editing variable SERVER in the makefile or setting env. variable HDLMAKE_RSYNTH_SERVER." && false
endif
ifeq (x$(ISE_PATH),x)
\t@echo "Remote synthesis server is not set.
\t@echo "Remote synthesis server is not set.\
You can set it by editing variable ISE_PATH in the makefile or setting env. variable HDLMAKE_RSYNTH_ISE_PATH." && false
endif
"""
......@@ -207,11 +207,14 @@ webtalk_pn.xml \
run.tcl
#target for performing local synthesis
local: syn_pre_cmd
local: syn_pre_cmd check_tool
\t\techo "project open $$(PROJECT)" > run.tcl
\t\techo "process run {Generate Programming File} -force rerun_all" >> run.tcl
\t\t${ise_path}/xtclsh run.tcl
check_tool:
\t\t${check_tool}
syn_post_cmd: local
\t\t${syn_post_cmd}
......@@ -227,7 +230,7 @@ clean:
mrproper:
\t\trm -f *.bit *.bin *.mcs
.PHONY: mrproper clean syn_pre_scipt syn_post_cmd local
.PHONY: mrproper clean syn_pre_scipt syn_post_cmd local check_tool
""")
self.initialize()
......@@ -241,9 +244,20 @@ mrproper:
else:
syn_post_cmd = ''
if top_mod.force_tool:
ft = top_mod.force_tool
check_tool = """python $(HDLMAKE_HDLMAKE_PATH)/hdlmake _conditioncheck --tool {tool} --reference {reference} --condition "{condition}"\\
|| (echo "{tool} version does not meet condition: {condition} {reference}" && false)
""".format(tool=ft[0],
condition=ft[1],
reference=ft[2])
else:
check_tool = ''
makefile_text = makefile_tmplt.substitute(syn_top=top_mod.syn_top,
project_name=top_mod.syn_project,
ise_path=ise_path,
check_tool=check_tool,
syn_pre_cmd=syn_pre_cmd,
syn_post_cmd=syn_post_cmd)
self.write(makefile_text)
......
......@@ -65,7 +65,8 @@ class ManifestParser(ConfigParser):
self.add_option('top_module', default=None, help="Top level entity for synthesis and simulation", type='')
self.add_delimiter()
self.add_option('force_tool', default=None, help="Force certain version of a tool, e.g. 'ise-13.2'")
self.add_option('force_tool', default=None, help="Force certain version of a tool, e.g. 'ise < 13.2' or 'iverilog == 0.9.6",
type='')
self.add_delimiter()
self.add_option('include_dirs', default=None, help="Include dirs for Verilog sources", type=[])
......
......@@ -80,6 +80,7 @@ class Module(object):
self._files = None
self.manifest = None
self.incl_makefiles = []
self.force_tool = None
self.syn_device = None
self.syn_grade = None
self.syn_package = None
......@@ -256,6 +257,12 @@ class Module(object):
self.vlog_opt = self.manifest_dict["vlog_opt"]
self.iverilog_opt = self.manifest_dict["iverilog_opt"]
self.sim_tool = self.manifest_dict["sim_tool"]
if self.manifest_dict["force_tool"]:
ft = self.manifest_dict["force_tool"]
self.force_tool = ft.split(' ')
if len(self.force_tool) != 3:
logging.warning("Incorrect force_tool format %s. Ignoring" % self.force_tool)
self.force_tool = None
if "top_module" in self.manifest_dict:
self.top_module = self.manifest_dict["top_module"]
......
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