srcfile.py: remove redundant code

01309173 · Paweł Szostek · 38c22f5d · 01309173
Commit 01309173 authored Jun 23, 2013 by Paweł Szostek
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srcfile.py src/srcfile.py +1 -2

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--- a/src/srcfile.py
+++ b/src/srcfile.py
@@ -304,8 +304,7 @@ class VerilogFile(SourceFile):


 class SVFile(VerilogFile):
-    def __init__(self, path, library=None, vlog_opt=None, include_dirs=None):
-        VerilogFile.__init__(self, path, library, vlog_opt, include_dirs)
+    pass


 class UCFFile(File):