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Hdlmake
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Cycle Analytics
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Hdlmake
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aabe6c840ed4d8414dd62bb67781e10672184103
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hdl-make
tests
counter
sim
modelsim
verilog
Manifest.py
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Disable optimisations in order to have visibility of counter's signal.
· aabe6c84
Adrian Fiergolski
authored
Oct 10, 2014
aabe6c84
Manifest.py
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