srcfile.py 8.29 KB
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# -*- coding: utf-8 -*-
#
# Copyright (c) 2013, 2014 CERN
# Author: Pawel Szostek (pawel.szostek@cern.ch)
# Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com)
#
# This file is part of Hdlmake.
#
# Hdlmake is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# Hdlmake is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with Hdlmake.  If not, see <http://www.gnu.org/licenses/>.
#

"""Module providing the source file class and a set of classes
representing the different possible files and file extensions"""

from __future__ import print_function
from __future__ import absolute_import
import os
import logging

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from ..util import path as path_mod
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from .dep_file import DepFile, File
import six


class SourceFile(DepFile):

    """This is a class acting as a base for the different
    HDL sources files, i.e. those that can be parsed"""

    def __init__(self, path, module, library):
        assert isinstance(path, six.string_types)
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        self.is_include = False
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        self.library = library
        if not library:
            self.library = "work"
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        DepFile.__init__(self, path=path, module=module)
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    def __hash__(self):
        return hash(self.path + self.library)


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# SOURCE FILES

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class VHDLFile(SourceFile):

    """This is the class providing the generic VHDL file"""

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    def __init__(self, path, module, library=None):
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        SourceFile.__init__(self, path=path, module=module, library=library)
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        from .vhdl_parser import VHDLParser
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        self.parser = VHDLParser(self)
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class VerilogFile(SourceFile):

    """This is the class providing the generic Verilog file"""

    def __init__(self, path, module, library=None,
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                 include_dirs=None, is_include=False):
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        SourceFile.__init__(self, path=path, module=module, library=library)
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        from .vlog_parser import VerilogParser
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        self.include_dirs = []
        if include_dirs:
            self.include_dirs.extend(include_dirs)
        self.include_dirs.append(path_mod.relpath(self.dirname))
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        self.parser = VerilogParser(self)
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        self.is_include = is_include
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class SVFile(VerilogFile):
    """This is the class providing the generic SystemVerilog file"""
    pass


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# TCL COMMAND FILE
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class TCLFile(File):
    """This is the class providing the Tool Command Language file"""
    pass


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# XILINX FILES

class UCFFile(File):
    """This is the class providing the User Constraint Guide file"""
    pass


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class XISEFile(File):
    """This is the class providing the new Xilinx ISE project file"""
    pass


class CDCFile(File):
    """This is the class providing the Xilinx ChipScope Definition
    and Connection file"""
    pass


class XMPFile(File):
    """Xilinx Embedded Micro Processor"""
    pass


class PPRFile(File):
    """Xilinx PlanAhead Project"""
    pass


class XPRFile(File):
    """Xilinx Vivado Project"""
    pass


class BDFile(File):
    """Xilinx Block Design"""
    pass


class XCOFile(File):
    """Xilinx Core Generator File"""
    pass


class NGCFile(File):
    """Xilinx Generated Netlist File"""
    pass


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class XDCFile(File):
    """Xilinx Design Constraint File"""
    pass


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class XCFFile(File):
    """Xilinx XST Constraint File"""
    pass


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class COEFile(File):
    """Xilinx Coefficient File"""
    pass


class MIFFile(File):
    """Xilinx Memory Initialization File"""
    pass


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class RAMFile(File):
    """Xilinx RAM  File"""
    pass


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class VHOFile(File):
    """Xilinx VHDL Template File"""
    pass


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class BMMFile(File):
    """Xilinx Block Memory Map File"""
    pass


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class VEOFile(File):
    """Xilinx Verilog Template File"""
    pass


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class XCIFile(SourceFile):
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    """Xilinx Core IP File"""

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    def __init__(self, path, module, library=None):
        SourceFile.__init__(self, path=path, module=module, library=library)
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        from .xci_parser import XCIParser
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        self.parser = XCIParser(self)
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XILINX_FILE_DICT = {
    'xise': XISEFile,
    'ise': XISEFile,
    'ngc': NGCFile,
    'ucf': UCFFile,
    'cdc': CDCFile,
    'xmp': XMPFile,
    'ppr': PPRFile,
    'xpr': XPRFile,
    'bd': BDFile,
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    'xco': XCOFile,
    'xdc': XDCFile,
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    'xcf': XCFFile,
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    'coe': COEFile,
    'mif': MIFFile,
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    'ram': RAMFile,
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    'vho': VHOFile,
    'veo': VEOFile,
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    'bmm': BMMFile,
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    'xci': XCIFile}
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# SYNOPSYS FILES

class SDCFile(File):
    """Synopsys Design Constraints"""
    pass


# LATTICE FILES

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class LDFFile(File):
    """Lattice Diamond Project File"""
    pass


class LPFFile(File):
    """Lattice Preference/Constraint File"""
    pass

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class PCFFile(File):
    """Icestorm Physical constraints File"""
    pass
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class EDFFile(File):
    """EDIF Netlist Files"""
    pass


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LATTICE_FILE_DICT = {
    'ldf': LDFFile,
    'lpf': LPFFile,
    'edf': EDFFile,
    'edif': EDFFile,
    'edi': EDFFile,
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    'edn': EDFFile,
    'pcf': PCFFile}
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# MICROSEMI/ACTEL FILES

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class PDCFile(File):
    """Physical Design Constraints"""
    pass


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MICROSEMI_FILE_DICT = {
    'pdc': PDCFile}


# OHR FILES

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class WBGenFile(File):
    """Wishbone generator file"""
    pass


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# INTEL/ALTERA FILES

class QIPFile(File):
    """This is the class providing the Altera Quartus IP file"""
    pass


class QSYSFile(File):
    """Qsys - Altera's System Integration Tool"""
    pass


class DPFFile(File):
    """This is the class providing Altera Quartus Design Protocol File"""
    pass


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class QSFFile(File):
    """Quartus Settings File"""
    pass


class BSFFile(File):
    """Quartus Block Symbol File"""
    pass


class BDFFile(File):
    """Quartus Block Design File"""
    pass


class TDFFile(File):
    """Quartus Text Design File"""
    pass


class GDFFile(File):
    """Quartus Graphic Design File"""
    pass


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class SignalTapFile(File):
    """This is the class providing the Altera Signal Tap Language file"""
    pass


ALTERA_FILE_DICT = {
    'stp': SignalTapFile,
    'qip': QIPFile,
    'qsys': QSYSFile,
    'dpf': DPFFile,
    'qsf': QSFFile,
    'bsf': BSFFile,
    'bdf': BDFFile,
    'tdf': TDFFile,
    'gdf': GDFFile}


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def create_source_file(path, module, library=None,
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                       include_dirs=None, is_include=False):
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    """Function that analyzes the given arguments and returns a new HDL source
    file of the appropriated type"""
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    assert path
    assert os.path.isabs(path)
    _, extension = os.path.splitext(path)
    assert extension[0] == '.'
    # Remove '.'
    extension = extension[1:]
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    logging.debug("add file " + path)

    if extension in ['vhd', 'vhdl', 'vho']:
        new_file = VHDLFile(path=path,
                            module=module,
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                            library=library)
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    elif extension in ['v', 'vh', 'vo', 'vm']:
        new_file = VerilogFile(path=path,
                               module=module,
                               library=library,
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                               include_dirs=include_dirs,
                               is_include=is_include)
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    elif extension == 'sv' or extension == 'svh':
        new_file = SVFile(path=path,
                          module=module,
                          library=library,
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                          include_dirs=include_dirs,
                          is_include=is_include)
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    elif extension == 'wb':
        new_file = WBGenFile(path=path, module=module)
    elif extension == 'tcl':
        new_file = TCLFile(path=path, module=module)
    elif extension == 'sdc':
        new_file = SDCFile(path=path, module=module)
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    elif extension in XILINX_FILE_DICT:
        new_file = XILINX_FILE_DICT[extension](path=path, module=module)
    elif extension in ALTERA_FILE_DICT:
        new_file = ALTERA_FILE_DICT[extension](path=path, module=module)
    elif extension in LATTICE_FILE_DICT:
        new_file = LATTICE_FILE_DICT[extension](path=path, module=module)
    elif extension in MICROSEMI_FILE_DICT:
        new_file = MICROSEMI_FILE_DICT[extension](path=path, module=module)
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    else:
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        raise Exception("Unknown extension '{}' for file {}".format(extension, path))
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    return new_file