From 2e614fcbcd5bdc83204dd7b1c133e0e5861e028d Mon Sep 17 00:00:00 2001
From: Pawel Szostek <pawel.szostek@cern.ch>
Date: Fri, 14 Jan 2011 12:42:50 +0000
Subject: [PATCH] Updated informations concerning synthesis in tex
---
VHDLSimSyn.tex | 2 ++
synthesis/xst_synthesis.sh | 44 +++++++++++++++++++-------------------
2 files changed, 24 insertions(+), 22 deletions(-)
diff --git a/VHDLSimSyn.tex b/VHDLSimSyn.tex
index e8f72f1f..f81fd966 100644
--- a/VHDLSimSyn.tex
+++ b/VHDLSimSyn.tex
@@ -151,6 +151,8 @@ When the make finishes the simulation is ready for browsing in Modelsim.
\section{Synthesis}
\subsection{Description of the problem}
Synthesis of large projects is a time and resource-consuming process. It makes the edit-compile-test cycle unreasonably long and makes harder to introduce petty modifications to the hardware. Apart from that much of system resources like memory or CPU time are consumed and synthesis makes running other application harder. The solution for this problem is to set up a dedicated server for synthesis purpose only. This allows to delegate this demanding task to a fast machine, while the developer's computer remains still useful.
+
+What is more, common synthesis server allows to unify synthesis projects. Usually, when developing a project in a team, all team members have different version of software tools. These tools are complex and their ersions are not always fully compatible with each other. When collaborating developers share the same machine for synthesis they can always be sure that the synthesis will run correctly.
\subsection{How does it work internally}
There are a few scripts that differ from each other depending on synthesis tool, that they are used with. Supported tools are:
\begin{itemize}
diff --git a/synthesis/xst_synthesis.sh b/synthesis/xst_synthesis.sh
index 09afd671..8d92e594 100755
--- a/synthesis/xst_synthesis.sh
+++ b/synthesis/xst_synthesis.sh
@@ -1,15 +1,25 @@
#!/bin/bash
########################################################################################
-# Variables for modification. If you believe that the script won't detect them
-#+ properly your project files then change appropriate variables.
-#+ Otherwise leave it as it is and the work be will done automatically
-
-declare xsvf_gen_file="" #file used for xsvf generation with impact
-declare mcs_gen_file="" #file used for mcs generation with impact
-declare xtclsh_file="" #files used for project implentation, automatically generated by
-declare ise_proj_file="" #.xise project file (main ISE project file)
-declare syn_proj_file="" #.prj file for synthesis with Synplify
+# Variables for modification.
+
+# data for logging in via ssh
+R_MACHINE="localhost"
+R_USER="pawel"
+ARCH_NAME="arch.tar"
+########################################################################################
+# The following variables are set automatically by the script.
+#+ If you believe that the script won't set them properly
+#+ then change appropriate variables.Otherwise leave it as it is.
+
+declare prj_file="" #.prj file is required by the xflow tool. It is to be generated with ISE.
+declare ise_proj_file="" #main ise project file. Its extension should be either .ise or .xise
+
+# The following line is intended to automatically detect the design name
+#+If it doesn't work replace it with the actual name
+design_name=$(ls | grep -e '^.*\.xise' | sed -e 's/\(.*\)\.xise/\1/g')
+
+SYNTHESIS_COMMAND="xflow -p xc6slx150t-2-fgg676 -implement balanced -config bitgen $design_name"
########################################################################################
# DO NOT MODIFY BELOW THIS POINT -> .
########################################################################################
@@ -59,10 +69,6 @@ SYNPLIFY=""
XTCLSH=""
IMPACT=""
-#data for logging in via ssh
-R_MACHINE="localhost"
-R_USER="pawel"
-ARCH_NAME="arch.tar"
proj_path=$(abs_path $(pwd))
proj_path=${proj_path%/}
@@ -85,8 +91,8 @@ ise_proj_file=$(abs_path $ise_proj_file)
#check if the variable was specified by the user
if [ "x$syn_proj_file" = "x" ]; then
- syn_proj_file=$(ls $proj_path | grep -e '.*\.prj$')
- if [ $(echo $syn_proj_file | wc -w) -ne 1 ]; then
+ prj_file=$(ls $proj_path | grep -e '.*\.prj$')
+ if [ $(echo $prj_file | wc -w) -ne 1 ]; then
cat <<-EOH
Inpropriate number of Synplify project files
Project file (.prj) must be passed
@@ -141,13 +147,7 @@ message "Transferring vhdl files, project files and scripts to remote machine...
tar -cvjf - $transfered_files | ssh $R_USER@$R_MACHINE "(cd $randstring; tar xjf -)" &&
message "Running synthesis and fitting on $R_MACHINE..." &&
-ssh $R_USER@$R_MACHINE "
- cd $randstring$(pwd); export TERM=linux;
- $SYNPLIFY -batch $syn_proj_file &&
- $XTCLSH $xtclsh rebuild_project
- $IMPACT -batch $mcs_gen_file
- $IMPACT -batch $xsvf_gen_file
-" &&
+ssh $R_USER@$R_MACHINE $SYNTHESIS_COMMAND &&
#check for new files, put them in an archive and transfer back
message "Creating list of files that should be copied back..." &&
--
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