@@ -956,7 +956,7 @@ IP cores may accelerate your design at the first stages and synthesize at much h
\subsubsection{Registering of Core's External I/Os}
All core's external I/Os should be registered. It prevents long timing paths and allows you to meet timing constraints easier. It also allows easier verification of the entire SoC. Tri-State I/Os output enable line should also be registered.
All core I/Os should be registered, whether they are FPGA I/Os or connect to other internal FPGA resources. It prevents long timing paths and allows you to meet timing constraints easier. It also allows easier verification of the entire SoC. Tri-State I/Os output enable line should also be registered.