btrain-v1.2   Release v1.2 of BTrain-over-WhiteRabbit https://gitlab.cern.ch/BTrain-TEAM/Btrain-over-WhiteRabbit/wikis/home

btrain-v2.5   This version of gn4124-core is used by BTrain-ELENA v2.5

revision-beta

v1.0 protected   GN4124 Core Release v1.0

v1.0.0 protected

v2.0 protected   GN4124 Core Release v2.0

v2.0.0 protected

v3.0.0 protected   3.0.0 - 2020-07-27 ================== https://www.ohwr.org/project/gn4124-core/tree/v3.0.0 Added ----- - hdl: SystemVerilog BFM and testbench. - hdl: Add wrapper with wishbone records and slave adapters. - hdl: Add generics to tune the depths of the various async FIFOs. Changed ------- - hdl: Major rewrite of DMA engine, in particular the L2P DMA Master. - hdl: Major cleanup of resets and cross-clock domain synchronisation. - hdl: Stop using coregen FIFOs, switch to FIFOs from general-cores. - hdl: Make DMA optional (g_WITH_DMA generic). - hdl: Use cheby to describe registers, only one interrupt (level). - hdl: Test, verify and enable byte swap feature. - hdl: Extend SV BFM with tasks to read/write from simulated host memory. Fixed ----- - hdl: Fixed incorrect 64-bit DMA transaction generation bug. - hdl: Allow larger DMA reads (up to the full 32 bits of the "length" register) for L2P DMA master. - hdl: Add flow control to the write buffer of the BFM to prevent overflows during 'wr' commands. - hdl: Fix swapped bits in attributes. - hdl: Handle host 32-bit address overflow in L2P DMA master. - hdl: Fix bug in BFM not respecting P2L_RDY during DMA writes. - hdl: Fix bug in BFM not accepting 4096B writes.

v3.0.1 protected   3.0.1 - 2020-09-29 ================== https://www.ohwr.org/project/gn4124-core/tree/v3.0.1 Fixed ----- - hdl: L2P DMA issues reported with slower hosts

v3.1.0 protected   Version 3.1.0

v3.1.1 protected   Release v3.1.1