3.0.0 - 2020-07-27

- hdl: SystemVerilog BFM and testbench.
- hdl: Add wrapper with wishbone records and slave adapters.
- hdl: Add generics to tune the depths of the various async FIFOs.

- hdl: Major rewrite of DMA engine, in particular the L2P DMA Master.
- hdl: Major cleanup of resets and cross-clock domain synchronisation.
- hdl: Stop using coregen FIFOs, switch to FIFOs from general-cores.
- hdl: Make DMA optional (g_WITH_DMA generic).
- hdl: Use cheby to describe registers, only one interrupt (level).
- hdl: Test, verify and enable byte swap feature.
- hdl: Extend SV BFM with tasks to read/write from simulated host memory.

- hdl: Fixed incorrect 64-bit DMA transaction generation bug.
- hdl: Allow larger DMA reads (up to the full 32 bits of the "length" register) for L2P DMA master.
- hdl: Add flow control to the write buffer of the BFM to prevent overflows during 'wr' commands.
- hdl: Fix swapped bits in attributes.
- hdl: Handle host 32-bit address overflow in L2P DMA master.
- hdl: Fix bug in BFM not respecting P2L_RDY during DMA writes.
- hdl: Fix bug in BFM not accepting 4096B writes.
This tag has no release notes.