Commit 72e138ad authored by Dimitris Lampridis's avatar Dimitris Lampridis

hdl: Fix size and threshold of L2P DMA FIFO

The FIFO size and full threshold need to be enough to hold if necessary all the pending read data
requests from the WB slave.

In the case of the Spartan-6 DDR controller being the WB slave, the FIFO needs to be able to store
up to 192 words (128 from the controller itself, plus 64 from our wrapper).

Since the GN4124 is used primarily on the SPEC, this is now the default value for the L2P DMA
master.
Signed-off-by: Dimitris Lampridis's avatarDimitris Lampridis <dimitris.lampridis@cern.ch>
parent 593be77a
......@@ -34,8 +34,13 @@ use work.genram_pkg.all;
entity l2p_dma_master is
generic (
g_FIFO_SIZE : positive := 128;
g_BYTE_SWAP : boolean := FALSE);
-- It is important to set this threshold such that the FIFO has room to store
-- all pending read requests from the pipelined wishbone interface in case
-- the Gennum decides to stall and the FIFO starts filling up. The default
-- value is correct if the WB slave is the Spartan-6 DDR controller.
g_FIFO_FULL_THRES : positive := 64;
g_FIFO_SIZE : positive := 256;
g_BYTE_SWAP : boolean := FALSE);
port (
-- GN4124 core clk and reset
clk_i : in std_logic;
......@@ -525,7 +530,7 @@ begin
g_SHOW_AHEAD => TRUE,
g_WITH_WR_FULL => FALSE,
g_WITH_WR_ALMOST_FULL => TRUE,
g_ALMOST_FULL_THRESHOLD => g_FIFO_SIZE/2 - c_SYNC_FIFO_FULL_DELAY)
g_ALMOST_FULL_THRESHOLD => g_FIFO_FULL_THRES - c_SYNC_FIFO_FULL_DELAY)
port map (
-- write port
rst_wr_n_i => data_fifo_rst_wr_n,
......
......@@ -48,7 +48,8 @@ entity gn4124_core is
g_WBM_FROM_WB_FIFO_SIZE : positive := 128;
g_WBM_FROM_WB_FIFO_FULL_THRES : positive := 110;
g_P2L_FIFO_SIZE : positive := 64;
g_L2P_FIFO_SIZE : positive := 128;
g_L2P_FIFO_SIZE : positive := 256;
g_L2P_FIFO_FULL_THRES : positive := 64;
-- Wishbone ACK timeout (in wishbone clock cycles)
g_ACK_TIMEOUT : positive := 100);
port (
......@@ -569,8 +570,9 @@ begin
-----------------------------------------------------------------------------
cmp_l2p_dma_master : entity work.l2p_dma_master
generic map (
g_FIFO_SIZE => g_L2P_FIFO_SIZE,
g_BYTE_SWAP => TRUE)
g_FIFO_FULL_THRES => g_L2P_FIFO_FULL_THRES,
g_FIFO_SIZE => g_L2P_FIFO_SIZE,
g_BYTE_SWAP => TRUE)
port map (
clk_i => sys_clk,
rst_n_i => sys_rst_n,
......
......@@ -61,7 +61,8 @@ package gn4124_core_pkg is
g_WBM_FROM_WB_FIFO_SIZE : positive := 128;
g_WBM_FROM_WB_FIFO_FULL_THRES : positive := 110;
g_P2L_FIFO_SIZE : positive := 64;
g_L2P_FIFO_SIZE : positive := 128;
g_L2P_FIFO_SIZE : positive := 256;
g_L2P_FIFO_FULL_THRES : positive := 64;
g_WB_MASTER_MODE : t_wishbone_interface_mode := PIPELINED;
g_WB_MASTER_GRANULARITY : t_wishbone_address_granularity := BYTE;
g_WB_DMA_CFG_MODE : t_wishbone_interface_mode := PIPELINED;
......@@ -118,7 +119,8 @@ package gn4124_core_pkg is
g_WBM_FROM_WB_FIFO_SIZE : positive := 128;
g_WBM_FROM_WB_FIFO_FULL_THRES : positive := 110;
g_P2L_FIFO_SIZE : positive := 64;
g_L2P_FIFO_SIZE : positive := 128;
g_L2P_FIFO_SIZE : positive := 256;
g_L2P_FIFO_FULL_THRES : positive := 64;
g_ACK_TIMEOUT : positive := 100);
port (
---------------------------------------------------------
......
......@@ -41,7 +41,8 @@ entity xwb_gn4124_core is
g_WBM_FROM_WB_FIFO_SIZE : positive := 128;
g_WBM_FROM_WB_FIFO_FULL_THRES : positive := 110;
g_P2L_FIFO_SIZE : positive := 64;
g_L2P_FIFO_SIZE : positive := 128;
g_L2P_FIFO_SIZE : positive := 256;
g_L2P_FIFO_FULL_THRES : positive := 64;
-- WB config for three WB interfaces
g_WB_MASTER_MODE : t_wishbone_interface_mode := PIPELINED;
g_WB_MASTER_GRANULARITY : t_wishbone_address_granularity := BYTE;
......@@ -193,6 +194,7 @@ begin
g_WBM_FROM_WB_FIFO_FULL_THRES => g_WBM_FROM_WB_FIFO_FULL_THRES,
g_P2L_FIFO_SIZE => g_P2L_FIFO_SIZE,
g_L2P_FIFO_SIZE => g_L2P_FIFO_SIZE,
g_L2P_FIFO_FULL_THRES => g_L2P_FIFO_FULL_THRES,
g_ACK_TIMEOUT => g_ACK_TIMEOUT)
port map (
rst_n_a_i => rst_n_a_i,
......
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