Relax timing pressure on dma_ctrl_direction

461b30fe · Tristan Gingold · c6293643 · 461b30fe · 461b30fe
Commit 461b30fe authored Nov 13, 2020 by Tristan Gingold
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Showing with 12 additions and 2 deletions

dma_controller.vhd hdl/rtl/dma_controller.vhd +2 -0

gn4124_core.vhd hdl/rtl/spartan6/gn4124_core.vhd +10 -2

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--- a/hdl/rtl/dma_controller.vhd
+++ b/hdl/rtl/dma_controller.vhd
@@ -291,6 +291,8 @@ begin
              dma_attrib_chain_reg   <= dma_async_attrib_chain;
              dma_attrib_dir_reg     <= dma_async_attrib_dir;
              dma_ctrl_byte_swap_reg <= dma_ctrl_byte_swap;
+              -- Set it early to ease timing.
+              dma_ctrl_direction_o   <= dma_async_attrib_dir;
              -- Starts a new transfer
              dma_ctrl_current_state <= DMA_START_TRANSFER;
            end if;

--- a/hdl/rtl/spartan6/gn4124_core.vhd
+++ b/hdl/rtl/spartan6/gn4124_core.vhd
@@ -255,6 +255,7 @@ architecture rtl of gn4124_core is
  signal dma_ctrl_start_p2l    : std_logic;
  signal dma_ctrl_start_next   : std_logic;
  signal dma_ctrl_direction    : std_logic;
+  signal dma_ctrl_direction_d  : std_logic;

  signal dma_ctrl_done      : std_logic;
  signal dma_ctrl_error     : std_logic;
@@ -669,10 +670,17 @@ begin
    p2l_dma_in.rty   <= dma_rty_i;

    -- NOTE: dma_ctrl_direction crosses clock domains.
-    p_dma_wb_mux : process (dma_ack_i, dma_ctrl_direction, dma_stall_i,
+    process (dma_clk_i)
+    begin
+      if rising_edge(dma_clk_i) then
+        dma_ctrl_direction_d <= dma_ctrl_direction;
+      end if;
+    end process;
+
+    p_dma_wb_mux : process (dma_ack_i, dma_ctrl_direction_d, dma_stall_i,
                            l2p_dma_out, p2l_dma_out)
    begin
-      if (dma_ctrl_direction = '0') then
+      if dma_ctrl_direction_d = '0' then
        dma_adr_o        <= l2p_dma_out.adr;
        dma_dat_o        <= l2p_dma_out.dat;
        dma_sel_o        <= l2p_dma_out.sel;