# ------------------------------------------------------------------------------
#  CERN BE-CO-HT
#  GN4124 core for PCIe FMC carrier
#  http://www.ohwr.org/projects/gn4124-core
# ------------------------------------------------------------------------------
#
#  unit name:   dma_controller_regs
#
#  description: GN4124 core DMA controller registers block layout
#
# ------------------------------------------------------------------------------
#  Copyright CERN 2010-2019
# ------------------------------------------------------------------------------
#  Copyright and related rights are licensed under the Solderpad Hardware
#  License, Version 2.0 (the "License"); you may not use this file except
#  in compliance with the License. You may obtain a copy of the License at
#  http://solderpad.org/licenses/SHL-2.0.
#  Unless required by applicable law or agreed to in writing, software,
#  hardware and materials distributed under this License is distributed on an
#  "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
#  or implied. See the License for the specific language governing permissions
#  and limitations under the License.
# ------------------------------------------------------------------------------
memory-map:
  bus: wb-32-be
  name: dma_controller_regs
  description: "GN4124 core DMA controller"
  comment: Wishbone slave for the DMA controller of the GN4124 core
  children:
  - reg:
      name: ctrl
      address: 0x00000000
      width: 32
      access: rw
      description: DMACTRLR
      children:
      - field:
         name: start
         range: 0
         comment: Start DMA transfer
         description: Write '1' to start a DMA transfer
         x-hdl:
           type: wire
      - field:
         name: abort
         range: 1
         comment: Abort current DMA transfer
         description: Write '1' to abort the DMA transfer
         x-hdl:
           type: wire
      - field:
         name: byteswap
         range: 3-2
         description: Control byte-swapping
      x-hdl:
        write-strobe: True
        write-ack: True
  - reg:
      name: stat
      address: 0x00000004
      width: 32
      access: rw
      description: DMASTATR
      children:
      - field:
         name: status
         comment: DMA state
         description: |
           DMA state:
           00: idle
           01: busy
           10: error
           11: abort
         range: 1-0
         x-hdl:
           type: wire
      - field:
         name: irq
         comment: IRQ status, write 1 to clear
         range: 2
         x-hdl:
           type: wire
      x-hdl:
        write-strobe: True
        write-ack: True
        read-strobe: True
        read-ack: True
  - reg:
      name: cstart
      address: 0x00000008
      width: 32
      access: rw
      comment: DMACSTARTR
      description: Carrier start address
  - reg:
      name: hstartl
      address: 0x0000000c
      width: 32
      access: rw
      comment: DMAHSTARTLR
      description: DMA start address (low) in the host
  - reg:
      name: hstarth
      address: 0x00000010
      width: 32
      access: rw
      comment: DMAHSTARTHR
      description: DMA start address (high) in the host
  - reg:
      name: len
      address: 0x00000014
      width: 32
      access: rw
      comment: DMALENR
      description: DMA read length in bytes
  - reg:
      name: nextl
      address: 0x00000018
      width: 32
      access: rw
      comment: DMANEXTLR
      description: Pointer (low) to next item in list
  - reg:
      name: nexth
      address: 0x0000001c
      width: 32
      access: rw
      comment: DMANEXTHR
      description: Pointer (high) to next item in list
  - reg:
      name: attrib
      address: 0x00000020
      width: 32
      access: rw
      comment: DMAATTRIBR
      description: DMA chain control
      children:
      - field:
         name: chain
         comment: Transfer chain (if 1)
         range: 1
      - field:
         name: dir
         comment: "Transfer direction (0: to host, 1: to carrier)"
         range: 0