diff --git a/hdl/gullwing/chipscope/cs_core.cdc b/hdl/gullwing/chipscope/cs_core.cdc
deleted file mode 100644
index ca1a18855f03cbcc8efcaeccedecdc961b267d87..0000000000000000000000000000000000000000
--- a/hdl/gullwing/chipscope/cs_core.cdc
+++ /dev/null
@@ -1,393 +0,0 @@
-#ChipScope Core Inserter Project File Version 3.0
-#Thu Nov 04 10:12:17 CET 2010
-Project.device.designInputFile=/home/mcattin/projects/GN4124_core/hdl/gn4124core/gw_wrapper_cs.ngc
-Project.device.designOutputFile=/home/mcattin/projects/GN4124_core/hdl/gn4124core/gw_wrapper_cs.ngc
-Project.device.deviceFamily=15
-Project.device.enableRPMs=true
-Project.device.outputDirectory=/home/mcattin/projects/GN4124_core/hdl/gn4124core/_ngo
-Project.device.useSRL16=true
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-Project.unit<0>.dataChannel<31>=cmp_gn4124_core/cmp_p2l_des/p2l_data_o<31>
-Project.unit<0>.dataChannel<32>=cmp_gn4124_core/cmp_p2l_des/p2l_dframe_o
-Project.unit<0>.dataChannel<33>=cmp_gn4124_core/cmp_p2l_des/p2l_valid_o
-Project.unit<0>.dataChannel<34>=cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<0>
-Project.unit<0>.dataChannel<35>=cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<1>
-Project.unit<0>.dataChannel<36>=cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<2>
-Project.unit<0>.dataChannel<37>=cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<3>
-Project.unit<0>.dataChannel<38>=cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<4>
-Project.unit<0>.dataChannel<39>=cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<5>
-Project.unit<0>.dataChannel<3>=cmp_gn4124_core/cmp_p2l_des/p2l_data_o<3>
-Project.unit<0>.dataChannel<40>=cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<6>
-Project.unit<0>.dataChannel<41>=cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<7>
-Project.unit<0>.dataChannel<42>=cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<8>
-Project.unit<0>.dataChannel<43>=cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<9>
-Project.unit<0>.dataChannel<44>=cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<10>
-Project.unit<0>.dataChannel<45>=cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<11>
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-Project.unit<0>.dataChannel<81>=cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din<1>
-Project.unit<0>.dataChannel<82>=cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din<10>
-Project.unit<0>.dataChannel<83>=cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din<11>
-Project.unit<0>.dataChannel<84>=cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din<12>
-Project.unit<0>.dataChannel<85>=cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din<13>
-Project.unit<0>.dataChannel<86>=cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din<14>
-Project.unit<0>.dataChannel<87>=cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din<15>
-Project.unit<0>.dataChannel<88>=cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din<16>
-Project.unit<0>.dataChannel<89>=cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din<17>
-Project.unit<0>.dataChannel<8>=cmp_gn4124_core/cmp_p2l_des/p2l_data_o<8>
-Project.unit<0>.dataChannel<90>=cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din<18>
-Project.unit<0>.dataChannel<91>=cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din<19>
-Project.unit<0>.dataChannel<92>=cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din<2>
-Project.unit<0>.dataChannel<93>=cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din<20>
-Project.unit<0>.dataChannel<94>=cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din<21>
-Project.unit<0>.dataChannel<95>=cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din<22>
-Project.unit<0>.dataChannel<96>=cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din<23>
-Project.unit<0>.dataChannel<97>=cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din<24>
-Project.unit<0>.dataChannel<98>=cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din<25>
-Project.unit<0>.dataChannel<99>=cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din<26>
-Project.unit<0>.dataChannel<9>=cmp_gn4124_core/cmp_p2l_des/p2l_data_o<9>
-Project.unit<0>.dataDepth=1024
-Project.unit<0>.dataEqualsTrigger=false
-Project.unit<0>.dataPortWidth=256
-Project.unit<0>.enableGaps=false
-Project.unit<0>.enableStorageQualification=true
-Project.unit<0>.enableTimestamps=false
-Project.unit<0>.timestampDepth=0
-Project.unit<0>.timestampWidth=0
-Project.unit<0>.triggerChannel<0><0>=cmp_gn4124_core/cmp_p2l_des/p2l_dframe_o
-Project.unit<0>.triggerChannel<0><10>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_data_cnt<1>
-Project.unit<0>.triggerChannel<0><11>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_data_cnt<2>
-Project.unit<0>.triggerChannel<0><12>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_data_cnt<3>
-Project.unit<0>.triggerChannel<0><13>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_data_cnt<4>
-Project.unit<0>.triggerChannel<0><14>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_data_cnt<5>
-Project.unit<0>.triggerChannel<0><15>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_data_cnt<6>
-Project.unit<0>.triggerChannel<0><16>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_data_cnt<7>
-Project.unit<0>.triggerChannel<0><17>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_data_cnt<8>
-Project.unit<0>.triggerChannel<0><18>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_data_cnt<9>
-Project.unit<0>.triggerChannel<0><19>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_data_cnt<10>
-Project.unit<0>.triggerChannel<0><1>=cmp_gn4124_core/cmp_p2l_des/p2l_valid_o
-Project.unit<0>.triggerChannel<0><2>=cmp_gn4124_core/cmp_dma_controller/dma_error_irq
-Project.unit<0>.triggerChannel<0><3>=cmp_gn4124_core/cmp_l2p_dma_master/dma_ctrl_error_o
-Project.unit<0>.triggerChannel<0><4>=cmp_gn4124_core/cmp_p2l_dma_master/completion_error
-Project.unit<0>.triggerChannel<0><5>=cmp_gn4124_core/cmp_p2l_dma_master/dma_busy_error
-Project.unit<0>.triggerChannel<0><6>=cmp_gn4124_core/cmp_p2l_dma_master/rx_error_o
-Project.unit<0>.triggerChannel<0><7>=cmp_gn4124_core/cmp_dma_controller/dma_done_irq
-Project.unit<0>.triggerChannel<0><8>=irq_to_gn4124
-Project.unit<0>.triggerChannel<0><9>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_data_cnt<0>
-Project.unit<0>.triggerChannel<1><0>=cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_valid_o
-Project.unit<0>.triggerChannel<1><10>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt<4>
-Project.unit<0>.triggerChannel<1><11>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt<5>
-Project.unit<0>.triggerChannel<1><12>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt<6>
-Project.unit<0>.triggerChannel<1><13>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt<7>
-Project.unit<0>.triggerChannel<1><14>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt<8>
-Project.unit<0>.triggerChannel<1><15>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt<9>
-Project.unit<0>.triggerChannel<1><16>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt<10>
-Project.unit<0>.triggerChannel<1><17>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt<11>
-Project.unit<0>.triggerChannel<1><18>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt<12>
-Project.unit<0>.triggerChannel<1><19>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt<13>
-Project.unit<0>.triggerChannel<1><1>=cmp_gn4124_core/cmp_p2l_dma_master/pdm_arb_valid_o
-Project.unit<0>.triggerChannel<1><20>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt<14>
-Project.unit<0>.triggerChannel<1><21>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt<15>
-Project.unit<0>.triggerChannel<1><22>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt<16>
-Project.unit<0>.triggerChannel<1><23>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt<17>
-Project.unit<0>.triggerChannel<1><24>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt<18>
-Project.unit<0>.triggerChannel<1><25>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt<19>
-Project.unit<0>.triggerChannel<1><26>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt<20>
-Project.unit<0>.triggerChannel<1><27>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt<21>
-Project.unit<0>.triggerChannel<1><28>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt<22>
-Project.unit<0>.triggerChannel<1><29>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt<23>
-Project.unit<0>.triggerChannel<1><2>=cmp_gn4124_core/cmp_wbmaster32/wbm_arb_valid_o
-Project.unit<0>.triggerChannel<1><30>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt<24>
-Project.unit<0>.triggerChannel<1><31>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt<25>
-Project.unit<0>.triggerChannel<1><32>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt<26>
-Project.unit<0>.triggerChannel<1><33>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt<27>
-Project.unit<0>.triggerChannel<1><34>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt<28>
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diff --git a/hdl/gullwing/gullwing.ucf b/hdl/gullwing/gullwing.ucf
deleted file mode 100644
index ae41e4cc3d743fc3fd9db9883d7297f30eeb2779..0000000000000000000000000000000000000000
--- a/hdl/gullwing/gullwing.ucf
+++ /dev/null
@@ -1,559 +0,0 @@
-
-#---------------------------------------------------------------------------------------------
-# IO standards 
-#---------------------------------------------------------------------------------------------
-NET "l2p_data[0]"  IOSTANDARD = SSTL18_I;
-NET "l2p_data[10]" IOSTANDARD = SSTL18_I;
-NET "l2p_data[11]" IOSTANDARD = SSTL18_I;
-NET "l2p_data[12]" IOSTANDARD = SSTL18_I;
-NET "l2p_data[13]" IOSTANDARD = SSTL18_I;
-NET "l2p_data[14]" IOSTANDARD = SSTL18_I;
-NET "l2p_data[15]" IOSTANDARD = SSTL18_I;
-NET "l2p_data[1]"  IOSTANDARD = SSTL18_I;
-NET "l2p_data[2]"  IOSTANDARD = SSTL18_I;
-NET "l2p_data[3]"  IOSTANDARD = SSTL18_I;
-NET "l2p_data[4]"  IOSTANDARD = SSTL18_I;
-NET "l2p_data[5]"  IOSTANDARD = SSTL18_I;
-NET "l2p_data[6]"  IOSTANDARD = SSTL18_I;
-NET "l2p_data[7]"  IOSTANDARD = SSTL18_I;
-NET "l2p_data[8]"  IOSTANDARD = SSTL18_I;
-NET "l2p_data[9]"  IOSTANDARD = SSTL18_I;
-NET "l2p_clkp"     IOSTANDARD = DIFF_SSTL18_I;
-NET "l2p_clkn"     IOSTANDARD = DIFF_SSTL18_I;
-NET "l2p_rdy"      IOSTANDARD = SSTL18_I;
-NET "l_clkn"       IOSTANDARD = DIFF_SSTL18_I; #SSTL18_I;
-NET "l_clkp"       IOSTANDARD = DIFF_SSTL18_I; #SSTL18_I;
-NET "l_rst_n"      IOSTANDARD = SSTL18_I;
-NET "p2l_clkp"     IOSTANDARD = DIFF_SSTL18_I;
-NET "p2l_clkn"     IOSTANDARD = DIFF_SSTL18_I;
-NET "p2l_data[0]"  IOSTANDARD = SSTL18_I;
-NET "p2l_data[10]" IOSTANDARD = SSTL18_I;
-NET "p2l_data[11]" IOSTANDARD = SSTL18_I;
-NET "p2l_data[12]" IOSTANDARD = SSTL18_I;
-NET "p2l_data[13]" IOSTANDARD = SSTL18_I;
-NET "p2l_data[14]" IOSTANDARD = SSTL18_I;
-NET "p2l_data[15]" IOSTANDARD = SSTL18_I;
-NET "p2l_data[1]"  IOSTANDARD = SSTL18_I;
-NET "p2l_data[2]"  IOSTANDARD = SSTL18_I;
-NET "p2l_data[3]"  IOSTANDARD = SSTL18_I;
-NET "p2l_data[4]"  IOSTANDARD = SSTL18_I;
-NET "p2l_data[5]"  IOSTANDARD = SSTL18_I;
-NET "p2l_data[6]"  IOSTANDARD = SSTL18_I;
-NET "p2l_data[7]"  IOSTANDARD = SSTL18_I;
-NET "p2l_data[8]"  IOSTANDARD = SSTL18_I;
-NET "p2l_data[9]"  IOSTANDARD = SSTL18_I;
-NET "p2l_rdy"      IOSTANDARD = SSTL18_I;
-NET "l_wr_rdy[0]"    IOSTANDARD = SSTL18_I;
-NET "l_wr_rdy[1]"    IOSTANDARD = SSTL18_I;
-NET "p_rd_d_rdy[0]"  IOSTANDARD = SSTL18_I;
-NET "p_rd_d_rdy[1]"  IOSTANDARD = SSTL18_I;
-NET "l2p_dframe"   IOSTANDARD = SSTL18_I;
-NET "l2p_valid"    IOSTANDARD = SSTL18_I;
-NET "l2p_edb"      IOSTANDARD = SSTL18_I;
-NET "p2l_dframe"   IOSTANDARD = SSTL18_I;
-NET "p2l_valid"    IOSTANDARD = SSTL18_I;
-NET "p_wr_rdy[0]"    IOSTANDARD = SSTL18_I;
-NET "p_wr_rdy[1]"    IOSTANDARD = SSTL18_I;
-NET "rx_error"     IOSTANDARD = SSTL18_I;
-NET "tx_error"     IOSTANDARD = SSTL18_I;
-NET "vc_rdy[0]"    IOSTANDARD = SSTL18_I;
-NET "vc_rdy[1]"    IOSTANDARD = SSTL18_I;
-NET "p_wr_req[0]" IOSTANDARD = SSTL18_I;
-NET "p_wr_req[1]" IOSTANDARD = SSTL18_I;
-
-NET "l_rst33_n"    IOSTANDARD = "LVCMOS33";
-
-## GN1559 de-serializer
-NET "des[*]"   IOSTANDARD = "LVCMOS33";
-NET "des_pclk" IOSTANDARD = "LVCMOS33";
-
-## GN1531 serializer
-NET "ser[*]"    IOSTANDARD = "LVCMOS33";
-
-## GN1559 related
-NET "des_h" IOSTANDARD = "LVCMOS33";
-NET "des_v" IOSTANDARD = "LVCMOS33";
-NET "des_f" IOSTANDARD = "LVCMOS33";
-NET "des_smpte_bypass" IOSTANDARD = "LVCMOS33";
-NET "des_dvb_asi" IOSTANDARD = "LVCMOS33";
-NET "des_sdhdn" IOSTANDARD = "LVCMOS33";
-
-## GN1531 related
-NET "ser_h" IOSTANDARD = "LVCMOS33";
-NET "ser_v" IOSTANDARD = "LVCMOS33";
-NET "ser_f" IOSTANDARD = "LVCMOS33";
-NET "ser_smpte_bypass" IOSTANDARD = "LVCMOS33";
-NET "ser_dvb_asi" IOSTANDARD = "LVCMOS33";
-NET "ser_sdhdn" IOSTANDARD = "LVCMOS33";
-
-
-## GN4911 Timing Generator
-NET "syncseperator_h_timing" IOSTANDARD = "LVCMOS33";
-NET "syncseperator_v_timing" IOSTANDARD = "LVCMOS33";
-NET "syncseperator_f_timing" IOSTANDARD = "LVCMOS33";
-
-# GPIO
-NET "gpio[*]" IOSTANDARD = "LVCMOS33";
-
-# I2C
-NET "sda" IOSTANDARD = "LVCMOS33";
-NET "scl" IOSTANDARD = "LVCMOS33";
-
-# MICTOR connector
-NET "mic_clka" IOSTANDARD = "LVCMOS33";
-NET "mic_clkb" IOSTANDARD = "LVCMOS33";
-
-NET "mic_data[*]" IOSTANDARD = "LVCMOS33";
-
-# debug input switches
-NET "debug[*]" IOSTANDARD = "LVCMOS33";
-NET "led[*]"   IOSTANDARD = "LVCMOS33";
-
-NET "spi_sck" IOSTANDARD = "LVCMOS33";
-NET "spi_ss[*]"   IOSTANDARD = "LVCMOS33";
-NET "spi_mosi" IOSTANDARD = "LVCMOS33";
-NET "spi_miso" IOSTANDARD = "LVCMOS33";
-   
-NET "gs4911_host_b" IOSTANDARD = "LVCMOS33";
-NET "gs4911_sclk" IOSTANDARD = "LVCMOS33";
-NET "gs4911_sdin" IOSTANDARD = "LVCMOS33";
-NET "gs4911_sdout" IOSTANDARD = "LVCMOS33";
-NET "gs4911_csb" IOSTANDARD = "LVCMOS33";
-NET "PCLK_4911_1531" IOSTANDARD = "LVCMOS33";
-NET "GS4911_LOCK_LOST" IOSTANDARD = "LVCMOS33";
-NET "GS4911_REF_LOST"  IOSTANDARD = "LVCMOS33";
-
-#---------------------------------------------------------------------------------------------
-# Force DDR Flops into IOBs 
-# Offset constraints shoudl force this although the input and output DDR primtives are 
-# instantiated within the RTL.
-#---------------------------------------------------------------------------------------------
-#INST "lp2_data<*>" IOB=TRUE;  
-#INST "l2p_dframe" IOB=TRUE;
-#INST "l2p_valid"  IOB=TRUE;
-#INST "l2p_edb"    IOB=TRUE;
-#
-#---------------------------------------------------------------------------------------------
-# Constrain DDR inputs
-# Assume offset requirement of 6.25 on inputs for a 10ns clock
-#---------------------------------------------------------------------------------------------
-# Group the I/O  pads -- 0 degree clock 
-
-# Create a PERIOD constraint on the original clock
-NET "P2L_CLKp" TNM_NET = "p2l_clkp_grp";
-#### mcattin ####
-#TIMESPEC TS_p2l_clkp = PERIOD "p2l_clkp_grp" 4.8 ns HIGH 50%;   
-TIMESPEC TS_p2l_clkp = PERIOD "p2l_clkp_grp" 5 ns HIGH 50%;
-NET "P2L_CLKn" TNM_NET = "p2l_clkn_grp";
-#### mcattin ####
-#TIMESPEC TS_p2l_clkn = PERIOD "p2l_clkn_grp" 4.8 ns HIGH 50%; 
-TIMESPEC TS_p2l_clkn = PERIOD "p2l_clkn_grp" 5 ns HIGH 50%; 
-
-NET "P2L_CLKp" IBUF_DELAY_VALUE= 0;
-NET "P2L_CLKn" IBUF_DELAY_VALUE= 0;
-
-# Create an OFFSET constraint for the ddr group
-NET "p2l_data*" IFD_DELAY_VALUE = 2;  # Option: 0-8 or AUTO(does not work) 
-net "p2l_data*" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE "P2L_CLKp" high;
-net "p2l_data*" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE "P2L_CLKn" high;
-
-#---------------------------------------------------------------------------------------------
-# Constrain DDR outputs
-# Assume offset requirement of 7.5 on outputs for a 10ns clock period
-#---------------------------------------------------------------------------------------------
-
-# Create an OFFSET constraint for the ddr group
-# There is a minimum delay of ~3.2ns from the DDRDFF to the pad!!!!
-NET "l2p_data*" OFFSET = OUT 6.5 ns AFTER "P2L_CLKp" high;
-NET "l2p_data*" OFFSET = OUT 6.5 ns AFTER "P2L_CLKn" high;
-
-#---------------------------------------------------------------------------------------------
-# Constrain the other inputs
-#---------------------------------------------------------------------------------------------
-NET "p2l_dframe" IFD_DELAY_VALUE = 1;  # 0-8 or AUTO
-NET "p2l_dframe"  OFFSET = IN 1.2 ns VALID 3.0 ns BEFORE "P2L_CLKp" HIGH; ##1.5 ns VALID 2.0 ns
-NET "p2l_valid" IFD_DELAY_VALUE = 1;
-NET "p2l_valid"   OFFSET = IN 1.2 ns VALID 3.0 ns BEFORE "P2L_CLKp" HIGH; ##1.5 ns VALID 2.0 ns
-
-
-NET "vc_rdy*" maxdelay = 2 ns;
-NET "l_wr_rdy*" maxdelay = 2 ns;
-NET "p_rd_d_rdy[*]" maxdelay = 2 ns;
-NET "l2p_rdy" maxdelay = 2 ns;
-
-#---------------------------------------------------------------------------------------------
-# Constrain the other outputs
-#---------------------------------------------------------------------------------------------
-NET "l2p_dframe"   OFFSET = OUT 6.5 ns AFTER "P2L_CLKn" HIGH;
-NET "l2p_valid"    OFFSET = OUT 6.5 ns AFTER "P2L_CLKn" HIGH;
-NET "l2p_clkp"     OFFSET = OUT 6.5 ns AFTER "P2L_CLKp" HIGH;
-NET "l2p_clkn"     OFFSET = OUT 6.5 ns AFTER "P2L_CLKn" HIGH;
-
-#---------------------------------------------------------------------------------------------
-# False Path from Aysnchronous reset
-#---------------------------------------------------------------------------------------------
-NET "l_rst_n" TIG;
-##### mcattin #####
-#NET "cmp_gn4124_core/cmp_p2l_des/irst*" TIG;
-##### mcattin #####
-NET "cmp_gn4124_core/rst_*" TIG;
-
-#---------------------------------------------------------------------------------------------
-# False Path from write pointer as it is multi cycle
-#---------------------------------------------------------------------------------------------
-
-#---------------------------------------------------------------------------------------------
-# False Path from all lgogic clocked by l_clk_fpga in tx_fifo to logic clocked by l2p_0_clk
-#---------------------------------------------------------------------------------------------
-
-
-#---------------------------------------------------------------------------------------------
-# DCM placement constraints
-#---------------------------------------------------------------------------------------------
-
-#INST lbi_0/lt_0/lclk_0/CLK2X_BUFG_INST LOC=BUFGMUX_X1Y0; 
-##### mcattin #####
-#INST cmp_gn4124_core/cmp_p2l_des/iclk_bufg  LOC = BUFGMUX_X2Y10;
-#INST cmp_gn4124_core/cmp_p2l_des/iclkn_bufg LOC = BUFGMUX_X2Y11;
-#NET "P2L_CLKp" CLOCK_DEDICATED_ROUTE = FALSE;
-#NET "P2L_CLKn" CLOCK_DEDICATED_ROUTE = FALSE;
-
-#NET "cmp_gn4124_core/cmp_p2l_des/iclk_i" maxdelay = 0.1 ns;
-#NET "cmp_gn4124_core/cmp_p2l_des/iclkn_i" maxdelay = 0.1 ns;
-##### mcattin #####
-
-#INST cmp_gn4124_core/clk_p_bufg LOC = BUFGMUX_X2Y10;
-#INST cmp_gn4124_core/clk_n_bufg LOC = BUFGMUX_X2Y11;
-INST cmp_gn4124_core/clk_bufg LOC = BUFGMUX_X2Y10;
-INST cmp_gn4124_core/clkn_bufg LOC = BUFGMUX_X2Y11;
-NET "P2L_CLKp" CLOCK_DEDICATED_ROUTE = FALSE;
-NET "P2L_CLKn" CLOCK_DEDICATED_ROUTE = FALSE;
-
-NET "cmp_gn4124_core/clk_p_buf" maxdelay = 0.1 ns;
-NET "cmp_gn4124_core/clk_n_buf" maxdelay = 0.1 ns;
-
-#The IO Location Constraints 
-NET "des_h" LOC = C10;
-NET "gpio[4]" LOC = AB13;
-#NET "ser[14]" LOC = A20;
-#NET "ddr2_dqs[2]" LOC = K1;
-NET "gpio[5]" LOC = AA3;
-#NET "ser[15]" LOC = E15;
-#NET "cntrl0_ddr2_dqs[3]" LOC = H4;
-#NET "cntrl0_ddr2_cs_n" LOC = C1;
-NET "gpio[6]" LOC = AA4;
-#NET "ser[16]" LOC = F15;
-NET "des_v" LOC = G11;
-NET "gpio[7]" LOC = AA8;
-#NET "ser[17]" LOC = C18;
-NET "syncseperator_f_timing" LOC = D7;
-NET "p2l_dframe" LOC = L22;
-NET "gpio[8]" LOC = V10;
-NET "des[10]" LOC = E16;
-#NET "ser[18]" LOC = A18;
-NET "gpio[9]" LOC = AB2;
-NET "des[11]" LOC = G15;
-#NET "ser[19]" LOC = A19;
-NET "des[12]" LOC = G16;
-NET "tx_error" LOC = M16;
-NET "des[13]" LOC = G14;
-#NET "cntrl0_ddr2_ck_n[0]" LOC = AA2;
-NET "des[14]" LOC = H14;
-NET "l2p_rdy" LOC = P16;
-#NET "cntrl0_ddr2_ck_n[1]" LOC = Y2;
-#NET "cntrl0_ddr2_a[0]" LOC = D3;
-NET "des[15]" LOC = H13;
-NET "l2p_valid" LOC = T19;
-#NET "cntrl0_ddr2_a[1]" LOC = G5;
-NET "des[16]" LOC = F12;
-#NET "cntrl0_ddr2_dq[0]" LOC = W1;
-#NET "cntrl0_ddr2_a[2]" LOC = G6;
-NET "des[17]" LOC = G12;
-#NET "cntrl0_ddr2_dq[1]" LOC = W2;
-#NET "sys_clkb" LOC = U12;
-NET "l2p_data[10]" LOC = R19;
-#NET "cntrl0_ddr2_a[3]" LOC = E1;
-NET "des[18]" LOC = D11;
-#NET "cntrl0_ddr2_dq[2]" LOC = U3;
-NET "p2l_valid" LOC = M22;
-NET "l2p_data[11]" LOC = N18;
-#NET "cntrl0_ddr2_a[4]" LOC = D1;
-NET "des[19]" LOC = C5;
-#NET "cntrl0_ddr2_dq[3]" LOC = U4;
-NET "l2p_data[12]" LOC = U19;
-#NET "cntrl0_ddr2_a[5]" LOC = E3;
-#NET "cntrl0_ddr2_dq[4]" LOC = V1;
-NET "l2p_data[13]" LOC = U21;
-#NET "cntrl0_ddr2_a[6]" LOC = F4;
-#NET "cntrl0_ddr2_dq[5]" LOC = V3;
-NET "des[0]" LOC = A8;
-NET "l2p_data[14]" LOC = U20;
-#NET "cntrl0_ddr2_a[7]" LOC = G4;
-#NET "cntrl0_ddr2_dq[6]" LOC = U1;
-NET "des[1]" LOC = D10;
-NET "l2p_edb" LOC = L21;
-NET "l2p_data[15]" LOC = N19;
-#NET "cntrl0_ddr2_a[8]" LOC = F3;
-#NET "cntrl0_ddr2_dq[7]" LOC = U2;
-NET "des[2]" LOC = E10;
-#NET "cntrl0_ddr2_a[9]" LOC = H6;
-#NET "cntrl0_ddr2_dq[8]" LOC = R5;
-NET "des[3]" LOC = H10;
-#NET "cntrl0_ddr2_dq[9]" LOC = T3;
-NET "des[4]" LOC = B9;
-NET "des[5]" LOC = B8;
-NET "p_rd_d_rdy[0]" LOC = N17;
-NET "p_rd_d_rdy[1]" LOC = P18;
-NET "des[6]" LOC = C8;
-NET "des[7]" LOC = G10;
-NET "l_rst_n" LOC = N20;
-NET "p2l_data[10]" LOC = K19;
-NET "p_wr_rdy[0]" LOC = T20;
-NET "p_wr_rdy[1]" LOC = T22;
-NET "des[8]" LOC = A7;
-NET "p2l_data[11]" LOC = M20;
-NET "des[9]" LOC = A6;
-NET "p2l_data[12]" LOC = G22;
-NET "p2l_data[13]" LOC = L18;
-NET "p2l_data[14]" LOC = M18;
-NET "p2l_rdy" LOC = D21;
-NET "p2l_data[15]" LOC = K20;
-NET "l2p_clkn" LOC = Y21;
-NET "l2p_clkp" LOC = AA22;
-#NET "ser[0]" LOC = D17;
-#NET "ser[1]" LOC = C17;
-NET "des_dvb_asi" LOC = E13;
-#NET "ser[2]" LOC = D16;
-NET "debug[0]" LOC = AB11;
-NET "syncseperator_v_timing" LOC = B6;
-#NET "ser[3]" LOC = C16;
-NET "rx_error" LOC = U22;
-NET "des_smpte_bypass" LOC = A13;
-NET "debug[1]" LOC = Y11;
-#NET "ser[4]" LOC = C14;
-NET "debug[2]" LOC = R10;
-#NET "ser[5]" LOC = E14;
-NET "debug[3]" LOC = AB10;
-#NET "ser[6]" LOC = B17;
-NET "debug[4]" LOC = U7;
-#NET "ser[7]" LOC = A17;
-NET "debug[5]" LOC = V7;
-#NET "ser[8]" LOC = D15;
-NET "debug[6]" LOC = U8;
-#NET "ser[9]" LOC = C15;
-NET "debug[7]" LOC = T9;
-NET "vc_rdy[0]" LOC = N21;
-NET "vc_rdy[1]" LOC = L20;
-NET "mic_data[0]" LOC = AB15;
-NET "mic_data[1]" LOC = Y17;
-#NET "cntrl0_ddr2_we_n" LOC = G17;
-NET "mic_data[2]" LOC = AA14;
-NET "mic_data[3]" LOC = AA19;
-#NET "cntrl0_ddr2_odt" LOC = G18;
-#NET "cntrl0_ddr2_a[10]" LOC = H5;
-#NET "sys_clk" LOC = V12;
-NET "p2l_clkn" LOC = E12;
-NET "p2l_clkp" LOC = C12;
-NET "mic_data[4]" LOC = Y16;
-#NET "cntrl0_ddr2_a[11]" LOC = J5;
-NET "l_wr_rdy[0]" LOC = M17;
-NET "l_wr_rdy[1]" LOC = R15;
-NET "mic_data[5]" LOC = Y7;
-#NET "cntrl0_ddr2_dq[10]" LOC = R3;
-#NET "cntrl0_ddr2_ck[0]" LOC = AA1;
-#NET "cntrl0_ddr2_a[12]" LOC = K6;
-NET "mic_data[6]" LOC = AB17;
-#NET "cntrl0_ddr2_dq[11]" LOC = R4;
-#NET "cntrl0_ddr2_ck[1]" LOC = Y1;
-NET "mic_data[7]" LOC = AB19;
-NET "l2p_data[0]" LOC = V22;
-#NET "cntrl0_ddr2_dq[12]" LOC = M5;
-NET "mic_data[8]" LOC = AB6;
-NET "l2p_data[1]" LOC = W22;
-NET "cntrl0_ddr2_dq[13]" LOC = N4;
-#NET "cntrl0_ddr2_dqs_n[0]" LOC = U5;
-#NET "cntrl0_ddr2_cas_n" LOC = N3;
-NET "mic_data[9]" LOC = AB8;
-NET "l2p_data[2]" LOC = V20;
-NET "l_clkn" LOC = V11;
-#NET "cntrl0_ddr2_dq[14]" LOC = P3;
-NET "p2l_data[0]" LOC = E22;
-NET "l_clkp" LOC = U11;
-#NET "cntrl0_ddr2_dqs_n[1]" LOC = R2;
-NET "des_sdhdn" LOC = A14;
-NET "l2p_data[3]" LOC = V19;
-#NET "cntrl0_ddr2_dq[20]" LOC = L5;
-#NET "cntrl0_ddr2_dq[15]" LOC = P5;
-NET "p2l_data[1]" LOC = J18;
-#NET "cntrl0_ddr2_dqs_n[2]" LOC = L1;
-NET "l2p_data[4]" LOC = W21;
-#NET "cntrl0_ddr2_dq[21]" LOC = L3;
-#NET "cntrl0_ddr2_dq[16]" LOC = M3;
-NET "p2l_data[2]" LOC = G19;
-#NET "cntrl0_ddr2_dqs_n[3]" LOC = H3;
-NET "l2p_data[5]" LOC = Y22;
-#NET "cntrl0_ddr2_dq[22]" LOC = K3;
-#NET "cntrl0_ddr2_dq[17]" LOC = M4;
-NET "p2l_data[3]" LOC = K15;
-NET "mic_data[10]" LOC = W8;
-NET "l2p_data[6]" LOC = T18;
-#NET "cntrl0_ddr2_dq[23]" LOC = K2;
-#NET "cntrl0_ddr2_dq[18]" LOC = M1;
-NET "p2l_data[4]" LOC = H17;
-NET "mic_data[11]" LOC = V16;
-NET "l2p_data[7]" LOC = T17;
-NET "syncseperator_h_timing" LOC = C7;
-#NET "cntrl0_ddr2_dq[24]" LOC = K5;
-#NET "cntrl0_ddr2_dq[19]" LOC = M2;
-NET "p2l_data[5]" LOC = G20;
-NET "mic_data[12]" LOC = AA6;
-NET "l2p_data[8]" LOC = W20;
-#NET "cntrl0_ddr2_dq[30]" LOC = F2;
-#NET "cntrl0_ddr2_dq[25]" LOC = K4;
-NET "p2l_data[6]" LOC = F22;
-NET "mic_data[13]" LOC = Y8;
-NET "l2p_data[9]" LOC = W19;
-#NET "cntrl0_ddr2_dq[31]" LOC = F1;
-#NET "cntrl0_ddr2_dq[26]" LOC = J3;
-NET "p2l_data[7]" LOC = H19;
-NET "mic_data[14]" LOC = Y6;
-#NET "cntrl0_ddr2_ras_n" LOC = D2;
-#NET "cntrl0_rst_dqs_div_out" LOC = P1;
-#NET "cntrl0_ddr2_dq[27]" LOC = H1;
-NET "p2l_data[8]" LOC = K22;
-NET "mic_data[20]" LOC = AA15;
-NET "mic_data[15]" LOC = V15;
-#NET "cntrl0_ddr2_dq[28]" LOC = G3;
-NET "p2l_data[9]" LOC = K17;
-NET "mic_data[21]" LOC = Y12;
-NET "mic_data[16]" LOC = AB16;
-#NET "cntrl0_ddr2_dq[29]" LOC = G1;
-#NET "cntrl0_ddr2_ba[0]" LOC = B1;
-NET "mic_data[22]" LOC = AB21;
-NET "mic_data[17]" LOC = W17;
-#NET "cntrl0_ddr2_ba[1]" LOC = E4;
-NET "mic_data[23]" LOC = Y13;
-NET "mic_data[18]" LOC = V14;
-NET "reset_in_n" LOC = N8;
-#NET "cntrl0_rst_dqs_div_in" LOC = P2;
-NET "mic_data[24]" LOC = U13;
-NET "mic_data[19]" LOC = Y5;
-NET "gpio[10]" LOC = AB18;
-NET "mic_data[30]" LOC = AB14;
-NET "mic_data[25]" LOC = W18;
-NET "gpio[11]" LOC = Y10;
-NET "mic_data[31]" LOC = W16;
-NET "mic_data[26]" LOC = W15;
-NET "l2p_dframe" LOC = J22;
-NET "gpio[12]" LOC = W6;
-NET "mic_data[27]" LOC = Y18;
-#NET "cntrl0_ddr2_dm[0]" LOC = T4;
-#NET "cntrl0_ddr2_cke" LOC = C2;
-NET "gpio[13]" LOC = Y9;
-NET "mic_data[28]" LOC = AB7;
-#NET "cntrl0_ddr2_dm[1]" LOC = H2;
-NET "gpio[14]" LOC = AB9;
-NET "mic_data[29]" LOC = AA21;
-#NET "cntrl0_ddr2_dm[2]" LOC = V4;
-NET "gpio[15]" LOC = AA10;
-#NET "cntrl0_ddr2_dm[3]" LOC = W3;
-NET "des_pclk" LOC = E11;
-NET "sda" LOC = A16; ##R12;  ##Problem
-#NET "mic_clka" LOC = Y15;
-#NET "mic_clkb" LOC = Y4;
-NET "scl" LOC = W9;
-NET "gpio[0]" LOC = AB5;
-#NET "ser[10]" LOC = E17;
-NET "l_rst33_n" LOC = H8;
-NET "gpio[1]" LOC = W7;
-#NET "ser[11]" LOC = D18;
-NET "gpio[2]" LOC = AB4;
-#NET "ser[12]" LOC = C19;
-#NET "cntrl0_ddr2_dqs[0]" LOC = T5;
-NET "gpio[3]" LOC = AB3;
-#NET "ser[13]" LOC = B20;
-#NET "cntrl0_ddr2_dqs[1]" LOC = R1;
-NET "des_f" LOC = A10;
-#NET "ser_h" LOC = D8;
-#NET "ser_v" LOC = A12;
-#NET "ser_f" LOC = D13;
-#NET "ser_smpte_bypass" LOC = C6;
-#NET "ser_dvb_asi" LOC = A3;
-#NET "ser_sdhdn" LOC = E9;
-NET "p_wr_req[0]" LOC = L15;
-NET "p_wr_req[1]" LOC = R21;
-
-NET "led[0]" LOC = Y14;
-NET "led[1]" LOC = W12;
-NET "led[2]" LOC = V17;
-NET "led[3]" LOC = AA17;
-NET "led[4]" LOC = AA12;
-NET "led[5]" LOC = AB12;
-NET "led[6]" LOC = V9;
-NET "led[7]" LOC = W13;
-
-NET "spi_sck"       LOC = G9;
-NET "spi_ss[0]"     LOC = D5;
-NET "spi_ss[1]"     LOC = B13;
-NET "spi_ss[2]"     LOC = A4;
-NET "spi_ss[3]"     LOC = C13;
-NET "spi_ss[4]"     LOC = B15;
-NET "spi_mosi"      LOC = G13;
-NET "spi_miso"      LOC = A5;
-NET "gs4911_host_B" LOC = B4;
-NET "gs4911_sclk"   LOC = B3;
-NET "gs4911_sdin"   LOC = D6;
-NET "gs4911_sdout"  LOC = E8;
-NET "gs4911_csb"    LOC = A9;
-NET "PCLK_4911_1531" LOC = A11;
-NET "GS4911_LOCK_LOST" LOC = B22;
-NET "GS4911_REF_LOST"  LOC = B21;
-
-#---------------------------------------------------------------------------------------------
-# Prohibit the use of configuration pins
-#---------------------------------------------------------------------------------------------
-CONFIG CONFIG_MODE=S_SERIAL;
-
-CONFIG PROHIBIT = W5;   # MODE 0
-CONFIG PROHIBIT = V6;   # MODE 1
-CONFIG PROHIBIT = W4;   # MODE 2
-CONFIG PROHIBIT = V13;  # INIT_B
-CONFIG PROHIBIT = AB20; # DIN
-CONFIG PROHIBIT = AA20; # CCLK
-CONFIG PROHIBIT = J1;
-CONFIG PROHIBIT = N1;
-CONFIG PROHIBIT = T1;
-CONFIG PROHIBIT = J8;
-CONFIG PROHIBIT = R6;
-CONFIG PROHIBIT = H7;
-CONFIG PROHIBIT = L8;
-CONFIG PROHIBIT = T6;
-CONFIG PROHIBIT = R12;
-CONFIG PROHIBIT = R13;
-CONFIG PROHIBIT = R14;
-CONFIG PROHIBIT = T10;
-CONFIG PROHIBIT = T11;
-CONFIG PROHIBIT = T15;
-CONFIG PROHIBIT = T16;
-CONFIG PROHIBIT = T7;
-CONFIG PROHIBIT = T8;
-CONFIG PROHIBIT = V8;
-CONFIG PROHIBIT = P22;
-CONFIG PROHIBIT = R16;
-CONFIG PROHIBIT = R18;
-CONFIG PROHIBIT = N16;
-CONFIG PROHIBIT = M15;
-CONFIG PROHIBIT = K14;
-CONFIG PROHIBIT = J15;
-CONFIG PROHIBIT = H16;
-CONFIG PROHIBIT = A15;
-CONFIG PROHIBIT = C9;
-CONFIG PROHIBIT = D19;
-CONFIG PROHIBIT = B19;
-CONFIG PROHIBIT = B2;
-CONFIG PROHIBIT = G8;
-CONFIG PROHIBIT = H12;
-CONFIG PROHIBIT = H9;
- 
-
-
diff --git a/hdl/gullwing/ip_cores/fifo_32x512.gise b/hdl/gullwing/ip_cores/fifo_32x512.gise
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diff --git a/hdl/gullwing/ip_cores/fifo_32x512.ncf b/hdl/gullwing/ip_cores/fifo_32x512.ncf
deleted file mode 100644
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deleted file mode 100644
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\ No newline at end of file
diff --git a/hdl/gullwing/ip_cores/fifo_32x512.vhd b/hdl/gullwing/ip_cores/fifo_32x512.vhd
deleted file mode 100644
index a09445938ce0a9c7233da37203cd71c3388d42d2..0000000000000000000000000000000000000000
--- a/hdl/gullwing/ip_cores/fifo_32x512.vhd
+++ /dev/null
@@ -1,164 +0,0 @@
---------------------------------------------------------------------------------
---     This file is owned and controlled by Xilinx and must be used           --
---     solely for design, simulation, implementation and creation of          --
---     design files limited to Xilinx devices or technologies. Use            --
---     with non-Xilinx devices or technologies is expressly prohibited        --
---     and immediately terminates your license.                               --
---                                                                            --
---     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"          --
---     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                --
---     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION        --
---     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            --
---     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS              --
---     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                --
---     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE       --
---     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY               --
---     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                --
---     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR         --
---     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF        --
---     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS        --
---     FOR A PARTICULAR PURPOSE.                                              --
---                                                                            --
---     Xilinx products are not intended for use in life support               --
---     appliances, devices, or systems. Use in such applications are          --
---     expressly prohibited.                                                  --
---                                                                            --
---     (c) Copyright 1995-2009 Xilinx, Inc.                                   --
---     All rights reserved.                                                   --
---------------------------------------------------------------------------------
--- You must compile the wrapper file fifo_32x512.vhd when simulating
--- the core, fifo_32x512. When compiling the wrapper file, be sure to
--- reference the XilinxCoreLib VHDL simulation library. For detailed
--- instructions, please refer to the "CORE Generator Help".
-
--- The synthesis directives "translate_off/translate_on" specified
--- below are supported by Xilinx, Mentor Graphics and Synplicity
--- synthesis tools. Ensure they are correct for your synthesis tool(s).
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
--- synthesis translate_off
-Library XilinxCoreLib;
--- synthesis translate_on
-ENTITY fifo_32x512 IS
-	port (
-	rst: IN std_logic;
-	wr_clk: IN std_logic;
-	rd_clk: IN std_logic;
-	din: IN std_logic_VECTOR(31 downto 0);
-	wr_en: IN std_logic;
-	rd_en: IN std_logic;
-	prog_full_thresh_assert: IN std_logic_VECTOR(8 downto 0);
-	prog_full_thresh_negate: IN std_logic_VECTOR(8 downto 0);
-	dout: OUT std_logic_VECTOR(31 downto 0);
-	full: OUT std_logic;
-	empty: OUT std_logic;
-	valid: OUT std_logic;
-	prog_full: OUT std_logic);
-END fifo_32x512;
-
-ARCHITECTURE fifo_32x512_a OF fifo_32x512 IS
--- synthesis translate_off
-component wrapped_fifo_32x512
-	port (
-	rst: IN std_logic;
-	wr_clk: IN std_logic;
-	rd_clk: IN std_logic;
-	din: IN std_logic_VECTOR(31 downto 0);
-	wr_en: IN std_logic;
-	rd_en: IN std_logic;
-	prog_full_thresh_assert: IN std_logic_VECTOR(8 downto 0);
-	prog_full_thresh_negate: IN std_logic_VECTOR(8 downto 0);
-	dout: OUT std_logic_VECTOR(31 downto 0);
-	full: OUT std_logic;
-	empty: OUT std_logic;
-	valid: OUT std_logic;
-	prog_full: OUT std_logic);
-end component;
-
--- Configuration specification 
-	for all : wrapped_fifo_32x512 use entity XilinxCoreLib.fifo_generator_v6_2(behavioral)
-		generic map(
-			c_has_int_clk => 0,
-			c_wr_response_latency => 1,
-			c_rd_freq => 1,
-			c_has_srst => 0,
-			c_enable_rst_sync => 1,
-			c_has_rd_data_count => 0,
-			c_din_width => 32,
-			c_has_wr_data_count => 0,
-			c_full_flags_rst_val => 1,
-			c_implementation_type => 2,
-			c_family => "spartan3",
-			c_use_embedded_reg => 0,
-			c_has_wr_rst => 0,
-			c_wr_freq => 1,
-			c_use_dout_rst => 1,
-			c_underflow_low => 0,
-			c_has_meminit_file => 0,
-			c_has_overflow => 0,
-			c_preload_latency => 1,
-			c_dout_width => 32,
-			c_msgon_val => 1,
-			c_rd_depth => 512,
-			c_default_value => "BlankString",
-			c_mif_file_name => "BlankString",
-			c_error_injection_type => 0,
-			c_has_underflow => 0,
-			c_has_rd_rst => 0,
-			c_has_almost_full => 0,
-			c_has_rst => 1,
-			c_data_count_width => 9,
-			c_has_wr_ack => 0,
-			c_use_ecc => 0,
-			c_wr_ack_low => 0,
-			c_common_clock => 0,
-			c_rd_pntr_width => 9,
-			c_use_fwft_data_count => 0,
-			c_has_almost_empty => 0,
-			c_rd_data_count_width => 9,
-			c_enable_rlocs => 0,
-			c_wr_pntr_width => 9,
-			c_overflow_low => 0,
-			c_prog_empty_type => 0,
-			c_optimization_mode => 0,
-			c_wr_data_count_width => 9,
-			c_preload_regs => 0,
-			c_dout_rst_val => "0",
-			c_has_data_count => 0,
-			c_prog_full_thresh_negate_val => 508,
-			c_wr_depth => 512,
-			c_prog_empty_thresh_negate_val => 3,
-			c_prog_empty_thresh_assert_val => 2,
-			c_has_valid => 1,
-			c_init_wr_pntr_val => 0,
-			c_prog_full_thresh_assert_val => 509,
-			c_use_fifo16_flags => 0,
-			c_has_backup => 0,
-			c_valid_low => 0,
-			c_prim_fifo_type => "512x36",
-			c_count_type => 0,
-			c_prog_full_type => 4,
-			c_memory_type => 1);
--- synthesis translate_on
-BEGIN
--- synthesis translate_off
-U0 : wrapped_fifo_32x512
-		port map (
-			rst => rst,
-			wr_clk => wr_clk,
-			rd_clk => rd_clk,
-			din => din,
-			wr_en => wr_en,
-			rd_en => rd_en,
-			prog_full_thresh_assert => prog_full_thresh_assert,
-			prog_full_thresh_negate => prog_full_thresh_negate,
-			dout => dout,
-			full => full,
-			empty => empty,
-			valid => valid,
-			prog_full => prog_full);
--- synthesis translate_on
-
-END fifo_32x512_a;
-
diff --git a/hdl/gullwing/ip_cores/fifo_32x512.xco b/hdl/gullwing/ip_cores/fifo_32x512.xco
deleted file mode 100644
index a406f0cab661b3cd3cce897ee98e2fa3d53a6452..0000000000000000000000000000000000000000
--- a/hdl/gullwing/ip_cores/fifo_32x512.xco
+++ /dev/null
@@ -1,84 +0,0 @@
-##############################################################
-#
-# Xilinx Core Generator version 12.2
-# Date: Thu Sep 23 08:35:20 2010
-#
-##############################################################
-#
-#  This file contains the customisation parameters for a
-#  Xilinx CORE Generator IP GUI. It is strongly recommended
-#  that you do not manually alter this file as it may cause
-#  unexpected and unsupported behavior.
-#
-##############################################################
-#
-# BEGIN Project Options
-SET addpads = false
-SET asysymbol = true
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = false
-SET designentry = VHDL
-SET device = xc3s1400a
-SET devicefamily = spartan3a
-SET flowvendor = Foundation_ISE
-SET formalverification = false
-SET foundationsym = false
-SET implementationfiletype = Ngc
-SET package = fg484
-SET removerpms = false
-SET simulationfiles = Behavioral
-SET speedgrade = -5
-SET verilogsim = true
-SET vhdlsim = true
-# END Project Options
-# BEGIN Select
-SELECT Fifo_Generator family Xilinx,_Inc. 6.2
-# END Select
-# BEGIN Parameters
-CSET almost_empty_flag=false
-CSET almost_full_flag=false
-CSET component_name=fifo_32x512
-CSET data_count=false
-CSET data_count_width=9
-CSET disable_timing_violations=false
-CSET dout_reset_value=0
-CSET empty_threshold_assert_value=2
-CSET empty_threshold_negate_value=3
-CSET enable_ecc=false
-CSET enable_int_clk=false
-CSET enable_reset_synchronization=true
-CSET fifo_implementation=Independent_Clocks_Block_RAM
-CSET full_flags_reset_value=1
-CSET full_threshold_assert_value=509
-CSET full_threshold_negate_value=508
-CSET inject_dbit_error=false
-CSET inject_sbit_error=false
-CSET input_data_width=32
-CSET input_depth=512
-CSET output_data_width=32
-CSET output_depth=512
-CSET overflow_flag=false
-CSET overflow_sense=Active_High
-CSET performance_options=Standard_FIFO
-CSET programmable_empty_type=No_Programmable_Empty_Threshold
-CSET programmable_full_type=Multiple_Programmable_Full_Threshold_Input_Ports
-CSET read_clock_frequency=1
-CSET read_data_count=false
-CSET read_data_count_width=9
-CSET reset_pin=true
-CSET reset_type=Asynchronous_Reset
-CSET underflow_flag=false
-CSET underflow_sense=Active_High
-CSET use_dout_reset=true
-CSET use_embedded_registers=false
-CSET use_extra_logic=false
-CSET valid_flag=true
-CSET valid_sense=Active_High
-CSET write_acknowledge_flag=false
-CSET write_acknowledge_sense=Active_High
-CSET write_clock_frequency=1
-CSET write_data_count=false
-CSET write_data_count_width=9
-# END Parameters
-GENERATE
-# CRC: ce29be58
diff --git a/hdl/gullwing/ip_cores/fifo_32x512.xise b/hdl/gullwing/ip_cores/fifo_32x512.xise
deleted file mode 100644
index 79e7c4620af73a547271b05e1f56a7f9f79d6abf..0000000000000000000000000000000000000000
--- a/hdl/gullwing/ip_cores/fifo_32x512.xise
+++ /dev/null
@@ -1,73 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <header>
-    <!-- ISE source project file created by Project Navigator.             -->
-    <!--                                                                   -->
-    <!-- This file contains project source information including a list of -->
-    <!-- project source files, project and process properties.  This file, -->
-    <!-- along with the project source files, is sufficient to open and    -->
-    <!-- implement in ISE Project Navigator.                               -->
-    <!--                                                                   -->
-    <!-- Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved. -->
-  </header>
-
-  <version xil_pn:ise_version="12.2" xil_pn:schema_version="2"/>
-
-  <files>
-    <file xil_pn:name="fifo_32x512.ngc" xil_pn:type="FILE_NGC">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="fifo_32x512.v" xil_pn:type="FILE_VERILOG"/>
-    <file xil_pn:name="fifo_32x512.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-      <association xil_pn:name="PostMapSimulation"/>
-      <association xil_pn:name="PostRouteSimulation"/>
-      <association xil_pn:name="PostTranslateSimulation"/>
-    </file>
-  </files>
-
-  <properties>
-    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device" xil_pn:value="xc3s1400a" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device Family" xil_pn:value="Spartan3A and Spartan3AN" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|fifo_32x512|fifo_32x512_a" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="fifo_32x512.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/fifo_32x512" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Package" xil_pn:value="fg484" xil_pn:valueState="default"/>
-    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Speed Grade" xil_pn:value="-5" xil_pn:valueState="default"/>
-    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
-    <!--                                                                                  -->
-    <!-- The following properties are for internal use only. These should not be modified.-->
-    <!--                                                                                  -->
-    <property xil_pn:name="PROP_DesignName" xil_pn:value="fifo_32x512" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3a" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2010-09-23T10:35:27" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="134B851861F96372525873D4E7767890" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
-  </properties>
-
-  <bindings/>
-
-  <libraries/>
-
-  <autoManagedFiles>
-    <!-- The following files are identified by `include statements in verilog -->
-    <!-- source files and are automatically managed by Project Navigator.     -->
-    <!--                                                                      -->
-    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
-    <!-- project is analyzed based on files automatically identified as       -->
-    <!-- include files.                                                       -->
-  </autoManagedFiles>
-
-</project>
diff --git a/hdl/gullwing/ip_cores/fifo_64x512.gise b/hdl/gullwing/ip_cores/fifo_64x512.gise
deleted file mode 100644
index 092ca06fc0ad78dfc8f7a65d4e2c0e4e9a177db0..0000000000000000000000000000000000000000
--- a/hdl/gullwing/ip_cores/fifo_64x512.gise
+++ /dev/null
@@ -1,28 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <!--                                                          -->
-
-  <!--             For tool use only. Do not edit.              -->
-
-  <!--                                                          -->
-
-  <!-- ProjectNavigator created generated project file.         -->
-
-  <!-- For use in tracking generated file and other information -->
-
-  <!-- allowing preservation of process status.                 -->
-
-  <!--                                                          -->
-
-  <!-- Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved. -->
-
-  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
-
-  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="fifo_64x512.xise"/>
-
-  <files xmlns="http://www.xilinx.com/XMLSchema"/>
-
-  <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
-
-</generated_project>
diff --git a/hdl/gullwing/ip_cores/fifo_64x512.ncf b/hdl/gullwing/ip_cores/fifo_64x512.ncf
deleted file mode 100644
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..0000000000000000000000000000000000000000
diff --git a/hdl/gullwing/ip_cores/fifo_64x512.ngc b/hdl/gullwing/ip_cores/fifo_64x512.ngc
deleted file mode 100644
index b24c95e4f55c51d7c14e26639639dc87c41f55a4..0000000000000000000000000000000000000000
--- a/hdl/gullwing/ip_cores/fifo_64x512.ngc
+++ /dev/null
@@ -1,3 +0,0 @@
-XILINX-XDB 0.1 STUB 0.1 ASCII
-XILINX-XDM V1.6e
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\ No newline at end of file
diff --git a/hdl/gullwing/ip_cores/fifo_64x512.vhd b/hdl/gullwing/ip_cores/fifo_64x512.vhd
deleted file mode 100644
index c5901574571f014e865d1338a3b32644a5d2027e..0000000000000000000000000000000000000000
--- a/hdl/gullwing/ip_cores/fifo_64x512.vhd
+++ /dev/null
@@ -1,164 +0,0 @@
---------------------------------------------------------------------------------
---     This file is owned and controlled by Xilinx and must be used           --
---     solely for design, simulation, implementation and creation of          --
---     design files limited to Xilinx devices or technologies. Use            --
---     with non-Xilinx devices or technologies is expressly prohibited        --
---     and immediately terminates your license.                               --
---                                                                            --
---     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"          --
---     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                --
---     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION        --
---     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            --
---     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS              --
---     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                --
---     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE       --
---     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY               --
---     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                --
---     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR         --
---     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF        --
---     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS        --
---     FOR A PARTICULAR PURPOSE.                                              --
---                                                                            --
---     Xilinx products are not intended for use in life support               --
---     appliances, devices, or systems. Use in such applications are          --
---     expressly prohibited.                                                  --
---                                                                            --
---     (c) Copyright 1995-2009 Xilinx, Inc.                                   --
---     All rights reserved.                                                   --
---------------------------------------------------------------------------------
--- You must compile the wrapper file fifo_64x512.vhd when simulating
--- the core, fifo_64x512. When compiling the wrapper file, be sure to
--- reference the XilinxCoreLib VHDL simulation library. For detailed
--- instructions, please refer to the "CORE Generator Help".
-
--- The synthesis directives "translate_off/translate_on" specified
--- below are supported by Xilinx, Mentor Graphics and Synplicity
--- synthesis tools. Ensure they are correct for your synthesis tool(s).
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
--- synthesis translate_off
-Library XilinxCoreLib;
--- synthesis translate_on
-ENTITY fifo_64x512 IS
-	port (
-	rst: IN std_logic;
-	wr_clk: IN std_logic;
-	rd_clk: IN std_logic;
-	din: IN std_logic_VECTOR(63 downto 0);
-	wr_en: IN std_logic;
-	rd_en: IN std_logic;
-	prog_full_thresh_assert: IN std_logic_VECTOR(8 downto 0);
-	prog_full_thresh_negate: IN std_logic_VECTOR(8 downto 0);
-	dout: OUT std_logic_VECTOR(63 downto 0);
-	full: OUT std_logic;
-	empty: OUT std_logic;
-	valid: OUT std_logic;
-	prog_full: OUT std_logic);
-END fifo_64x512;
-
-ARCHITECTURE fifo_64x512_a OF fifo_64x512 IS
--- synthesis translate_off
-component wrapped_fifo_64x512
-	port (
-	rst: IN std_logic;
-	wr_clk: IN std_logic;
-	rd_clk: IN std_logic;
-	din: IN std_logic_VECTOR(63 downto 0);
-	wr_en: IN std_logic;
-	rd_en: IN std_logic;
-	prog_full_thresh_assert: IN std_logic_VECTOR(8 downto 0);
-	prog_full_thresh_negate: IN std_logic_VECTOR(8 downto 0);
-	dout: OUT std_logic_VECTOR(63 downto 0);
-	full: OUT std_logic;
-	empty: OUT std_logic;
-	valid: OUT std_logic;
-	prog_full: OUT std_logic);
-end component;
-
--- Configuration specification 
-	for all : wrapped_fifo_64x512 use entity XilinxCoreLib.fifo_generator_v6_2(behavioral)
-		generic map(
-			c_has_int_clk => 0,
-			c_wr_response_latency => 1,
-			c_rd_freq => 1,
-			c_has_srst => 0,
-			c_enable_rst_sync => 1,
-			c_has_rd_data_count => 0,
-			c_din_width => 64,
-			c_has_wr_data_count => 0,
-			c_full_flags_rst_val => 1,
-			c_implementation_type => 2,
-			c_family => "spartan3",
-			c_use_embedded_reg => 0,
-			c_has_wr_rst => 0,
-			c_wr_freq => 1,
-			c_use_dout_rst => 1,
-			c_underflow_low => 0,
-			c_has_meminit_file => 0,
-			c_has_overflow => 0,
-			c_preload_latency => 1,
-			c_dout_width => 64,
-			c_msgon_val => 1,
-			c_rd_depth => 512,
-			c_default_value => "BlankString",
-			c_mif_file_name => "BlankString",
-			c_error_injection_type => 0,
-			c_has_underflow => 0,
-			c_has_rd_rst => 0,
-			c_has_almost_full => 0,
-			c_has_rst => 1,
-			c_data_count_width => 9,
-			c_has_wr_ack => 0,
-			c_use_ecc => 0,
-			c_wr_ack_low => 0,
-			c_common_clock => 0,
-			c_rd_pntr_width => 9,
-			c_use_fwft_data_count => 0,
-			c_has_almost_empty => 0,
-			c_rd_data_count_width => 9,
-			c_enable_rlocs => 0,
-			c_wr_pntr_width => 9,
-			c_overflow_low => 0,
-			c_prog_empty_type => 0,
-			c_optimization_mode => 0,
-			c_wr_data_count_width => 9,
-			c_preload_regs => 0,
-			c_dout_rst_val => "0",
-			c_has_data_count => 0,
-			c_prog_full_thresh_negate_val => 508,
-			c_wr_depth => 512,
-			c_prog_empty_thresh_negate_val => 3,
-			c_prog_empty_thresh_assert_val => 2,
-			c_has_valid => 1,
-			c_init_wr_pntr_val => 0,
-			c_prog_full_thresh_assert_val => 509,
-			c_use_fifo16_flags => 0,
-			c_has_backup => 0,
-			c_valid_low => 0,
-			c_prim_fifo_type => "512x72",
-			c_count_type => 0,
-			c_prog_full_type => 4,
-			c_memory_type => 1);
--- synthesis translate_on
-BEGIN
--- synthesis translate_off
-U0 : wrapped_fifo_64x512
-		port map (
-			rst => rst,
-			wr_clk => wr_clk,
-			rd_clk => rd_clk,
-			din => din,
-			wr_en => wr_en,
-			rd_en => rd_en,
-			prog_full_thresh_assert => prog_full_thresh_assert,
-			prog_full_thresh_negate => prog_full_thresh_negate,
-			dout => dout,
-			full => full,
-			empty => empty,
-			valid => valid,
-			prog_full => prog_full);
--- synthesis translate_on
-
-END fifo_64x512_a;
-
diff --git a/hdl/gullwing/ip_cores/fifo_64x512.xco b/hdl/gullwing/ip_cores/fifo_64x512.xco
deleted file mode 100644
index c05ddc9d40dfe2de5376e94d383df512d1ed6b2b..0000000000000000000000000000000000000000
--- a/hdl/gullwing/ip_cores/fifo_64x512.xco
+++ /dev/null
@@ -1,84 +0,0 @@
-##############################################################
-#
-# Xilinx Core Generator version 12.2
-# Date: Thu Sep 23 08:42:15 2010
-#
-##############################################################
-#
-#  This file contains the customisation parameters for a
-#  Xilinx CORE Generator IP GUI. It is strongly recommended
-#  that you do not manually alter this file as it may cause
-#  unexpected and unsupported behavior.
-#
-##############################################################
-#
-# BEGIN Project Options
-SET addpads = false
-SET asysymbol = true
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = false
-SET designentry = VHDL
-SET device = xc3s1400a
-SET devicefamily = spartan3a
-SET flowvendor = Foundation_ISE
-SET formalverification = false
-SET foundationsym = false
-SET implementationfiletype = Ngc
-SET package = fg484
-SET removerpms = false
-SET simulationfiles = Behavioral
-SET speedgrade = -5
-SET verilogsim = true
-SET vhdlsim = true
-# END Project Options
-# BEGIN Select
-SELECT Fifo_Generator family Xilinx,_Inc. 6.2
-# END Select
-# BEGIN Parameters
-CSET almost_empty_flag=false
-CSET almost_full_flag=false
-CSET component_name=fifo_64x512
-CSET data_count=false
-CSET data_count_width=9
-CSET disable_timing_violations=false
-CSET dout_reset_value=0
-CSET empty_threshold_assert_value=2
-CSET empty_threshold_negate_value=3
-CSET enable_ecc=false
-CSET enable_int_clk=false
-CSET enable_reset_synchronization=true
-CSET fifo_implementation=Independent_Clocks_Block_RAM
-CSET full_flags_reset_value=1
-CSET full_threshold_assert_value=509
-CSET full_threshold_negate_value=508
-CSET inject_dbit_error=false
-CSET inject_sbit_error=false
-CSET input_data_width=64
-CSET input_depth=512
-CSET output_data_width=64
-CSET output_depth=512
-CSET overflow_flag=false
-CSET overflow_sense=Active_High
-CSET performance_options=Standard_FIFO
-CSET programmable_empty_type=No_Programmable_Empty_Threshold
-CSET programmable_full_type=Multiple_Programmable_Full_Threshold_Input_Ports
-CSET read_clock_frequency=1
-CSET read_data_count=false
-CSET read_data_count_width=9
-CSET reset_pin=true
-CSET reset_type=Asynchronous_Reset
-CSET underflow_flag=false
-CSET underflow_sense=Active_High
-CSET use_dout_reset=true
-CSET use_embedded_registers=false
-CSET use_extra_logic=false
-CSET valid_flag=true
-CSET valid_sense=Active_High
-CSET write_acknowledge_flag=false
-CSET write_acknowledge_sense=Active_High
-CSET write_clock_frequency=1
-CSET write_data_count=false
-CSET write_data_count_width=9
-# END Parameters
-GENERATE
-# CRC: bbf199eb
diff --git a/hdl/gullwing/ip_cores/fifo_64x512.xise b/hdl/gullwing/ip_cores/fifo_64x512.xise
deleted file mode 100644
index fb04b7fb73a1f210c4f6c3bb2366ae8de4198cc1..0000000000000000000000000000000000000000
--- a/hdl/gullwing/ip_cores/fifo_64x512.xise
+++ /dev/null
@@ -1,73 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <header>
-    <!-- ISE source project file created by Project Navigator.             -->
-    <!--                                                                   -->
-    <!-- This file contains project source information including a list of -->
-    <!-- project source files, project and process properties.  This file, -->
-    <!-- along with the project source files, is sufficient to open and    -->
-    <!-- implement in ISE Project Navigator.                               -->
-    <!--                                                                   -->
-    <!-- Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved. -->
-  </header>
-
-  <version xil_pn:ise_version="12.2" xil_pn:schema_version="2"/>
-
-  <files>
-    <file xil_pn:name="fifo_64x512.ngc" xil_pn:type="FILE_NGC">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="fifo_64x512.v" xil_pn:type="FILE_VERILOG"/>
-    <file xil_pn:name="fifo_64x512.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-      <association xil_pn:name="PostMapSimulation"/>
-      <association xil_pn:name="PostRouteSimulation"/>
-      <association xil_pn:name="PostTranslateSimulation"/>
-    </file>
-  </files>
-
-  <properties>
-    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device" xil_pn:value="xc3s1400a" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device Family" xil_pn:value="Spartan3A and Spartan3AN" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|fifo_64x512|fifo_64x512_a" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="fifo_64x512.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/fifo_64x512" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Package" xil_pn:value="fg484" xil_pn:valueState="default"/>
-    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Speed Grade" xil_pn:value="-5" xil_pn:valueState="default"/>
-    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
-    <!--                                                                                  -->
-    <!-- The following properties are for internal use only. These should not be modified.-->
-    <!--                                                                                  -->
-    <property xil_pn:name="PROP_DesignName" xil_pn:value="fifo_64x512" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3a" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2010-09-23T10:42:21" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="39408F1BAE3A8081592B702FA80F00A3" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
-  </properties>
-
-  <bindings/>
-
-  <libraries/>
-
-  <autoManagedFiles>
-    <!-- The following files are identified by `include statements in verilog -->
-    <!-- source files and are automatically managed by Project Navigator.     -->
-    <!--                                                                      -->
-    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
-    <!-- project is analyzed based on files automatically identified as       -->
-    <!-- include files.                                                       -->
-  </autoManagedFiles>
-
-</project>
diff --git a/hdl/gullwing/ip_cores/ram_2048x32.gise b/hdl/gullwing/ip_cores/ram_2048x32.gise
deleted file mode 100644
index fc5af56f31119a2f5b4e2982d0fe6e9843bf2360..0000000000000000000000000000000000000000
--- a/hdl/gullwing/ip_cores/ram_2048x32.gise
+++ /dev/null
@@ -1,28 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <!--                                                          -->
-
-  <!--             For tool use only. Do not edit.              -->
-
-  <!--                                                          -->
-
-  <!-- ProjectNavigator created generated project file.         -->
-
-  <!-- For use in tracking generated file and other information -->
-
-  <!-- allowing preservation of process status.                 -->
-
-  <!--                                                          -->
-
-  <!-- Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved. -->
-
-  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
-
-  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="ram_2048x32.xise"/>
-
-  <files xmlns="http://www.xilinx.com/XMLSchema"/>
-
-  <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
-
-</generated_project>
diff --git a/hdl/gullwing/ip_cores/ram_2048x32.mif b/hdl/gullwing/ip_cores/ram_2048x32.mif
deleted file mode 100755
index b909ba07a296ec0c90c9af38f0bd669f35f0f91e..0000000000000000000000000000000000000000
--- a/hdl/gullwing/ip_cores/ram_2048x32.mif
+++ /dev/null
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-00000000000000000001000100010001
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-00000000000000000001000100010001
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diff --git a/hdl/gullwing/ip_cores/ram_2048x32.ncf b/hdl/gullwing/ip_cores/ram_2048x32.ncf
deleted file mode 100644
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..0000000000000000000000000000000000000000
diff --git a/hdl/gullwing/ip_cores/ram_2048x32.ngc b/hdl/gullwing/ip_cores/ram_2048x32.ngc
deleted file mode 100644
index 6174249d189cb034dc8787f421e08631d66d37d3..0000000000000000000000000000000000000000
--- a/hdl/gullwing/ip_cores/ram_2048x32.ngc
+++ /dev/null
@@ -1,3 +0,0 @@
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\ No newline at end of file
diff --git a/hdl/gullwing/ip_cores/ram_2048x32.vhd b/hdl/gullwing/ip_cores/ram_2048x32.vhd
deleted file mode 100644
index 83c10168ac5d34cb41b5c9e1727517001bfe02ed..0000000000000000000000000000000000000000
--- a/hdl/gullwing/ip_cores/ram_2048x32.vhd
+++ /dev/null
@@ -1,132 +0,0 @@
---------------------------------------------------------------------------------
---     This file is owned and controlled by Xilinx and must be used           --
---     solely for design, simulation, implementation and creation of          --
---     design files limited to Xilinx devices or technologies. Use            --
---     with non-Xilinx devices or technologies is expressly prohibited        --
---     and immediately terminates your license.                               --
---                                                                            --
---     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"          --
---     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                --
---     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION        --
---     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            --
---     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS              --
---     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                --
---     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE       --
---     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY               --
---     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                --
---     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR         --
---     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF        --
---     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS        --
---     FOR A PARTICULAR PURPOSE.                                              --
---                                                                            --
---     Xilinx products are not intended for use in life support               --
---     appliances, devices, or systems. Use in such applications are          --
---     expressly prohibited.                                                  --
---                                                                            --
---     (c) Copyright 1995-2009 Xilinx, Inc.                                   --
---     All rights reserved.                                                   --
---------------------------------------------------------------------------------
--- You must compile the wrapper file ram_2048x32.vhd when simulating
--- the core, ram_2048x32. When compiling the wrapper file, be sure to
--- reference the XilinxCoreLib VHDL simulation library. For detailed
--- instructions, please refer to the "CORE Generator Help".
-
--- The synthesis directives "translate_off/translate_on" specified
--- below are supported by Xilinx, Mentor Graphics and Synplicity
--- synthesis tools. Ensure they are correct for your synthesis tool(s).
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
--- synthesis translate_off
-Library XilinxCoreLib;
--- synthesis translate_on
-ENTITY ram_2048x32 IS
-	port (
-	clka: IN std_logic;
-	wea: IN std_logic_VECTOR(0 downto 0);
-	addra: IN std_logic_VECTOR(10 downto 0);
-	dina: IN std_logic_VECTOR(31 downto 0);
-	douta: OUT std_logic_VECTOR(31 downto 0));
-END ram_2048x32;
-
-ARCHITECTURE ram_2048x32_a OF ram_2048x32 IS
--- synthesis translate_off
-component wrapped_ram_2048x32
-	port (
-	clka: IN std_logic;
-	wea: IN std_logic_VECTOR(0 downto 0);
-	addra: IN std_logic_VECTOR(10 downto 0);
-	dina: IN std_logic_VECTOR(31 downto 0);
-	douta: OUT std_logic_VECTOR(31 downto 0));
-end component;
-
--- Configuration specification 
-	for all : wrapped_ram_2048x32 use entity XilinxCoreLib.blk_mem_gen_v4_2(behavioral)
-		generic map(
-			c_has_regceb => 0,
-			c_has_regcea => 0,
-			c_mem_type => 0,
-			c_rstram_b => 0,
-			c_rstram_a => 0,
-			c_has_injecterr => 0,
-			c_rst_type => "SYNC",
-			c_prim_type => 1,
-			c_read_width_b => 32,
-			c_initb_val => "0",
-			c_family => "spartan3",
-			c_read_width_a => 32,
-			c_disable_warn_bhv_coll => 0,
-			c_use_softecc => 0,
-			c_write_mode_b => "WRITE_FIRST",
-			c_init_file_name => "/home/mcattin/projects/GN4124_core/hdl/gn4124core/design/ipcore_dir/ram_2048x32.mif",
-			c_write_mode_a => "WRITE_FIRST",
-			c_mux_pipeline_stages => 0,
-			c_has_softecc_output_regs_b => 0,
-			c_has_mem_output_regs_b => 0,
-			c_has_mem_output_regs_a => 0,
-			c_load_init_file => 1,
-			c_xdevicefamily => "spartan3a",
-			c_write_depth_b => 2048,
-			c_write_depth_a => 2048,
-			c_has_rstb => 0,
-			c_has_rsta => 0,
-			c_has_mux_output_regs_b => 0,
-			c_inita_val => "0",
-			c_has_mux_output_regs_a => 0,
-			c_addra_width => 11,
-			c_has_softecc_input_regs_a => 0,
-			c_addrb_width => 11,
-			c_default_data => "0",
-			c_use_ecc => 0,
-			c_algorithm => 1,
-			c_disable_warn_bhv_range => 0,
-			c_write_width_b => 32,
-			c_write_width_a => 32,
-			c_read_depth_b => 2048,
-			c_read_depth_a => 2048,
-			c_byte_size => 9,
-			c_sim_collision_check => "ALL",
-			c_common_clk => 0,
-			c_wea_width => 1,
-			c_has_enb => 0,
-			c_web_width => 1,
-			c_has_ena => 0,
-			c_use_byte_web => 0,
-			c_use_byte_wea => 0,
-			c_rst_priority_b => "CE",
-			c_rst_priority_a => "CE",
-			c_use_default_data => 0);
--- synthesis translate_on
-BEGIN
--- synthesis translate_off
-U0 : wrapped_ram_2048x32
-		port map (
-			clka => clka,
-			wea => wea,
-			addra => addra,
-			dina => dina,
-			douta => douta);
--- synthesis translate_on
-
-END ram_2048x32_a;
-
diff --git a/hdl/gullwing/ip_cores/ram_2048x32.xco b/hdl/gullwing/ip_cores/ram_2048x32.xco
deleted file mode 100644
index f848be06f23a52569e0fb6d85c5ae4d0258edf5d..0000000000000000000000000000000000000000
--- a/hdl/gullwing/ip_cores/ram_2048x32.xco
+++ /dev/null
@@ -1,93 +0,0 @@
-##############################################################
-#
-# Xilinx Core Generator version 12.2
-# Date: Mon Oct  4 13:58:49 2010
-#
-##############################################################
-#
-#  This file contains the customisation parameters for a
-#  Xilinx CORE Generator IP GUI. It is strongly recommended
-#  that you do not manually alter this file as it may cause
-#  unexpected and unsupported behavior.
-#
-##############################################################
-#
-# BEGIN Project Options
-SET addpads = false
-SET asysymbol = true
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = false
-SET designentry = VHDL
-SET device = xc3s1400a
-SET devicefamily = spartan3a
-SET flowvendor = Foundation_ISE
-SET formalverification = false
-SET foundationsym = false
-SET implementationfiletype = Ngc
-SET package = fg484
-SET removerpms = false
-SET simulationfiles = Behavioral
-SET speedgrade = -5
-SET verilogsim = true
-SET vhdlsim = true
-# END Project Options
-# BEGIN Select
-SELECT Block_Memory_Generator family Xilinx,_Inc. 4.2
-# END Select
-# BEGIN Parameters
-CSET additional_inputs_for_power_estimation=false
-CSET algorithm=Minimum_Area
-CSET assume_synchronous_clk=false
-CSET byte_size=9
-CSET coe_file=./ram_2048x32_init.coe
-CSET collision_warnings=ALL
-CSET component_name=ram_2048x32
-CSET disable_collision_warnings=false
-CSET disable_out_of_range_warnings=false
-CSET ecc=false
-CSET ecctype=No_ECC
-CSET enable_a=Always_Enabled
-CSET enable_b=Always_Enabled
-CSET error_injection_type=Single_Bit_Error_Injection
-CSET fill_remaining_memory_locations=false
-CSET load_init_file=true
-CSET memory_type=Single_Port_RAM
-CSET operating_mode_a=WRITE_FIRST
-CSET operating_mode_b=WRITE_FIRST
-CSET output_reset_value_a=0
-CSET output_reset_value_b=0
-CSET pipeline_stages=0
-CSET port_a_clock=100
-CSET port_a_enable_rate=100
-CSET port_a_write_rate=50
-CSET port_b_clock=0
-CSET port_b_enable_rate=0
-CSET port_b_write_rate=0
-CSET primitive=8kx2
-CSET read_width_a=32
-CSET read_width_b=32
-CSET register_porta_input_of_softecc=false
-CSET register_porta_output_of_memory_core=false
-CSET register_porta_output_of_memory_primitives=false
-CSET register_portb_output_of_memory_core=false
-CSET register_portb_output_of_memory_primitives=false
-CSET register_portb_output_of_softecc=false
-CSET remaining_memory_locations=0
-CSET reset_memory_latch_a=false
-CSET reset_memory_latch_b=false
-CSET reset_priority_a=CE
-CSET reset_priority_b=CE
-CSET reset_type=SYNC
-CSET softecc=false
-CSET use_byte_write_enable=false
-CSET use_error_injection_pins=false
-CSET use_regcea_pin=false
-CSET use_regceb_pin=false
-CSET use_rsta_pin=false
-CSET use_rstb_pin=false
-CSET write_depth_a=2048
-CSET write_width_a=32
-CSET write_width_b=32
-# END Parameters
-GENERATE
-# CRC: d12ee861
diff --git a/hdl/gullwing/ip_cores/ram_2048x32.xise b/hdl/gullwing/ip_cores/ram_2048x32.xise
deleted file mode 100644
index cd621806cc0fbd5035fa16985bcfa412a1570f76..0000000000000000000000000000000000000000
--- a/hdl/gullwing/ip_cores/ram_2048x32.xise
+++ /dev/null
@@ -1,73 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <header>
-    <!-- ISE source project file created by Project Navigator.             -->
-    <!--                                                                   -->
-    <!-- This file contains project source information including a list of -->
-    <!-- project source files, project and process properties.  This file, -->
-    <!-- along with the project source files, is sufficient to open and    -->
-    <!-- implement in ISE Project Navigator.                               -->
-    <!--                                                                   -->
-    <!-- Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved. -->
-  </header>
-
-  <version xil_pn:ise_version="12.2" xil_pn:schema_version="2"/>
-
-  <files>
-    <file xil_pn:name="ram_2048x32.ngc" xil_pn:type="FILE_NGC">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="ram_2048x32.v" xil_pn:type="FILE_VERILOG"/>
-    <file xil_pn:name="ram_2048x32.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-      <association xil_pn:name="PostMapSimulation"/>
-      <association xil_pn:name="PostRouteSimulation"/>
-      <association xil_pn:name="PostTranslateSimulation"/>
-    </file>
-  </files>
-
-  <properties>
-    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device" xil_pn:value="xc3s1400a" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device Family" xil_pn:value="Spartan3A and Spartan3AN" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|ram_2048x32|ram_2048x32_a" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="ram_2048x32.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/ram_2048x32" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Package" xil_pn:value="fg484" xil_pn:valueState="default"/>
-    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Speed Grade" xil_pn:value="-5" xil_pn:valueState="default"/>
-    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
-    <!--                                                                                  -->
-    <!-- The following properties are for internal use only. These should not be modified.-->
-    <!--                                                                                  -->
-    <property xil_pn:name="PROP_DesignName" xil_pn:value="ram_2048x32" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3a" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2010-10-04T15:58:58" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="1940058D9217B62CBF2C14C9FB464AB0" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
-  </properties>
-
-  <bindings/>
-
-  <libraries/>
-
-  <autoManagedFiles>
-    <!-- The following files are identified by `include statements in verilog -->
-    <!-- source files and are automatically managed by Project Navigator.     -->
-    <!--                                                                      -->
-    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
-    <!-- project is analyzed based on files automatically identified as       -->
-    <!-- include files.                                                       -->
-  </autoManagedFiles>
-
-</project>
diff --git a/hdl/gullwing/ip_cores/ram_2048x32_init.coe b/hdl/gullwing/ip_cores/ram_2048x32_init.coe
deleted file mode 100644
index afcf1456a26e36c5db8e4944a760e3561012fd57..0000000000000000000000000000000000000000
--- a/hdl/gullwing/ip_cores/ram_2048x32_init.coe
+++ /dev/null
@@ -1,41 +0,0 @@
-; This .COE file specifies the contents for a block
-
-; memory of depth=2046, and width=32. In this case, values
-
-; are specified in hexadecimal format.
-
-memory_initialization_radix=16;
-
-memory_initialization_vector=
-
-1111,
-
-1111,
-
-1111,
-
-1111,
-
-1111,
-
-0000,
-
-0101,
-
-0011,
-
-0000,
-
-1111,
-
-1111,
-
-1111,
-
-1111,
-
-1111,
-
-1111,
-
-1111; 
\ No newline at end of file
diff --git a/hdl/gullwing/ise_project/gn4124core.xise b/hdl/gullwing/ise_project/gn4124core.xise
deleted file mode 100644
index c6dace70a27ed378a1bac45aa40e2143caa120fd..0000000000000000000000000000000000000000
--- a/hdl/gullwing/ise_project/gn4124core.xise
+++ /dev/null
@@ -1,415 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <header>
-    <!-- ISE source project file created by Project Navigator.             -->
-    <!--                                                                   -->
-    <!-- This file contains project source information including a list of -->
-    <!-- project source files, project and process properties.  This file, -->
-    <!-- along with the project source files, is sufficient to open and    -->
-    <!-- implement in ISE Project Navigator.                               -->
-    <!--                                                                   -->
-    <!-- Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved. -->
-  </header>
-
-  <version xil_pn:ise_version="12.2" xil_pn:schema_version="2"/>
-
-  <files>
-    <file xil_pn:name="../../gn4124core/rtl/l2p_arbiter.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="../../gn4124core/rtl/dma_controller_wb_slave.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="../../gn4124core/rtl/dma_controller.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="../../gn4124core/rtl/gn4124_core.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="../../gn4124core/rtl/l2p_dma_master.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="../../gn4124core/rtl/l2p_ser.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="../../gn4124core/rtl/wbmaster32.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="../../gn4124core/rtl/p2l_des.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="../../gn4124core/rtl/p2l_decode32.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="../rtl/gullwing_wrapper.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="../gullwing.ucf" xil_pn:type="FILE_UCF">
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="../../gn4124core/rtl/p2l_dma_master.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="../../gn4124core/rtl/gn4124_core_pkg.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="../ip_cores/fifo_32x512.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="../ip_cores/fifo_64x512.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="../ip_cores/ram_2048x32.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="../chipscope/cs_core.cdc" xil_pn:type="FILE_CDC">
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="../../common/rtl/dummy_ctrl_regs.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="../../common/rtl/dummy_stat_regs.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="../ip_cores/fifo_32x512.xise" xil_pn:type="FILE_COREGENISE">
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="../ip_cores/fifo_64x512.xise" xil_pn:type="FILE_COREGENISE">
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="../ip_cores/ram_2048x32.xise" xil_pn:type="FILE_COREGENISE">
-      <association xil_pn:name="Implementation"/>
-    </file>
-  </files>
-
-  <properties>
-    <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
-    <property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
-    <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Change Device Speed To" xil_pn:value="-5" xil_pn:valueState="default"/>
-    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-5" xil_pn:valueState="default"/>
-    <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="true" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
-    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Rate" xil_pn:value="25" xil_pn:valueState="default"/>
-    <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Binary Configuration File" xil_pn:value="true" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
-    <property xil_pn:name="Device" xil_pn:value="xc3s1400a" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device Family" xil_pn:value="Spartan3A and Spartan3AN" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-5" xil_pn:valueState="default"/>
-    <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Dummy Driver for Enable Filter on Suspend Input" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Filter on Suspend Input" xil_pn:value="Please use the ENABLE_SUSPEND implementation constraint." xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Power-On Reset Detection" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Suspend/Wake Global Set/Reset" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Extra Effort" xil_pn:value="Normal" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
-    <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="Normal" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
-    <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
-    <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence" xil_pn:value="4" xil_pn:valueState="default"/>
-    <property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence" xil_pn:value="5" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
-    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|gw_wrapper|rtl" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="../rtl/gullwing_wrapper.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/gw_wrapper" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Last Applied Goal" xil_pn:value="Timing Performance" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Last Applied Strategy" xil_pn:value="Performance with Physical Synthesis;/opt/Xilinx/12.2/ISE_DS/ISE/spartan3a/data/spartan3a_performance_with_physicalsynthesis.xds" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default" xil_pn:x_locked="true"/>
-    <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Max Fanout" xil_pn:value="500" xil_pn:valueState="default"/>
-    <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
-    <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
-    <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: Next Configuration Mode" xil_pn:value="001" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: Starting Address for Next Configuration" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: Use New Mode for Next Configuration" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Multiplier Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
-    <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="24" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Effort" xil_pn:value="High" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
-    <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default" xil_pn:x_locked="true"/>
-    <property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output File Name" xil_pn:value="LOTUS" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Yes" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
-    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
-    <property xil_pn:name="Package" xil_pn:value="fg484" xil_pn:valueState="default"/>
-    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="true" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
-    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default" xil_pn:x_locked="true"/>
-    <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default" xil_pn:x_locked="true"/>
-    <property xil_pn:name="Place MultiBoot Settings into Bitstream" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="High" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
-    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="LOTUS_map.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="LOTUS_timesim.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="LOTUS_synthesis.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="LOTUS_translate.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Produce Advanced Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
-    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
-    <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Balancing" xil_pn:value="Yes" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
-    <property xil_pn:name="Register Duplication" xil_pn:value="On" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
-    <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="LOTUS" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Retry Configuration if CRC Error Occurs" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="High" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
-    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Speed Grade" xil_pn:value="-5" xil_pn:valueState="default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
-    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="/opt/Xilinx/12.2/ISE_DS/ISE/spartan3a/data/spartan3a_performance_with_physicalsynthesis.xds" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
-    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
-    <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wakeup Clock" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
-    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <!--                                                                                  -->
-    <!-- The following properties are for internal use only. These should not be modified.-->
-    <!--                                                                                  -->
-    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_DesignName" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3a" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2010-10-05T15:06:20" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="C749A798FCB3171AB6EE962700242584" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
-  </properties>
-
-  <bindings/>
-
-  <libraries/>
-
-  <autoManagedFiles>
-    <!-- The following files are identified by `include statements in verilog -->
-    <!-- source files and are automatically managed by Project Navigator.     -->
-    <!--                                                                      -->
-    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
-    <!-- project is analyzed based on files automatically identified as       -->
-    <!-- include files.                                                       -->
-  </autoManagedFiles>
-
-</project>
diff --git a/hdl/gullwing/ise_project/gw_wrapper.bin b/hdl/gullwing/ise_project/gw_wrapper.bin
deleted file mode 100644
index e87c6e453d66909677ddbb01f348f85411343fd4..0000000000000000000000000000000000000000
Binary files a/hdl/gullwing/ise_project/gw_wrapper.bin and /dev/null differ
diff --git a/hdl/gullwing/ise_project/gw_wrapper.bit b/hdl/gullwing/ise_project/gw_wrapper.bit
deleted file mode 100644
index f46606d8252c5980c17f32e664a5685accfcfc07..0000000000000000000000000000000000000000
Binary files a/hdl/gullwing/ise_project/gw_wrapper.bit and /dev/null differ
diff --git a/hdl/gullwing/ise_project/gw_wrapper.par b/hdl/gullwing/ise_project/gw_wrapper.par
deleted file mode 100644
index 5f4988a51ec1b1f7307bfbe654bc086ce092b201..0000000000000000000000000000000000000000
--- a/hdl/gullwing/ise_project/gw_wrapper.par
+++ /dev/null
@@ -1,605 +0,0 @@
-Release 12.2 par M.63c (lin)
-Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
-
-ABPC10853::  Fri May 13 11:41:24 2011
-
-par -w -intstyle ise -pl high -rl high -xe n -t 1 gw_wrapper_map.ncd
-gw_wrapper.ncd gw_wrapper.pcf 
-
-
-Constraints file: gw_wrapper.pcf.
-Loading device for application Rf_Device from file '3s1400a.nph' in environment /opt/Xilinx/12.2/ISE_DS/ISE/.
-   "gw_wrapper" is an NCD, version 3.2, device xc3s1400a, package fg484, speed -5
-WARNING:ConstraintSystem:64 - Constraint <NET "L_WR_RDY<1>/L_WR_RDY_1_IBUF" MAXDELAY = 2 ns;> [gw_wrapper.pcf(18102)]
-   overrides constraint <NET "L_WR_RDY<1>/L_WR_RDY_1_IBUF" MAXDELAY = 2 ns;> [gw_wrapper.pcf(18101)] on the design
-   object 'L_WR_RDY<1>/L_WR_RDY_1_IBUF'.
-
-WARNING:ConstraintSystem:64 - Constraint <NET "L_WR_RDY<0>/L_WR_RDY_0_IBUF" MAXDELAY = 2 ns;> [gw_wrapper.pcf(18104)]
-   overrides constraint <NET "L_WR_RDY<0>/L_WR_RDY_0_IBUF" MAXDELAY = 2 ns;> [gw_wrapper.pcf(18103)] on the design
-   object 'L_WR_RDY<0>/L_WR_RDY_0_IBUF'.
-
-WARNING:ConstraintSystem:64 - Constraint <NET "VC_RDY<1>_IBUF" MAXDELAY = 2 ns;> [gw_wrapper.pcf(18109)] overrides
-   constraint <NET "VC_RDY<1>_IBUF" MAXDELAY = 2 ns;> [gw_wrapper.pcf(18108)] on the design object 'VC_RDY<1>_IBUF'.
-
-WARNING:ConstraintSystem:64 - Constraint <NET "VC_RDY<0>_IBUF" MAXDELAY = 2 ns;> [gw_wrapper.pcf(18111)] overrides
-   constraint <NET "VC_RDY<0>_IBUF" MAXDELAY = 2 ns;> [gw_wrapper.pcf(18110)] on the design object 'VC_RDY<0>_IBUF'.
-
-
-Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
-Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
-
-
-Device speed data version:  "PRODUCTION 1.41 2010-06-22".
-
-
-
-Design Summary Report:
-
- Number of External IOBs                         179 out of 375    47%
-
-   Number of External Input IOBs                130
-
-      Number of External Input IBUFs            130
-        Number of LOCed External Input IBUFs    130 out of 130   100%
-
-
-   Number of External Output IOBs                45
-
-      Number of External Output DIFFMs            1
-        Number of LOCed External Output DIFFMs    1 out of 1     100%
-
-      Number of External Output DIFFSs            1
-        Number of LOCed External Output DIFFSs    1 out of 1     100%
-
-      Number of External Output IOBs             43
-        Number of LOCed External Output IOBs     37 out of 43     86%
-
-
-   Number of External Bidir IOBs                  0
-
-
-   Number of BSCANs                          1 out of 1     100%
-   Number of BUFGMUXs                        5 out of 24     20%
-      Number of LOCed BUFGMUXs               2 out of 5      40%
-
-   Number of RAMB16BWEs                     28 out of 32     87%
-   Number of Slices                       4248 out of 11264  37%
-      Number of SLICEMs                    315 out of 5632    5%
-
-
-
-Overall effort level (-ol):   Not applicable because -pl and -rl switches are used
-Router effort level (-rl):    High 
-
-INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more information, see the TSI report.  Please
-   consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.
-Starting initial Timing Analysis.  REAL time: 47 secs 
-Finished initial Timing Analysis.  REAL time: 47 secs 
-
-WARNING:Par:288 - The signal RESET_IN_N_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal SPI_SCK_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal SDA_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal SCL_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal GS4911_REF_LOST_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal SPI_MOSI_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal GS4911_LOCK_LOST_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal VC_RDY<0>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal VC_RDY<1>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal SPI_SS<0>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal SPI_SS<1>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal SPI_SS<2>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal SPI_SS<3>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal SPI_SS<4>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal L_RST33_N_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal TX_ERROR_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal DES_F_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal CNTRL0_DDR2_DQ<13>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal DES_H_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal DES_V_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal SYNCSEPERATOR_F_TIMING_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal SYNCSEPERATOR_H_TIMING_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal P_WR_REQ<0>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal P_WR_REQ<1>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal MIC_DATA<0>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal MIC_DATA<1>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal MIC_DATA<2>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal MIC_DATA<3>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal MIC_DATA<4>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal MIC_DATA<5>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal MIC_DATA<6>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal MIC_DATA<7>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal MIC_DATA<8>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal MIC_DATA<9>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal DES<0>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal DES<1>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal DES<2>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal DES<3>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal DES<4>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal DES<5>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal DES<6>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal DES<7>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal DES<8>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal DES<9>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal SYNCSEPERATOR_V_TIMING_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal DES_SMPTE_BYPASS_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal GS4911_SDOUT_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal DES_SDHDN_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal PCLK_4911_1531_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal DES_DVB_ASI_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal MIC_DATA<10>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal MIC_DATA<11>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal MIC_DATA<20>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal MIC_DATA<12>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal MIC_DATA<21>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal MIC_DATA<13>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal MIC_DATA<30>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal MIC_DATA<22>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal MIC_DATA<14>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal MIC_DATA<31>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal MIC_DATA<23>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal MIC_DATA<15>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal MIC_DATA<24>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal MIC_DATA<16>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal MIC_DATA<25>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal MIC_DATA<17>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal MIC_DATA<26>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal MIC_DATA<18>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal MIC_DATA<27>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal MIC_DATA<19>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal MIC_DATA<28>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal MIC_DATA<29>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal DES_PCLK_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal GPIO<10>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal GPIO<11>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal GPIO<12>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal GPIO<13>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal GPIO<14>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal GPIO<15>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal DES<10>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal DES<11>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal DES<12>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal DES<13>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal DES<14>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal DES<15>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal DES<16>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal DES<17>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal DES<18>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal DES<19>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal GPIO<0>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal GPIO<1>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal GPIO<2>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal GPIO<3>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal GPIO<4>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal GPIO<5>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal GPIO<6>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal GPIO<7>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal GPIO<9>_IBUF has no load.  PAR will not attempt to route this signal.
-Starting Router
-
-
-Phase  1  : 25862 unrouted;      REAL time: 1 mins 13 secs 
-
-Phase  2  : 20180 unrouted;      REAL time: 1 mins 14 secs 
-
-Phase  3  : 5034 unrouted;      REAL time: 1 mins 28 secs 
-
-Phase  4  : 5445 unrouted; (Setup:41870, Hold:0, Component Switching Limit:0)     REAL time: 2 mins 20 secs 
-
-Phase  5  : 0 unrouted; (Setup:66529, Hold:0, Component Switching Limit:0)     REAL time: 3 mins 10 secs 
-
-Updating file: gw_wrapper.ncd with current fully routed design.
-
-Phase  6  : 0 unrouted; (Setup:66529, Hold:0, Component Switching Limit:0)     REAL time: 3 mins 16 secs 
-
-Phase  7  : 0 unrouted; (Setup:58880, Hold:0, Component Switching Limit:0)     REAL time: 5 mins 44 secs 
-
-Updating file: gw_wrapper.ncd with current fully routed design.
-
-Phase  8  : 0 unrouted; (Setup:50239, Hold:0, Component Switching Limit:0)     REAL time: 7 mins 1 secs 
-
-Phase  9  : 0 unrouted; (Setup:50239, Hold:0, Component Switching Limit:0)     REAL time: 7 mins 2 secs 
-
-Phase 10  : 0 unrouted; (Setup:37208, Hold:0, Component Switching Limit:0)     REAL time: 7 mins 5 secs 
-WARNING:Route:455 - CLK Net:icon_control0<13> may have excessive skew because 
-      1 CLK pins and 4 NON_CLK pins failed to route using a CLK template.
-
-Total REAL time to Router completion: 7 mins 6 secs 
-Total CPU time to Router completion: 7 mins 1 secs 
-
-Partition Implementation Status
--------------------------------
-
-  No Partitions were found in this design.
-
--------------------------------
-
-Generating "PAR" statistics.
-
-**************************
-Generating Clock Report
-**************************
-
-+---------------------+--------------+------+------+------------+-------------+
-|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
-+---------------------+--------------+------+------+------------+-------------+
-|               l_clk |  BUFGMUX_X2Y1| No   |  951 |  0.265     |  1.150      |
-+---------------------+--------------+------+------+------------+-------------+
-|cmp_gn4124_core/clk_ |              |      |      |            |             |
-|                   p | BUFGMUX_X2Y10|Yes   | 2809 |  0.261     |  1.148      |
-+---------------------+--------------+------+------+------------+-------------+
-|    icon_control0<0> |  BUFGMUX_X1Y0| No   |  180 |  0.167     |  1.053      |
-+---------------------+--------------+------+------+------------+-------------+
-|cmp_gn4124_core/clk_ |              |      |      |            |             |
-|                   n | BUFGMUX_X2Y11|Yes   |   50 |  0.148     |  1.041      |
-+---------------------+--------------+------+------+------------+-------------+
-|U_icon_pro/U0/iUPDAT |              |      |      |            |             |
-|               E_OUT |         Local|      |    1 |  0.000     |  1.699      |
-+---------------------+--------------+------+------+------------+-------------+
-|   icon_control0<13> |         Local|      |    5 |  0.000     |  0.798      |
-+---------------------+--------------+------+------+------------+-------------+
-
-* Net Skew is the difference between the minimum and maximum routing
-only delays for the net. Note this is different from Clock Skew which
-is reported in TRCE timing report. Clock Skew is the difference between
-the minimum and maximum path delays which includes logic delays.
-
-Timing Score: 37208 (Setup: 37208, Hold: 0, Component Switching Limit: 0)
-
-WARNING:Par:468 - Your design did not meet timing.  The following are some suggestions to assist you to meet timing in
-   your design.
-
-   Review the timing report using Timing Analyzer (In ISE select "Post-Place &
-   Route Static Timing Report"). Go to the failing constraint(s) and evaluate the failing paths for each constraint.
-
-   Try the Design Goal and Strategies for Timing Performance(In ISE select Project -> Design Goals & Strategies) to
-   ensure the best options are set in the tools for timing closure.
-
-   Increase the PAR Effort Level setting to "high"
-
-   Use the Xilinx "SmartXplorer" script to try special combinations of
-   options known to produce very good results.
-
-   Visit the Xilinx technical support web at http://support.xilinx.com and go to
-   either "Troubleshoot->Tech Tips->Timing & Constraints" or "
-   TechXclusives->Timing Closure" for tips and suggestions for meeting timing
-   in your design.
-
-Number of Timing Constraints that were not applied: 10
-
-Asterisk (*) preceding a constraint indicates it was not met.
-   This may be due to a setup or hold violation.
-
-----------------------------------------------------------------------------------------------------------
-  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing   
-                                            |             |    Slack   | Achievable | Errors |    Score   
-----------------------------------------------------------------------------------------------------------
-* TS_p2l_clkn = PERIOD TIMEGRP "p2l_clkn_gr | SETUP       |    -0.820ns|     5.820ns|     132|       37208
-  p" 5 ns HIGH 50%                          | HOLD        |     0.337ns|            |       0|           0
-----------------------------------------------------------------------------------------------------------
-  NET "cmp_gn4124_core/clk_p_buf" MAXDELAY  | MAXDELAY    |     0.078ns|     0.022ns|       0|           0
-  = 0.1 ns                                  |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  NET "cmp_gn4124_core/clk_n_buf" MAXDELAY  | MAXDELAY    |     0.078ns|     0.022ns|       0|           0
-  = 0.1 ns                                  |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "L2P_CLKp" OFFSET = OUT 6.5 ns AFTER | MAXDELAY    |     0.237ns|     6.263ns|       0|           0
-   COMP "P2L_CLKp" HIGH                     |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "L2P_CLKn" OFFSET = OUT 6.5 ns AFTER | MAXDELAY    |     0.237ns|     6.263ns|       0|           0
-   COMP "P2L_CLKn" HIGH                     |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "L2P_DATA<12>" OFFSET = OUT 6.5 ns A | MAXDELAY    |     0.313ns|     6.187ns|       0|           0
-  FTER COMP "P2L_CLKp" HIGH                 |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "L2P_DATA<14>" OFFSET = OUT 6.5 ns A | MAXDELAY    |     0.313ns|     6.187ns|       0|           0
-  FTER COMP "P2L_CLKn" HIGH                 |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "L2P_DATA<14>" OFFSET = OUT 6.5 ns A | MAXDELAY    |     0.313ns|     6.187ns|       0|           0
-  FTER COMP "P2L_CLKp" HIGH                 |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "L2P_DATA<12>" OFFSET = OUT 6.5 ns A | MAXDELAY    |     0.313ns|     6.187ns|       0|           0
-  FTER COMP "P2L_CLKn" HIGH                 |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "L2P_DATA<13>" OFFSET = OUT 6.5 ns A | MAXDELAY    |     0.317ns|     6.183ns|       0|           0
-  FTER COMP "P2L_CLKn" HIGH                 |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "L2P_DATA<13>" OFFSET = OUT 6.5 ns A | MAXDELAY    |     0.317ns|     6.183ns|       0|           0
-  FTER COMP "P2L_CLKp" HIGH                 |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "L2P_DFRAME" OFFSET = OUT 6.5 ns AFT | MAXDELAY    |     0.326ns|     6.174ns|       0|           0
-  ER COMP "P2L_CLKn" HIGH                   |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "L2P_DATA<8>" OFFSET = OUT 6.5 ns AF | MAXDELAY    |     0.330ns|     6.170ns|       0|           0
-  TER COMP "P2L_CLKn" HIGH                  |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "L2P_DATA<8>" OFFSET = OUT 6.5 ns AF | MAXDELAY    |     0.330ns|     6.170ns|       0|           0
-  TER COMP "P2L_CLKp" HIGH                  |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "L2P_DATA<1>" OFFSET = OUT 6.5 ns AF | MAXDELAY    |     0.330ns|     6.170ns|       0|           0
-  TER COMP "P2L_CLKp" HIGH                  |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "L2P_DATA<0>" OFFSET = OUT 6.5 ns AF | MAXDELAY    |     0.330ns|     6.170ns|       0|           0
-  TER COMP "P2L_CLKn" HIGH                  |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "L2P_DATA<0>" OFFSET = OUT 6.5 ns AF | MAXDELAY    |     0.330ns|     6.170ns|       0|           0
-  TER COMP "P2L_CLKp" HIGH                  |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "L2P_DATA<9>" OFFSET = OUT 6.5 ns AF | MAXDELAY    |     0.330ns|     6.170ns|       0|           0
-  TER COMP "P2L_CLKp" HIGH                  |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "L2P_DATA<9>" OFFSET = OUT 6.5 ns AF | MAXDELAY    |     0.330ns|     6.170ns|       0|           0
-  TER COMP "P2L_CLKn" HIGH                  |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "L2P_DATA<1>" OFFSET = OUT 6.5 ns AF | MAXDELAY    |     0.330ns|     6.170ns|       0|           0
-  TER COMP "P2L_CLKn" HIGH                  |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "L2P_DATA<11>" OFFSET = OUT 6.5 ns A | MAXDELAY    |     0.336ns|     6.164ns|       0|           0
-  FTER COMP "P2L_CLKn" HIGH                 |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "L2P_DATA<11>" OFFSET = OUT 6.5 ns A | MAXDELAY    |     0.336ns|     6.164ns|       0|           0
-  FTER COMP "P2L_CLKp" HIGH                 |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "L2P_DATA<7>" OFFSET = OUT 6.5 ns AF | MAXDELAY    |     0.337ns|     6.163ns|       0|           0
-  TER COMP "P2L_CLKn" HIGH                  |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "L2P_DATA<7>" OFFSET = OUT 6.5 ns AF | MAXDELAY    |     0.337ns|     6.163ns|       0|           0
-  TER COMP "P2L_CLKp" HIGH                  |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "L2P_DATA<6>" OFFSET = OUT 6.5 ns AF | MAXDELAY    |     0.337ns|     6.163ns|       0|           0
-  TER COMP "P2L_CLKn" HIGH                  |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "L2P_DATA<6>" OFFSET = OUT 6.5 ns AF | MAXDELAY    |     0.337ns|     6.163ns|       0|           0
-  TER COMP "P2L_CLKp" HIGH                  |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "L2P_DATA<2>" OFFSET = OUT 6.5 ns AF | MAXDELAY    |     0.341ns|     6.159ns|       0|           0
-  TER COMP "P2L_CLKn" HIGH                  |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "L2P_DATA<2>" OFFSET = OUT 6.5 ns AF | MAXDELAY    |     0.341ns|     6.159ns|       0|           0
-  TER COMP "P2L_CLKp" HIGH                  |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "L2P_DATA<3>" OFFSET = OUT 6.5 ns AF | MAXDELAY    |     0.341ns|     6.159ns|       0|           0
-  TER COMP "P2L_CLKp" HIGH                  |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "L2P_DATA<3>" OFFSET = OUT 6.5 ns AF | MAXDELAY    |     0.341ns|     6.159ns|       0|           0
-  TER COMP "P2L_CLKn" HIGH                  |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "L2P_DATA<4>" OFFSET = OUT 6.5 ns AF | MAXDELAY    |     0.352ns|     6.148ns|       0|           0
-  TER COMP "P2L_CLKp" HIGH                  |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "L2P_DATA<4>" OFFSET = OUT 6.5 ns AF | MAXDELAY    |     0.352ns|     6.148ns|       0|           0
-  TER COMP "P2L_CLKn" HIGH                  |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "L2P_DATA<5>" OFFSET = OUT 6.5 ns AF | MAXDELAY    |     0.352ns|     6.148ns|       0|           0
-  TER COMP "P2L_CLKp" HIGH                  |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "L2P_DATA<5>" OFFSET = OUT 6.5 ns AF | MAXDELAY    |     0.352ns|     6.148ns|       0|           0
-  TER COMP "P2L_CLKn" HIGH                  |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "L2P_DATA<15>" OFFSET = OUT 6.5 ns A | MAXDELAY    |     0.358ns|     6.142ns|       0|           0
-  FTER COMP "P2L_CLKp" HIGH                 |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "L2P_DATA<15>" OFFSET = OUT 6.5 ns A | MAXDELAY    |     0.358ns|     6.142ns|       0|           0
-  FTER COMP "P2L_CLKn" HIGH                 |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "L2P_DATA<10>" OFFSET = OUT 6.5 ns A | MAXDELAY    |     0.375ns|     6.125ns|       0|           0
-  FTER COMP "P2L_CLKn" HIGH                 |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "L2P_DATA<10>" OFFSET = OUT 6.5 ns A | MAXDELAY    |     0.375ns|     6.125ns|       0|           0
-  FTER COMP "P2L_CLKp" HIGH                 |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "P2L_DATA<9>" OFFSET = IN 1.2 ns VAL | SETUP       |     0.376ns|     0.824ns|       0|           0
-  ID 1.6 ns BEFORE COMP "P2L_CLKp"          | HOLD        |     0.308ns|            |       0|           0
-  HIGH                                      |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "P2L_DATA<9>" OFFSET = IN 1.2 ns VAL | SETUP       |     0.376ns|     0.824ns|       0|           0
-  ID 1.6 ns BEFORE COMP "P2L_CLKn"          | HOLD        |     0.308ns|            |       0|           0
-  HIGH                                      |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "L2P_VALID" OFFSET = OUT 6.5 ns AFTE | MAXDELAY    |     0.378ns|     6.122ns|       0|           0
-  R COMP "P2L_CLKn" HIGH                    |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "P2L_DATA<6>" OFFSET = IN 1.2 ns VAL | SETUP       |     0.382ns|     0.818ns|       0|           0
-  ID 1.6 ns BEFORE COMP "P2L_CLKn"          | HOLD        |     0.301ns|            |       0|           0
-  HIGH                                      |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "P2L_DATA<6>" OFFSET = IN 1.2 ns VAL | SETUP       |     0.382ns|     0.818ns|       0|           0
-  ID 1.6 ns BEFORE COMP "P2L_CLKp"          | HOLD        |     0.301ns|            |       0|           0
-  HIGH                                      |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "P2L_DATA<3>" OFFSET = IN 1.2 ns VAL | SETUP       |     0.383ns|     0.817ns|       0|           0
-  ID 1.6 ns BEFORE COMP "P2L_CLKn"          | HOLD        |     0.299ns|            |       0|           0
-  HIGH                                      |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "P2L_DATA<3>" OFFSET = IN 1.2 ns VAL | SETUP       |     0.383ns|     0.817ns|       0|           0
-  ID 1.6 ns BEFORE COMP "P2L_CLKp"          | HOLD        |     0.299ns|            |       0|           0
-  HIGH                                      |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "P2L_DATA<12>" OFFSET = IN 1.2 ns VA | SETUP       |     0.385ns|     0.815ns|       0|           0
-  LID 1.6 ns BEFORE COMP "P2L_CLKp"         | HOLD        |     0.295ns|            |       0|           0
-   HIGH                                     |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "P2L_DATA<12>" OFFSET = IN 1.2 ns VA | SETUP       |     0.386ns|     0.814ns|       0|           0
-  LID 1.6 ns BEFORE COMP "P2L_CLKn"         | HOLD        |     0.295ns|            |       0|           0
-   HIGH                                     |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "P2L_DATA<13>" OFFSET = IN 1.2 ns VA | SETUP       |     0.400ns|     0.800ns|       0|           0
-  LID 1.6 ns BEFORE COMP "P2L_CLKp"         | HOLD        |     0.275ns|            |       0|           0
-   HIGH                                     |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "P2L_DATA<13>" OFFSET = IN 1.2 ns VA | SETUP       |     0.401ns|     0.799ns|       0|           0
-  LID 1.6 ns BEFORE COMP "P2L_CLKn"         | HOLD        |     0.275ns|            |       0|           0
-   HIGH                                     |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "P2L_DATA<0>" OFFSET = IN 1.2 ns VAL | SETUP       |     0.408ns|     0.792ns|       0|           0
-  ID 1.6 ns BEFORE COMP "P2L_CLKn"          | HOLD        |     0.271ns|            |       0|           0
-  HIGH                                      |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "P2L_DATA<0>" OFFSET = IN 1.2 ns VAL | SETUP       |     0.408ns|     0.792ns|       0|           0
-  ID 1.6 ns BEFORE COMP "P2L_CLKp"          | HOLD        |     0.271ns|            |       0|           0
-  HIGH                                      |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "P2L_DATA<8>" OFFSET = IN 1.2 ns VAL | SETUP       |     0.415ns|     0.785ns|       0|           0
-  ID 1.6 ns BEFORE COMP "P2L_CLKp"          | HOLD        |     0.253ns|            |       0|           0
-  HIGH                                      |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "P2L_DATA<8>" OFFSET = IN 1.2 ns VAL | SETUP       |     0.416ns|     0.784ns|       0|           0
-  ID 1.6 ns BEFORE COMP "P2L_CLKn"          | HOLD        |     0.253ns|            |       0|           0
-  HIGH                                      |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "P2L_DATA<10>" OFFSET = IN 1.2 ns VA | SETUP       |     0.421ns|     0.779ns|       0|           0
-  LID 1.6 ns BEFORE COMP "P2L_CLKp"         | HOLD        |     0.246ns|            |       0|           0
-   HIGH                                     |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "P2L_DATA<15>" OFFSET = IN 1.2 ns VA | SETUP       |     0.421ns|     0.779ns|       0|           0
-  LID 1.6 ns BEFORE COMP "P2L_CLKp"         | HOLD        |     0.246ns|            |       0|           0
-   HIGH                                     |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "P2L_DATA<15>" OFFSET = IN 1.2 ns VA | SETUP       |     0.422ns|     0.778ns|       0|           0
-  LID 1.6 ns BEFORE COMP "P2L_CLKn"         | HOLD        |     0.246ns|            |       0|           0
-   HIGH                                     |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "P2L_DATA<10>" OFFSET = IN 1.2 ns VA | SETUP       |     0.422ns|     0.778ns|       0|           0
-  LID 1.6 ns BEFORE COMP "P2L_CLKn"         | HOLD        |     0.246ns|            |       0|           0
-   HIGH                                     |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "P2L_DATA<4>" OFFSET = IN 1.2 ns VAL | SETUP       |     0.423ns|     0.777ns|       0|           0
-  ID 1.6 ns BEFORE COMP "P2L_CLKp"          | HOLD        |     0.252ns|            |       0|           0
-  HIGH                                      |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "P2L_DATA<4>" OFFSET = IN 1.2 ns VAL | SETUP       |     0.423ns|     0.777ns|       0|           0
-  ID 1.6 ns BEFORE COMP "P2L_CLKn"          | HOLD        |     0.252ns|            |       0|           0
-  HIGH                                      |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "P2L_DATA<11>" OFFSET = IN 1.2 ns VA | SETUP       |     0.425ns|     0.775ns|       0|           0
-  LID 1.6 ns BEFORE COMP "P2L_CLKp"         | HOLD        |     0.242ns|            |       0|           0
-   HIGH                                     |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "P2L_DATA<14>" OFFSET = IN 1.2 ns VA | SETUP       |     0.425ns|     0.775ns|       0|           0
-  LID 1.6 ns BEFORE COMP "P2L_CLKp"         | HOLD        |     0.242ns|            |       0|           0
-   HIGH                                     |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "P2L_DATA<11>" OFFSET = IN 1.2 ns VA | SETUP       |     0.426ns|     0.774ns|       0|           0
-  LID 1.6 ns BEFORE COMP "P2L_CLKn"         | HOLD        |     0.242ns|            |       0|           0
-   HIGH                                     |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "P2L_DATA<14>" OFFSET = IN 1.2 ns VA | SETUP       |     0.426ns|     0.774ns|       0|           0
-  LID 1.6 ns BEFORE COMP "P2L_CLKn"         | HOLD        |     0.242ns|            |       0|           0
-   HIGH                                     |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "P2L_DATA<1>" OFFSET = IN 1.2 ns VAL | SETUP       |     0.435ns|     0.765ns|       0|           0
-  ID 1.6 ns BEFORE COMP "P2L_CLKp"          | HOLD        |     0.238ns|            |       0|           0
-  HIGH                                      |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "P2L_DATA<1>" OFFSET = IN 1.2 ns VAL | SETUP       |     0.435ns|     0.765ns|       0|           0
-  ID 1.6 ns BEFORE COMP "P2L_CLKn"          | HOLD        |     0.238ns|            |       0|           0
-  HIGH                                      |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "P2L_DATA<7>" OFFSET = IN 1.2 ns VAL | SETUP       |     0.435ns|     0.765ns|       0|           0
-  ID 1.6 ns BEFORE COMP "P2L_CLKp"          | HOLD        |     0.238ns|            |       0|           0
-  HIGH                                      |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "P2L_DATA<7>" OFFSET = IN 1.2 ns VAL | SETUP       |     0.435ns|     0.765ns|       0|           0
-  ID 1.6 ns BEFORE COMP "P2L_CLKn"          | HOLD        |     0.238ns|            |       0|           0
-  HIGH                                      |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "P2L_DATA<2>" OFFSET = IN 1.2 ns VAL | SETUP       |     0.439ns|     0.761ns|       0|           0
-  ID 1.6 ns BEFORE COMP "P2L_CLKp"          | HOLD        |     0.234ns|            |       0|           0
-  HIGH                                      |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "P2L_DATA<2>" OFFSET = IN 1.2 ns VAL | SETUP       |     0.439ns|     0.761ns|       0|           0
-  ID 1.6 ns BEFORE COMP "P2L_CLKn"          | HOLD        |     0.234ns|            |       0|           0
-  HIGH                                      |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "P2L_DATA<5>" OFFSET = IN 1.2 ns VAL | SETUP       |     0.439ns|     0.761ns|       0|           0
-  ID 1.6 ns BEFORE COMP "P2L_CLKp"          | HOLD        |     0.234ns|            |       0|           0
-  HIGH                                      |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "P2L_DATA<5>" OFFSET = IN 1.2 ns VAL | SETUP       |     0.439ns|     0.761ns|       0|           0
-  ID 1.6 ns BEFORE COMP "P2L_CLKn"          | HOLD        |     0.234ns|            |       0|           0
-  HIGH                                      |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  TS_p2l_clkp = PERIOD TIMEGRP "p2l_clkp_gr | MINPERIOD   |     0.500ns|     4.500ns|       0|           0
-  p" 5 ns HIGH 50%                          |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  COMP "P2L_DFRAME" OFFSET = IN 1.2 ns VALI | SETUP       |     1.176ns|     0.024ns|       0|           0
-  D 3 ns BEFORE COMP "P2L_CLKp" HIGH        | HOLD        |     1.198ns|            |       0|           0
-----------------------------------------------------------------------------------------------------------
-  COMP "P2L_VALID" OFFSET = IN 1.2 ns VALID | SETUP       |     1.176ns|     0.024ns|       0|           0
-   3 ns BEFORE COMP "P2L_CLKp" HIGH         | HOLD        |     1.198ns|            |       0|           0
-----------------------------------------------------------------------------------------------------------
-  NET "VC_RDY<0>_IBUF" MAXDELAY = 2 ns      | MAXDELAY    |     2.000ns|     0.000ns|       0|           0
-----------------------------------------------------------------------------------------------------------
-  NET "VC_RDY<1>_IBUF" MAXDELAY = 2 ns      | MAXDELAY    |     2.000ns|     0.000ns|       0|           0
-----------------------------------------------------------------------------------------------------------
-  TS_U_TO_J = MAXDELAY FROM TIMEGRP "U_CLK" | SETUP       |    10.054ns|     4.946ns|       0|           0
-   TO TIMEGRP "J_CLK" 15 ns                 | HOLD        |     1.952ns|            |       0|           0
-----------------------------------------------------------------------------------------------------------
-  TS_U_TO_U = MAXDELAY FROM TIMEGRP "U_CLK" | SETUP       |    13.697ns|     1.303ns|       0|           0
-   TO TIMEGRP "U_CLK" 15 ns                 | HOLD        |     0.955ns|            |       0|           0
-----------------------------------------------------------------------------------------------------------
-  TS_J_CLK = PERIOD TIMEGRP "J_CLK" 30 ns H | SETUP       |    16.381ns|    13.619ns|       0|           0
-  IGH 50%                                   | HOLD        |     0.602ns|            |       0|           0
-----------------------------------------------------------------------------------------------------------
-  PATH "TS_D_TO_J_path" TIG                 | SETUP       |         N/A|     6.193ns|     N/A|           0
-----------------------------------------------------------------------------------------------------------
-  PATH "TS_J_TO_D_path" TIG                 | SETUP       |         N/A|     6.457ns|     N/A|           0
-----------------------------------------------------------------------------------------------------------
-  NET "VC_RDY<0>_IBUF" MAXDELAY = 2 ns      | N/A         |         N/A|         N/A|     N/A|         N/A
-----------------------------------------------------------------------------------------------------------
-  NET "VC_RDY<1>_IBUF" MAXDELAY = 2 ns      | N/A         |         N/A|         N/A|     N/A|         N/A
-----------------------------------------------------------------------------------------------------------
-  NET "P_RD_D_RDY<0>/P_RD_D_RDY_0_IBUF" MAX | N/A         |         N/A|         N/A|     N/A|         N/A
-  DELAY = 2 ns                              |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  NET "P_RD_D_RDY<1>/P_RD_D_RDY_1_IBUF" MAX | N/A         |         N/A|         N/A|     N/A|         N/A
-  DELAY = 2 ns                              |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  NET "L2P_RDY/L2P_RDY_IBUF" MAXDELAY = 2 n | N/A         |         N/A|         N/A|     N/A|         N/A
-  s                                         |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  NET "L_WR_RDY<0>/L_WR_RDY_0_IBUF" MAXDELA | N/A         |         N/A|         N/A|     N/A|         N/A
-  Y = 2 ns                                  |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  NET "L_WR_RDY<0>/L_WR_RDY_0_IBUF" MAXDELA | N/A         |         N/A|         N/A|     N/A|         N/A
-  Y = 2 ns                                  |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  NET "L_WR_RDY<1>/L_WR_RDY_1_IBUF" MAXDELA | N/A         |         N/A|         N/A|     N/A|         N/A
-  Y = 2 ns                                  |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  NET "L_WR_RDY<1>/L_WR_RDY_1_IBUF" MAXDELA | N/A         |         N/A|         N/A|     N/A|         N/A
-  Y = 2 ns                                  |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-
-
-1 constraint not met.
-INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the 
-   constraint is not analyzed due to the following: No paths covered by this 
-   constraint; Other constraints intersect with this constraint; or This 
-   constraint was disabled by a Path Tracing Control. Please run the Timespec 
-   Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
-
-
-Generating Pad Report.
-
-All signals are completely routed.
-
-WARNING:Par:283 - There are 98 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
-
-Total REAL time to PAR completion: 7 mins 11 secs 
-Total CPU time to PAR completion: 7 mins 6 secs 
-
-Peak Memory Usage:  252 MB
-
-Placer: Placement generated during map.
-Routing: Completed - No errors found.
-Timing: Completed - 132 errors found.
-
-Number of error messages: 0
-Number of warning messages: 106
-Number of info messages: 1
-
-Writing design to file gw_wrapper.ncd
-
-
-
-PAR done!
diff --git a/hdl/gullwing/ise_project/gw_wrapper.syr b/hdl/gullwing/ise_project/gw_wrapper.syr
deleted file mode 100644
index bf68717caf0947bf6c45ef476fa9ebfb5798ce8b..0000000000000000000000000000000000000000
--- a/hdl/gullwing/ise_project/gw_wrapper.syr
+++ /dev/null
@@ -1,2066 +0,0 @@
-Release 12.2 - xst M.63c (lin)
-Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
---> 
-Parameter TMPDIR set to xst/projnav.tmp
-
-
-Total REAL time to Xst completion: 0.00 secs
-Total CPU time to Xst completion: 0.13 secs
- 
---> 
-Parameter xsthdpdir set to xst
-
-
-Total REAL time to Xst completion: 0.00 secs
-Total CPU time to Xst completion: 0.13 secs
- 
---> 
-Reading design: gw_wrapper.prj
-
-TABLE OF CONTENTS
-  1) Synthesis Options Summary
-  2) HDL Compilation
-  3) Design Hierarchy Analysis
-  4) HDL Analysis
-  5) HDL Synthesis
-     5.1) HDL Synthesis Report
-  6) Advanced HDL Synthesis
-     6.1) Advanced HDL Synthesis Report
-  7) Low Level Synthesis
-  8) Partition Report
-  9) Final Report
-	9.1) Device utilization summary
-	9.2) Partition Resource Summary
-	9.3) TIMING REPORT
-
-
-=========================================================================
-*                      Synthesis Options Summary                        *
-=========================================================================
----- Source Parameters
-Input File Name                    : "gw_wrapper.prj"
-Input Format                       : mixed
-Ignore Synthesis Constraint File   : NO
-
----- Target Parameters
-Output File Name                   : "gw_wrapper"
-Output Format                      : NGC
-Target Device                      : xc3s1400a-5-fg484
-
----- Source Options
-Top Module Name                    : gw_wrapper
-Automatic FSM Extraction           : YES
-FSM Encoding Algorithm             : Auto
-Safe Implementation                : No
-FSM Style                          : LUT
-RAM Extraction                     : Yes
-RAM Style                          : Auto
-ROM Extraction                     : Yes
-Mux Style                          : Auto
-Decoder Extraction                 : YES
-Priority Encoder Extraction        : Yes
-Shift Register Extraction          : YES
-Logical Shifter Extraction         : YES
-XOR Collapsing                     : YES
-ROM Style                          : Auto
-Mux Extraction                     : Yes
-Resource Sharing                   : YES
-Asynchronous To Synchronous        : NO
-Multiplier Style                   : Auto
-Automatic Register Balancing       : Yes
-
----- Target Options
-Add IO Buffers                     : YES
-Global Maximum Fanout              : 500
-Add Generic Clock Buffer(BUFG)     : 24
-Register Duplication               : YES
-Move First FlipFlop Stage          : YES
-Move Last FlipFlop Stage           : YES
-Slice Packing                      : YES
-Optimize Instantiated Primitives   : NO
-Use Clock Enable                   : Yes
-Use Synchronous Set                : Yes
-Use Synchronous Reset              : Yes
-Pack IO Registers into IOBs        : True
-Equivalent register Removal        : YES
-
----- General Options
-Optimization Goal                  : Speed
-Optimization Effort                : 2
-Keep Hierarchy                     : No
-Netlist Hierarchy                  : As_Optimized
-RTL Output                         : Yes
-Global Optimization                : AllClockNets
-Read Cores                         : YES
-Write Timing Constraints           : NO
-Cross Clock Analysis               : NO
-Hierarchy Separator                : /
-Bus Delimiter                      : <>
-Case Specifier                     : Maintain
-Slice Utilization Ratio            : 100
-BRAM Utilization Ratio             : 100
-Verilog 2001                       : YES
-Auto BRAM Packing                  : NO
-Slice Utilization Ratio Delta      : 5
-
----- Other Options
-Cores Search Directories           : {"../ip_cores"  }
-
-=========================================================================
-
-
-=========================================================================
-*                          HDL Compilation                              *
-=========================================================================
-Compiling vhdl file "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/gn4124_core_pkg.vhd" in Library work.
-Architecture gn4124_core_pkg of Entity gn4124_core_pkg is up to date.
-Compiling vhdl file "/home/mcattin/projects/GN4124_core/hdl/gullwing/ip_cores/fifo_64x512.vhd" in Library work.
-Architecture fifo_64x512_a of Entity fifo_64x512 is up to date.
-Compiling vhdl file "/home/mcattin/projects/GN4124_core/hdl/gullwing/ip_cores/fifo_32x512.vhd" in Library work.
-Architecture fifo_32x512_a of Entity fifo_32x512 is up to date.
-Compiling vhdl file "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd" in Library work.
-Architecture syn of Entity dma_controller_wb_slave is up to date.
-Compiling vhdl file "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/p2l_des.vhd" in Library work.
-Architecture rtl of Entity p2l_des is up to date.
-Compiling vhdl file "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/p2l_decode32.vhd" in Library work.
-Architecture rtl of Entity p2l_decode32 is up to date.
-Compiling vhdl file "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/wbmaster32.vhd" in Library work.
-Entity <wbmaster32> compiled.
-Entity <wbmaster32> (Architecture <behaviour>) compiled.
-Compiling vhdl file "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/dma_controller.vhd" in Library work.
-Entity <dma_controller> compiled.
-Entity <dma_controller> (Architecture <behaviour>) compiled.
-Compiling vhdl file "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/l2p_dma_master.vhd" in Library work.
-Entity <l2p_dma_master> compiled.
-Entity <l2p_dma_master> (Architecture <behaviour>) compiled.
-Compiling vhdl file "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/p2l_dma_master.vhd" in Library work.
-Entity <p2l_dma_master> compiled.
-Entity <p2l_dma_master> (Architecture <behaviour>) compiled.
-Compiling vhdl file "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/l2p_arbiter.vhd" in Library work.
-Entity <l2p_arbiter> compiled.
-Entity <l2p_arbiter> (Architecture <rtl>) compiled.
-Compiling vhdl file "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/l2p_ser.vhd" in Library work.
-Architecture rtl of Entity l2p_ser is up to date.
-Compiling vhdl file "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/gn4124_core.vhd" in Library work.
-Architecture rtl of Entity gn4124_core is up to date.
-Compiling vhdl file "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/dummy_stat_regs.vhd" in Library work.
-Architecture syn of Entity dummy_stat_regs_wb_slave is up to date.
-Compiling vhdl file "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/dummy_ctrl_regs.vhd" in Library work.
-Entity <dummy_ctrl_regs_wb_slave> compiled.
-Entity <dummy_ctrl_regs_wb_slave> (Architecture <syn>) compiled.
-Compiling vhdl file "/home/mcattin/projects/GN4124_core/hdl/gullwing/ip_cores/ram_2048x32.vhd" in Library work.
-Architecture ram_2048x32_a of Entity ram_2048x32 is up to date.
-Compiling vhdl file "/home/mcattin/projects/GN4124_core/hdl/gullwing/rtl/gullwing_wrapper.vhd" in Library work.
-Entity <gw_wrapper> compiled.
-Entity <gw_wrapper> (Architecture <rtl>) compiled.
-
-=========================================================================
-*                     Design Hierarchy Analysis                         *
-=========================================================================
-Analyzing hierarchy for entity <gw_wrapper> in library <work> (architecture <rtl>) with generics.
-	TAR_ADDR_WDTH = 13
-
-Analyzing hierarchy for entity <gn4124_core> in library <work> (architecture <rtl>) with generics.
-	g_BAR0_APERTURE = 20
-	g_CSR_WB_SLAVES_NB = 2
-	g_DMA_WB_ADDR_WIDTH = 26
-	g_DMA_WB_SLAVES_NB = 1
-	g_IS_SPARTAN6 = false
-
-Analyzing hierarchy for entity <dummy_stat_regs_wb_slave> in library <work> (architecture <syn>).
-
-Analyzing hierarchy for entity <dummy_ctrl_regs_wb_slave> in library <work> (architecture <syn>).
-
-Analyzing hierarchy for entity <p2l_des> in library <work> (architecture <rtl>) with generics.
-	g_IS_SPARTAN6 = false
-
-Analyzing hierarchy for entity <p2l_decode32> in library <work> (architecture <rtl>).
-
-Analyzing hierarchy for entity <wbmaster32> in library <work> (architecture <behaviour>) with generics.
-	g_BAR0_APERTURE = 20
-	g_WB_SLAVES_NB = 3
-
-Analyzing hierarchy for entity <dma_controller> in library <work> (architecture <behaviour>).
-
-Analyzing hierarchy for entity <l2p_dma_master> in library <work> (architecture <behaviour>) with generics.
-	g_BYTE_SWAP = false
-
-Analyzing hierarchy for entity <p2l_dma_master> in library <work> (architecture <behaviour>) with generics.
-	g_BYTE_SWAP = false
-
-Analyzing hierarchy for entity <l2p_arbiter> in library <work> (architecture <rtl>).
-
-Analyzing hierarchy for entity <l2p_ser> in library <work> (architecture <rtl>) with generics.
-	g_IS_SPARTAN6 = false
-
-Analyzing hierarchy for entity <dma_controller_wb_slave> in library <work> (architecture <syn>).
-
-
-=========================================================================
-*                            HDL Analysis                               *
-=========================================================================
-Analyzing generic Entity <gw_wrapper> in library <work> (Architecture <rtl>).
-	TAR_ADDR_WDTH = 13
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <cmp_sysclk_buf> in unit <gw_wrapper>.
-    Set user-defined property "DIFF_TERM =  FALSE" for instance <cmp_sysclk_buf> in unit <gw_wrapper>.
-    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <cmp_sysclk_buf> in unit <gw_wrapper>.
-    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <cmp_sysclk_buf> in unit <gw_wrapper>.
-    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <cmp_sysclk_buf> in unit <gw_wrapper>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <cmp_sysclk_buf> in unit <gw_wrapper>.
-WARNING:Xst:753 - "/home/mcattin/projects/GN4124_core/hdl/gullwing/rtl/gullwing_wrapper.vhd" line 482: Unconnected output port 'dummy_reg_1_wr_o' of component 'dummy_ctrl_regs_wb_slave'.
-WARNING:Xst:2211 - "/home/mcattin/projects/GN4124_core/hdl/gullwing/rtl/gullwing_wrapper.vhd" line 522: Instantiating black box module <ram_2048x32>.
-Entity <gw_wrapper> analyzed. Unit <gw_wrapper> generated.
-
-Analyzing generic Entity <gn4124_core> in library <work> (Architecture <rtl>).
-	g_BAR0_APERTURE = 20
-	g_CSR_WB_SLAVES_NB = 2
-	g_DMA_WB_ADDR_WIDTH = 26
-	g_DMA_WB_SLAVES_NB = 1
-	g_IS_SPARTAN6 = false
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <CLK_ibuf> in unit <gn4124_core>.
-    Set user-defined property "DIFF_TERM =  FALSE" for instance <CLK_ibuf> in unit <gn4124_core>.
-    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <CLK_ibuf> in unit <gn4124_core>.
-    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <CLK_ibuf> in unit <gn4124_core>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <CLK_ibuf> in unit <gn4124_core>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <CLKn_ibuf> in unit <gn4124_core>.
-    Set user-defined property "DIFF_TERM =  FALSE" for instance <CLKn_ibuf> in unit <gn4124_core>.
-    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <CLKn_ibuf> in unit <gn4124_core>.
-    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <CLKn_ibuf> in unit <gn4124_core>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <CLKn_ibuf> in unit <gn4124_core>.
-WARNING:Xst:752 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/gn4124_core.vhd" line 554: Unconnected input port 'p2l_dma_cyc_i' of component 'l2p_dma_master' is tied to default value.
-WARNING:Xst:752 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/gn4124_core.vhd" line 595: Unconnected input port 'l2p_dma_cyc_i' of component 'p2l_dma_master' is tied to default value.
-Entity <gn4124_core> analyzed. Unit <gn4124_core> generated.
-
-Analyzing generic Entity <p2l_des> in library <work> (Architecture <rtl>).
-	g_IS_SPARTAN6 = false
-Entity <p2l_des> analyzed. Unit <p2l_des> generated.
-
-Analyzing Entity <p2l_decode32> in library <work> (Architecture <rtl>).
-Entity <p2l_decode32> analyzed. Unit <p2l_decode32> generated.
-
-Analyzing generic Entity <wbmaster32> in library <work> (Architecture <behaviour>).
-	g_BAR0_APERTURE = 20
-	g_WB_SLAVES_NB = 3
-WARNING:Xst:753 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/wbmaster32.vhd" line 302: Unconnected output port 'full' of component 'fifo_64x512'.
-WARNING:Xst:753 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/wbmaster32.vhd" line 302: Unconnected output port 'valid' of component 'fifo_64x512'.
-WARNING:Xst:2211 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/wbmaster32.vhd" line 302: Instantiating black box module <fifo_64x512>.
-WARNING:Xst:753 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/wbmaster32.vhd" line 323: Unconnected output port 'full' of component 'fifo_32x512'.
-WARNING:Xst:753 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/wbmaster32.vhd" line 323: Unconnected output port 'valid' of component 'fifo_32x512'.
-WARNING:Xst:2211 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/wbmaster32.vhd" line 323: Instantiating black box module <fifo_32x512>.
-WARNING:Xst:790 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/wbmaster32.vhd" line 466: Index value(s) does not match array range, simulation mismatch.
-Entity <wbmaster32> analyzed. Unit <wbmaster32> generated.
-
-Analyzing Entity <dma_controller> in library <work> (Architecture <behaviour>).
-WARNING:Xst:753 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/dma_controller.vhd" line 204: Unconnected output port 'dma_stat_o' of component 'dma_controller_wb_slave'.
-WARNING:Xst:753 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/dma_controller.vhd" line 204: Unconnected output port 'dma_stat_load_o' of component 'dma_controller_wb_slave'.
-INFO:Xst:2679 - Register <dma_stat_reg<31>> in unit <dma_controller> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <dma_stat_reg<30>> in unit <dma_controller> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <dma_stat_reg<29>> in unit <dma_controller> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <dma_stat_reg<28>> in unit <dma_controller> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <dma_stat_reg<27>> in unit <dma_controller> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <dma_stat_reg<26>> in unit <dma_controller> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <dma_stat_reg<25>> in unit <dma_controller> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <dma_stat_reg<24>> in unit <dma_controller> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <dma_stat_reg<23>> in unit <dma_controller> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <dma_stat_reg<22>> in unit <dma_controller> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <dma_stat_reg<21>> in unit <dma_controller> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <dma_stat_reg<20>> in unit <dma_controller> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <dma_stat_reg<19>> in unit <dma_controller> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <dma_stat_reg<18>> in unit <dma_controller> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <dma_stat_reg<17>> in unit <dma_controller> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <dma_stat_reg<16>> in unit <dma_controller> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <dma_stat_reg<15>> in unit <dma_controller> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <dma_stat_reg<14>> in unit <dma_controller> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <dma_stat_reg<13>> in unit <dma_controller> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <dma_stat_reg<12>> in unit <dma_controller> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <dma_stat_reg<11>> in unit <dma_controller> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <dma_stat_reg<10>> in unit <dma_controller> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <dma_stat_reg<9>> in unit <dma_controller> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <dma_stat_reg<8>> in unit <dma_controller> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <dma_stat_reg<7>> in unit <dma_controller> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <dma_stat_reg<6>> in unit <dma_controller> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <dma_stat_reg<5>> in unit <dma_controller> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <dma_stat_reg<4>> in unit <dma_controller> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <dma_stat_reg<3>> in unit <dma_controller> has a constant value of 0 during circuit operation. The register is replaced by logic.
-Entity <dma_controller> analyzed. Unit <dma_controller> generated.
-
-Analyzing Entity <dma_controller_wb_slave> in library <work> (Architecture <syn>).
-INFO:Xst:2679 - Register <ack_sreg<9>> in unit <dma_controller_wb_slave> has a constant value of 0 during circuit operation. The register is replaced by logic.
-Entity <dma_controller_wb_slave> analyzed. Unit <dma_controller_wb_slave> generated.
-
-Analyzing generic Entity <l2p_dma_master> in library <work> (Architecture <behaviour>).
-	g_BYTE_SWAP = false
-WARNING:Xst:1610 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/l2p_dma_master.vhd" line 269: Width mismatch. <l2p_address_l> has a width of 32 bits but assigned expression is 43-bit wide.
-WARNING:Xst:753 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/l2p_dma_master.vhd" line 489: Unconnected output port 'full' of component 'fifo_32x512'.
-WARNING:Xst:2211 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/l2p_dma_master.vhd" line 489: Instantiating black box module <fifo_32x512>.
-WARNING:Xst:753 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/l2p_dma_master.vhd" line 505: Unconnected output port 'full' of component 'fifo_32x512'.
-WARNING:Xst:2211 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/l2p_dma_master.vhd" line 505: Instantiating black box module <fifo_32x512>.
-Entity <l2p_dma_master> analyzed. Unit <l2p_dma_master> generated.
-
-Analyzing generic Entity <p2l_dma_master> in library <work> (Architecture <behaviour>).
-	g_BYTE_SWAP = false
-WARNING:Xst:753 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/p2l_dma_master.vhd" line 493: Unconnected output port 'full' of component 'fifo_64x512'.
-WARNING:Xst:2211 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/p2l_dma_master.vhd" line 493: Instantiating black box module <fifo_64x512>.
-INFO:Xst:2679 - Register <to_wb_fifo_din<63>> in unit <p2l_dma_master> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <to_wb_fifo_din<62>> in unit <p2l_dma_master> has a constant value of 0 during circuit operation. The register is replaced by logic.
-Entity <p2l_dma_master> analyzed. Unit <p2l_dma_master> generated.
-
-Analyzing Entity <l2p_arbiter> in library <work> (Architecture <rtl>).
-Entity <l2p_arbiter> analyzed. Unit <l2p_arbiter> generated.
-
-Analyzing generic Entity <l2p_ser> in library <work> (Architecture <rtl>).
-	g_IS_SPARTAN6 = false
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <L2P_CLK_BUF> in unit <l2p_ser>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <L2P_CLK_BUF> in unit <l2p_ser>.
-    Set user-defined property "INIT =  0" for instance <gen_l2p_clk_ddr_ff.L2P_CLK_int> in unit <l2p_ser>.
-Entity <l2p_ser> analyzed. Unit <l2p_ser> generated.
-
-Analyzing Entity <dummy_stat_regs_wb_slave> in library <work> (Architecture <syn>).
-INFO:Xst:1561 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/dummy_stat_regs.vhd" line 110: Mux is complete : default of case is discarded
-INFO:Xst:2679 - Register <ack_sreg<9>> in unit <dummy_stat_regs_wb_slave> has a constant value of 0 during circuit operation. The register is replaced by logic.
-Entity <dummy_stat_regs_wb_slave> analyzed. Unit <dummy_stat_regs_wb_slave> generated.
-
-Analyzing Entity <dummy_ctrl_regs_wb_slave> in library <work> (Architecture <syn>).
-INFO:Xst:1561 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/dummy_ctrl_regs.vhd" line 155: Mux is complete : default of case is discarded
-INFO:Xst:2679 - Register <ack_sreg<9>> in unit <dummy_ctrl_regs_wb_slave> has a constant value of 0 during circuit operation. The register is replaced by logic.
-Entity <dummy_ctrl_regs_wb_slave> analyzed. Unit <dummy_ctrl_regs_wb_slave> generated.
-
-
-=========================================================================
-*                           HDL Synthesis                               *
-=========================================================================
-
-Performing bidirectional port resolution...
-INFO:Xst:2679 - Register <ack_sreg<8>> in unit <dma_controller_wb_slave> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <ack_sreg<8>> in unit <dummy_stat_regs_wb_slave> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <ack_sreg<8>> in unit <dummy_ctrl_regs_wb_slave> has a constant value of 0 during circuit operation. The register is replaced by logic.
-
-Synthesizing Unit <dummy_stat_regs_wb_slave>.
-    Related source file is "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/dummy_stat_regs.vhd".
-WARNING:Xst:646 - Signal <wrdata_reg> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <wr_int> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <rd_int> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <bwsel_reg> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <allzeros> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <allones> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-    Found 1-bit register for signal <ack_in_progress>.
-    Found 8-bit register for signal <ack_sreg<7:0>>.
-    Found 32-bit register for signal <rddata_reg>.
-    Found 32-bit 4-to-1 multiplexer for signal <rddata_reg$mux0000> created at line 82.
-    Summary:
-	inferred  41 D-type flip-flop(s).
-	inferred  32 Multiplexer(s).
-Unit <dummy_stat_regs_wb_slave> synthesized.
-
-
-Synthesizing Unit <dummy_ctrl_regs_wb_slave>.
-    Related source file is "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/dummy_ctrl_regs.vhd".
-WARNING:Xst:646 - Signal <wr_int> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <rd_int> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <bwsel_reg> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <allzeros> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <allones> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-    Found 1-bit register for signal <dummy_reg_1_wr_o>.
-    Found 1-bit register for signal <ack_in_progress>.
-    Found 8-bit register for signal <ack_sreg<7:0>>.
-    Found 32-bit register for signal <dummy_reg_2_int>.
-    Found 32-bit register for signal <dummy_reg_3_int>.
-    Found 32-bit register for signal <dummy_reg_led_int>.
-    Found 32-bit register for signal <rddata_reg>.
-    Found 1-bit 4-to-1 multiplexer for signal <rddata_reg_0$mux0000> created at line 92.
-    Found 1-bit 4-to-1 multiplexer for signal <rddata_reg_1$mux0000> created at line 92.
-    Found 1-bit 4-to-1 multiplexer for signal <rddata_reg_10$mux0000> created at line 92.
-    Found 1-bit 4-to-1 multiplexer for signal <rddata_reg_11$mux0000> created at line 92.
-    Found 1-bit 4-to-1 multiplexer for signal <rddata_reg_12$mux0000> created at line 92.
-    Found 1-bit 4-to-1 multiplexer for signal <rddata_reg_13$mux0000> created at line 92.
-    Found 1-bit 4-to-1 multiplexer for signal <rddata_reg_14$mux0000> created at line 92.
-    Found 1-bit 4-to-1 multiplexer for signal <rddata_reg_15$mux0000> created at line 92.
-    Found 1-bit 4-to-1 multiplexer for signal <rddata_reg_16$mux0000> created at line 92.
-    Found 1-bit 4-to-1 multiplexer for signal <rddata_reg_17$mux0000> created at line 92.
-    Found 1-bit 4-to-1 multiplexer for signal <rddata_reg_18$mux0000> created at line 92.
-    Found 1-bit 4-to-1 multiplexer for signal <rddata_reg_19$mux0000> created at line 92.
-    Found 1-bit 4-to-1 multiplexer for signal <rddata_reg_2$mux0000> created at line 92.
-    Found 1-bit 4-to-1 multiplexer for signal <rddata_reg_20$mux0000> created at line 92.
-    Found 1-bit 4-to-1 multiplexer for signal <rddata_reg_21$mux0000> created at line 92.
-    Found 1-bit 4-to-1 multiplexer for signal <rddata_reg_22$mux0000> created at line 92.
-    Found 1-bit 4-to-1 multiplexer for signal <rddata_reg_23$mux0000> created at line 92.
-    Found 1-bit 4-to-1 multiplexer for signal <rddata_reg_24$mux0000> created at line 92.
-    Found 1-bit 4-to-1 multiplexer for signal <rddata_reg_25$mux0000> created at line 92.
-    Found 1-bit 4-to-1 multiplexer for signal <rddata_reg_26$mux0000> created at line 92.
-    Found 1-bit 4-to-1 multiplexer for signal <rddata_reg_27$mux0000> created at line 92.
-    Found 1-bit 4-to-1 multiplexer for signal <rddata_reg_28$mux0000> created at line 92.
-    Found 1-bit 4-to-1 multiplexer for signal <rddata_reg_29$mux0000> created at line 92.
-    Found 1-bit 4-to-1 multiplexer for signal <rddata_reg_3$mux0000> created at line 92.
-    Found 1-bit 4-to-1 multiplexer for signal <rddata_reg_30$mux0000> created at line 92.
-    Found 1-bit 4-to-1 multiplexer for signal <rddata_reg_31$mux0000> created at line 92.
-    Found 1-bit 4-to-1 multiplexer for signal <rddata_reg_4$mux0000> created at line 92.
-    Found 1-bit 4-to-1 multiplexer for signal <rddata_reg_5$mux0000> created at line 92.
-    Found 1-bit 4-to-1 multiplexer for signal <rddata_reg_6$mux0000> created at line 92.
-    Found 1-bit 4-to-1 multiplexer for signal <rddata_reg_7$mux0000> created at line 92.
-    Found 1-bit 4-to-1 multiplexer for signal <rddata_reg_8$mux0000> created at line 92.
-    Found 1-bit 4-to-1 multiplexer for signal <rddata_reg_9$mux0000> created at line 92.
-    Summary:
-	inferred 138 D-type flip-flop(s).
-	inferred  32 Multiplexer(s).
-Unit <dummy_ctrl_regs_wb_slave> synthesized.
-
-
-Synthesizing Unit <p2l_decode32>.
-    Related source file is "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/p2l_decode32.vhd".
-WARNING:Xst:1780 - Signal <p2l_packet_start_d> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <p2l_d_first> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-    Found 1-bit register for signal <des_p2l_dframe_d>.
-    Found 1-bit register for signal <des_p2l_valid_d>.
-    Found 1-bit register for signal <master_cpld>.
-    Found 1-bit register for signal <master_cpln>.
-    Found 32-bit register for signal <p2l_addr>.
-    Found 30-bit adder for signal <p2l_addr_31_2$add0000> created at line 254.
-    Found 1-bit register for signal <p2l_addr_cycle>.
-    Found 1-bit register for signal <p2l_addr_start>.
-    Found 4-bit register for signal <p2l_be>.
-    Found 32-bit register for signal <p2l_d>.
-    Found 1-bit register for signal <p2l_d_last>.
-    Found 1-bit register for signal <p2l_d_valid>.
-    Found 1-bit register for signal <p2l_data_cycle>.
-    Found 2-bit register for signal <p2l_hdr_cid>.
-    Found 4-bit register for signal <p2l_hdr_fbe>.
-    Found 1-bit register for signal <p2l_hdr_last>.
-    Found 4-bit register for signal <p2l_hdr_lbe>.
-    Found 10-bit register for signal <p2l_hdr_length>.
-    Found 2-bit register for signal <p2l_hdr_stat>.
-    Found 1-bit register for signal <p2l_hdr_strobe>.
-    Found 1-bit register for signal <target_mrd>.
-    Found 1-bit register for signal <target_mwr>.
-    Summary:
-	inferred 103 D-type flip-flop(s).
-	inferred   1 Adder/Subtractor(s).
-Unit <p2l_decode32> synthesized.
-
-
-Synthesizing Unit <l2p_arbiter>.
-    Related source file is "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/l2p_arbiter.vhd".
-    Found 1-bit register for signal <arb_ser_dframe_o>.
-    Found 1-bit register for signal <arb_ser_valid_o>.
-    Found 32-bit register for signal <arb_ser_data_o>.
-    Found 1-bit register for signal <arb_ldm_gnt>.
-    Found 1-bit register for signal <arb_pdm_gnt>.
-    Found 32-bit register for signal <arb_ser_data_t>.
-    Found 1-bit register for signal <arb_ser_dframe_t>.
-    Found 1-bit register for signal <arb_ser_valid_t>.
-    Found 1-bit register for signal <arb_wbm_gnt>.
-    Summary:
-	inferred  71 D-type flip-flop(s).
-Unit <l2p_arbiter> synthesized.
-
-
-Synthesizing Unit <dma_controller_wb_slave>.
-    Related source file is "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd".
-WARNING:Xst:646 - Signal <wr_int> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <rd_int> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <bwsel_reg> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <bus_clock_int> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <allzeros> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <allones> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-    Found 32-bit register for signal <dma_attrib_o>.
-    Found 1-bit register for signal <dma_nexth_load_o>.
-    Found 32-bit register for signal <dma_ctrl_o>.
-    Found 32-bit register for signal <dma_stat_o>.
-    Found 1-bit register for signal <dma_nextl_load_o>.
-    Found 32-bit register for signal <dma_hstarth_o>.
-    Found 1-bit register for signal <dma_hstarth_load_o>.
-    Found 1-bit register for signal <dma_stat_load_o>.
-    Found 32-bit register for signal <dma_nextl_o>.
-    Found 1-bit register for signal <dma_attrib_load_o>.
-    Found 1-bit register for signal <dma_hstartl_load_o>.
-    Found 1-bit register for signal <dma_cstart_load_o>.
-    Found 32-bit register for signal <dma_cstart_o>.
-    Found 1-bit register for signal <dma_len_load_o>.
-    Found 32-bit register for signal <dma_len_o>.
-    Found 32-bit register for signal <dma_hstartl_o>.
-    Found 32-bit register for signal <dma_nexth_o>.
-    Found 1-bit register for signal <dma_ctrl_load_o>.
-    Found 1-bit register for signal <ack_in_progress>.
-    Found 8-bit register for signal <ack_sreg<7:0>>.
-    Found 32-bit register for signal <dma_attrib_int_read>.
-    Found 32-bit register for signal <dma_attrib_int_write>.
-    Found 1-bit register for signal <dma_attrib_lw>.
-    Found 1-bit register for signal <dma_attrib_lw_delay>.
-    Found 1-bit register for signal <dma_attrib_lw_read_in_progress>.
-    Found 1-bit register for signal <dma_attrib_lw_s0>.
-    Found 1-bit register for signal <dma_attrib_lw_s1>.
-    Found 1-bit register for signal <dma_attrib_lw_s2>.
-    Found 1-bit register for signal <dma_attrib_rwsel>.
-    Found 32-bit register for signal <dma_cstart_int_read>.
-    Found 32-bit register for signal <dma_cstart_int_write>.
-    Found 1-bit register for signal <dma_cstart_lw>.
-    Found 1-bit register for signal <dma_cstart_lw_delay>.
-    Found 1-bit register for signal <dma_cstart_lw_read_in_progress>.
-    Found 1-bit register for signal <dma_cstart_lw_s0>.
-    Found 1-bit register for signal <dma_cstart_lw_s1>.
-    Found 1-bit register for signal <dma_cstart_lw_s2>.
-    Found 1-bit register for signal <dma_cstart_rwsel>.
-    Found 32-bit register for signal <dma_ctrl_int_read>.
-    Found 32-bit register for signal <dma_ctrl_int_write>.
-    Found 1-bit register for signal <dma_ctrl_lw>.
-    Found 1-bit register for signal <dma_ctrl_lw_delay>.
-    Found 1-bit register for signal <dma_ctrl_lw_read_in_progress>.
-    Found 1-bit register for signal <dma_ctrl_lw_s0>.
-    Found 1-bit register for signal <dma_ctrl_lw_s1>.
-    Found 1-bit register for signal <dma_ctrl_lw_s2>.
-    Found 1-bit register for signal <dma_ctrl_rwsel>.
-    Found 32-bit register for signal <dma_hstarth_int_read>.
-    Found 32-bit register for signal <dma_hstarth_int_write>.
-    Found 1-bit register for signal <dma_hstarth_lw>.
-    Found 1-bit register for signal <dma_hstarth_lw_delay>.
-    Found 1-bit register for signal <dma_hstarth_lw_read_in_progress>.
-    Found 1-bit register for signal <dma_hstarth_lw_s0>.
-    Found 1-bit register for signal <dma_hstarth_lw_s1>.
-    Found 1-bit register for signal <dma_hstarth_lw_s2>.
-    Found 1-bit register for signal <dma_hstarth_rwsel>.
-    Found 32-bit register for signal <dma_hstartl_int_read>.
-    Found 32-bit register for signal <dma_hstartl_int_write>.
-    Found 1-bit register for signal <dma_hstartl_lw>.
-    Found 1-bit register for signal <dma_hstartl_lw_delay>.
-    Found 1-bit register for signal <dma_hstartl_lw_read_in_progress>.
-    Found 1-bit register for signal <dma_hstartl_lw_s0>.
-    Found 1-bit register for signal <dma_hstartl_lw_s1>.
-    Found 1-bit register for signal <dma_hstartl_lw_s2>.
-    Found 1-bit register for signal <dma_hstartl_rwsel>.
-    Found 32-bit register for signal <dma_len_int_read>.
-    Found 32-bit register for signal <dma_len_int_write>.
-    Found 1-bit register for signal <dma_len_lw>.
-    Found 1-bit register for signal <dma_len_lw_delay>.
-    Found 1-bit register for signal <dma_len_lw_read_in_progress>.
-    Found 1-bit register for signal <dma_len_lw_s0>.
-    Found 1-bit register for signal <dma_len_lw_s1>.
-    Found 1-bit register for signal <dma_len_lw_s2>.
-    Found 1-bit register for signal <dma_len_rwsel>.
-    Found 32-bit register for signal <dma_nexth_int_read>.
-    Found 32-bit register for signal <dma_nexth_int_write>.
-    Found 1-bit register for signal <dma_nexth_lw>.
-    Found 1-bit register for signal <dma_nexth_lw_delay>.
-    Found 1-bit register for signal <dma_nexth_lw_read_in_progress>.
-    Found 1-bit register for signal <dma_nexth_lw_s0>.
-    Found 1-bit register for signal <dma_nexth_lw_s1>.
-    Found 1-bit register for signal <dma_nexth_lw_s2>.
-    Found 1-bit register for signal <dma_nexth_rwsel>.
-    Found 32-bit register for signal <dma_nextl_int_read>.
-    Found 32-bit register for signal <dma_nextl_int_write>.
-    Found 1-bit register for signal <dma_nextl_lw>.
-    Found 1-bit register for signal <dma_nextl_lw_delay>.
-    Found 1-bit register for signal <dma_nextl_lw_read_in_progress>.
-    Found 1-bit register for signal <dma_nextl_lw_s0>.
-    Found 1-bit register for signal <dma_nextl_lw_s1>.
-    Found 1-bit register for signal <dma_nextl_lw_s2>.
-    Found 1-bit register for signal <dma_nextl_rwsel>.
-    Found 32-bit register for signal <dma_stat_int_read>.
-    Found 32-bit register for signal <dma_stat_int_write>.
-    Found 1-bit register for signal <dma_stat_lw>.
-    Found 1-bit register for signal <dma_stat_lw_delay>.
-    Found 1-bit register for signal <dma_stat_lw_read_in_progress>.
-    Found 1-bit register for signal <dma_stat_lw_s0>.
-    Found 1-bit register for signal <dma_stat_lw_s1>.
-    Found 1-bit register for signal <dma_stat_lw_s2>.
-    Found 1-bit register for signal <dma_stat_rwsel>.
-    Found 32-bit register for signal <rddata_reg>.
-    Summary:
-	inferred 977 D-type flip-flop(s).
-Unit <dma_controller_wb_slave> synthesized.
-
-
-Synthesizing Unit <p2l_des>.
-    Related source file is "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/p2l_des.vhd".
-WARNING:Xst:646 - Signal <p2l_valid_n> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <p2l_dframe_n> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <p2l_data_d> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-    Found 1-bit register for signal <p2l_dframe_o>.
-    Found 32-bit register for signal <p2l_data_o>.
-    Found 1-bit register for signal <p2l_valid_o>.
-    Found 16-bit register for signal <p2l_data_sdr_l>.
-    Summary:
-	inferred  50 D-type flip-flop(s).
-Unit <p2l_des> synthesized.
-
-
-Synthesizing Unit <wbmaster32>.
-    Related source file is "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/wbmaster32.vhd".
-WARNING:Xst:647 - Input <pd_wbm_addr_i<1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <pd_wbm_hdr_length_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <pd_wbm_data_last_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <pd_wbm_be_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:646 - Signal <wb_adr_t<30:18>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <s_wb_periph_select<3>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <from_wb_fifo_full> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-    Found finite state machine <FSM_0> for signal <wishbone_current_state>.
-    -----------------------------------------------------------------------
-    | States             | 4                                              |
-    | Transitions        | 6                                              |
-    | Inputs             | 2                                              |
-    | Outputs            | 5                                              |
-    | Clock              | wb_clk_i                  (rising_edge)        |
-    | Reset              | rst_n_i                   (negative)           |
-    | Reset type         | asynchronous                                   |
-    | Reset State        | wb_idle                                        |
-    | Power Up State     | wb_idle                                        |
-    | Encoding           | automatic                                      |
-    | Implementation     | LUT                                            |
-    -----------------------------------------------------------------------
-    Found finite state machine <FSM_1> for signal <l2p_read_cpl_current_state>.
-    -----------------------------------------------------------------------
-    | States             | 3                                              |
-    | Transitions        | 6                                              |
-    | Inputs             | 3                                              |
-    | Outputs            | 3                                              |
-    | Clock              | clk_i                     (rising_edge)        |
-    | Reset              | rst_n_i                   (negative)           |
-    | Reset type         | asynchronous                                   |
-    | Reset State        | l2p_idle                                       |
-    | Power Up State     | l2p_idle                                       |
-    | Encoding           | automatic                                      |
-    | Implementation     | LUT                                            |
-    -----------------------------------------------------------------------
-    Found 1-bit register for signal <wbm_arb_req_o>.
-    Found 32-bit register for signal <wbm_arb_data_o>.
-    Found 1-bit register for signal <wbm_arb_valid_o>.
-    Found 1-bit register for signal <wbm_arb_dframe_o>.
-    Found 32-bit register for signal <from_wb_fifo_din>.
-    Found 1-bit register for signal <from_wb_fifo_rd>.
-    Found 1-bit register for signal <from_wb_fifo_wr>.
-    Found 2-bit register for signal <p2l_cid>.
-    Found 2-bit comparator less for signal <s_wb_dat_i_muxed$cmp_lt0000> created at line 475.
-    Found 64-bit register for signal <to_wb_fifo_din>.
-    Found 1-bit register for signal <to_wb_fifo_rd>.
-    Found 1-bit register for signal <to_wb_fifo_wr>.
-    Found 2-bit adder for signal <v_index$addsub0000> created at line 439.
-    Found 1-bit register for signal <wb_ack_t>.
-    Found 31-bit register for signal <wb_adr_t>.
-    Found 1-bit register for signal <wb_cyc_t>.
-    Found 32-bit register for signal <wb_dat_i_t>.
-    Found 32-bit register for signal <wb_dat_o_t>.
-    Found 2-bit register for signal <wb_periph_addr>.
-    Found 4-bit register for signal <wb_sel_t>.
-    Found 1-bit register for signal <wb_stb_t>.
-    Found 1-bit register for signal <wb_we_t>.
-    Summary:
-	inferred   2 Finite State Machine(s).
-	inferred 242 D-type flip-flop(s).
-	inferred   1 Adder/Subtractor(s).
-	inferred   1 Comparator(s).
-Unit <wbmaster32> synthesized.
-
-
-Synthesizing Unit <dma_controller>.
-    Related source file is "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/dma_controller.vhd".
-WARNING:Xst:1780 - Signal <dma_stat_load> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <dma_stat> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-    Found finite state machine <FSM_2> for signal <dma_ctrl_current_state>.
-    -----------------------------------------------------------------------
-    | States             | 7                                              |
-    | Transitions        | 18                                             |
-    | Inputs             | 7                                              |
-    | Outputs            | 7                                              |
-    | Clock              | clk_i                     (rising_edge)        |
-    | Reset              | rst_n_i                   (negative)           |
-    | Reset type         | asynchronous                                   |
-    | Reset State        | dma_idle                                       |
-    | Power Up State     | dma_idle                                       |
-    | Encoding           | automatic                                      |
-    | Implementation     | LUT                                            |
-    -----------------------------------------------------------------------
-    Found 1-bit register for signal <dma_ctrl_start_l2p_o>.
-    Found 1-bit register for signal <dma_ctrl_abort_o>.
-    Found 1-bit register for signal <dma_ctrl_start_p2l_o>.
-    Found 32-bit register for signal <dma_ctrl_carrier_addr_o>.
-    Found 32-bit register for signal <dma_ctrl_host_addr_l_o>.
-    Found 32-bit register for signal <dma_ctrl_len_o>.
-    Found 1-bit register for signal <dma_ctrl_start_next_o>.
-    Found 32-bit register for signal <dma_ctrl_host_addr_h_o>.
-    Found 32-bit register for signal <dma_attrib_reg>.
-    Found 32-bit register for signal <dma_cstart_reg>.
-    Found 32-bit register for signal <dma_ctrl_reg>.
-    Found 1-bit register for signal <dma_done_irq>.
-    Found 1-bit register for signal <dma_error_irq>.
-    Found 32-bit register for signal <dma_hstarth_reg>.
-    Found 32-bit register for signal <dma_hstartl_reg>.
-    Found 32-bit register for signal <dma_len_reg>.
-    Found 32-bit register for signal <dma_nexth_reg>.
-    Found 32-bit register for signal <dma_nextl_reg>.
-    Found 3-bit register for signal <dma_stat_reg<2:0>>.
-    Found 3-bit register for signal <dma_status>.
-    Summary:
-	inferred   1 Finite State Machine(s).
-	inferred 396 D-type flip-flop(s).
-Unit <dma_controller> synthesized.
-
-
-Synthesizing Unit <l2p_dma_master>.
-    Related source file is "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/l2p_dma_master.vhd".
-WARNING:Xst:647 - Input <dma_ctrl_len_i<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <dma_ctrl_target_addr_i<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:646 - Signal <l2p_byte_swap> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-    Found finite state machine <FSM_3> for signal <l2p_dma_current_state>.
-    -----------------------------------------------------------------------
-    | States             | 8                                              |
-    | Transitions        | 23                                             |
-    | Inputs             | 9                                              |
-    | Outputs            | 12                                             |
-    | Clock              | clk_i                     (rising_edge)        |
-    | Reset              | rst_n_i                   (negative)           |
-    | Reset type         | asynchronous                                   |
-    | Reset State        | l2p_idle                                       |
-    | Power Up State     | l2p_idle                                       |
-    | Encoding           | automatic                                      |
-    | Implementation     | LUT                                            |
-    -----------------------------------------------------------------------
-    Found 1-bit register for signal <ldm_arb_dframe_o>.
-    Found 32-bit register for signal <l2p_dma_adr_o>.
-    Found 4-bit register for signal <l2p_dma_sel_o>.
-    Found 32-bit register for signal <ldm_arb_data_o>.
-    Found 1-bit register for signal <l2p_edb_o>.
-    Found 1-bit register for signal <ldm_arb_req_o>.
-    Found 1-bit register for signal <dma_ctrl_error_o>.
-    Found 1-bit register for signal <ldm_arb_valid_o>.
-    Found 1-bit register for signal <dma_ctrl_done_o>.
-    Found 32-bit register for signal <addr_fifo_din>.
-    Found 1-bit register for signal <addr_fifo_wr>.
-    Found 1-bit register for signal <data_fifo_rd>.
-    Found 30-bit down counter for signal <dma_length_cnt>.
-    Found 1-bit register for signal <l2p_64b_address>.
-    Found 32-bit register for signal <l2p_address_h>.
-    Found 32-bit register for signal <l2p_address_l>.
-    Found 32-bit adder for signal <l2p_address_l$addsub0000> created at line 269.
-    Found 11-bit register for signal <l2p_data_cnt>.
-    Found 11-bit subtractor for signal <l2p_data_cnt$addsub0000> created at line 266.
-    Found 30-bit comparator greater for signal <l2p_data_cnt$cmp_gt0000> created at line 271.
-    Found 30-bit comparator greater for signal <l2p_dma_current_state$cmp_gt0000> created at line 458.
-    Found 11-bit comparator lessequal for signal <l2p_dma_current_state$cmp_le0000> created at line 377.
-    Found 11-bit comparator lessequal for signal <l2p_dma_current_state$cmp_le0001> created at line 408.
-    Found 1-bit register for signal <l2p_dma_cyc_t>.
-    Found 32-bit subtractor for signal <l2p_dma_cyc_t$addsub0000> created at line 564.
-    Found 32-bit comparator equal for signal <l2p_dma_cyc_t$cmp_eq0000> created at line 564.
-    Found 1-bit register for signal <l2p_dma_stb_t>.
-    Found 1-bit register for signal <l2p_last_packet>.
-    Found 30-bit register for signal <l2p_len_cnt>.
-    Found 30-bit subtractor for signal <l2p_len_cnt$addsub0000> created at line 261.
-    Found 10-bit register for signal <l2p_len_header>.
-    Found 30-bit up counter for signal <target_addr_cnt>.
-    Found 32-bit up counter for signal <wb_ack_cnt>.
-    Found 32-bit up counter for signal <wb_read_cnt>.
-    Summary:
-	inferred   1 Finite State Machine(s).
-	inferred   4 Counter(s).
-	inferred 227 D-type flip-flop(s).
-	inferred   4 Adder/Subtractor(s).
-	inferred   5 Comparator(s).
-Unit <l2p_dma_master> synthesized.
-
-
-Synthesizing Unit <p2l_dma_master>.
-    Related source file is "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/p2l_dma_master.vhd".
-WARNING:Xst:647 - Input <p2l_dma_dat_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <pd_pdm_hdr_length_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <pd_pdm_be_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <pd_pdm_hdr_cid_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <dma_ctrl_carrier_addr_i<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <dma_ctrl_len_i<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <pd_pdm_hdr_start_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:646 - Signal <to_wb_fifo_dout<63:62>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <to_wb_fifo_byte_swap> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <dma_length_error> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-    Found finite state machine <FSM_4> for signal <p2l_dma_current_state>.
-    -----------------------------------------------------------------------
-    | States             | 5                                              |
-    | Transitions        | 17                                             |
-    | Inputs             | 10                                             |
-    | Outputs            | 7                                              |
-    | Clock              | clk_i                     (rising_edge)        |
-    | Reset              | rst_n_i                   (negative)           |
-    | Reset type         | asynchronous                                   |
-    | Reset State        | p2l_idle                                       |
-    | Power Up State     | p2l_idle                                       |
-    | Encoding           | automatic                                      |
-    | Implementation     | LUT                                            |
-    -----------------------------------------------------------------------
-    Found 32-bit register for signal <p2l_dma_adr_o>.
-    Found 32-bit register for signal <p2l_dma_dat_o>.
-    Found 1-bit register for signal <pdm_arb_req_o>.
-    Found 4-bit register for signal <p2l_dma_sel_o>.
-    Found 32-bit register for signal <next_item_next_l_o>.
-    Found 1-bit register for signal <rx_error_o>.
-    Found 32-bit register for signal <next_item_len_o>.
-    Found 32-bit register for signal <next_item_attrib_o>.
-    Found 32-bit register for signal <next_item_host_addr_l_o>.
-    Found 1-bit register for signal <next_item_valid_o>.
-    Found 1-bit register for signal <pdm_arb_dframe_o>.
-    Found 1-bit register for signal <pdm_arb_valid_o>.
-    Found 32-bit register for signal <next_item_next_h_o>.
-    Found 32-bit register for signal <pdm_arb_data_o>.
-    Found 32-bit register for signal <next_item_carrier_addr_o>.
-    Found 1-bit register for signal <dma_ctrl_done_o>.
-    Found 32-bit register for signal <next_item_host_addr_h_o>.
-    Found 1-bit register for signal <completion_error>.
-    Found 1-bit register for signal <dma_busy_error>.
-    Found 1-bit register for signal <dma_ctrl_done_t>.
-    Found 1-bit register for signal <is_next_item>.
-    Found 1-bit register for signal <l2p_64b_address>.
-    Found 32-bit register for signal <l2p_address_h>.
-    Found 32-bit register for signal <l2p_address_l>.
-    Found 1-bit register for signal <l2p_last_packet>.
-    Found 30-bit register for signal <l2p_len_cnt>.
-    Found 30-bit subtractor for signal <l2p_len_cnt$addsub0000> created at line 248.
-    Found 10-bit register for signal <l2p_len_header>.
-    Found 30-bit comparator greater for signal <l2p_len_header$cmp_gt0000> created at line 233.
-    Found 11-bit down counter for signal <p2l_data_cnt>.
-    Found 11-bit comparator lessequal for signal <p2l_dma_current_state$cmp_le0000> created at line 336.
-    Found 1-bit register for signal <p2l_dma_cyc_t>.
-    Found 32-bit subtractor for signal <p2l_dma_cyc_t$addsub0000> created at line 549.
-    Found 32-bit comparator equal for signal <p2l_dma_cyc_t$cmp_eq0000> created at line 549.
-    Found 1-bit register for signal <p2l_dma_stb_t>.
-    Found 1-bit register for signal <rx_error_t>.
-    Found 30-bit up counter for signal <target_addr_cnt>.
-    Found 62-bit register for signal <to_wb_fifo_din<61:0>>.
-    Found 1-bit register for signal <to_wb_fifo_wr>.
-    Found 32-bit up counter for signal <wb_ack_cnt>.
-    Found 32-bit up counter for signal <wb_write_cnt>.
-    Summary:
-	inferred   1 Finite State Machine(s).
-	inferred   4 Counter(s).
-	inferred 506 D-type flip-flop(s).
-	inferred   2 Adder/Subtractor(s).
-	inferred   3 Comparator(s).
-Unit <p2l_dma_master> synthesized.
-
-
-Synthesizing Unit <l2p_ser>.
-    Related source file is "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/l2p_ser.vhd".
-    Found 1-bit register for signal <l2p_valid_o>.
-    Found 1-bit register for signal <l2p_dframe_o>.
-    Found 32-bit register for signal <data_d>.
-    Found 1-bit register for signal <dframe_d>.
-    Found 1-bit register for signal <valid_d>.
-    Summary:
-	inferred  36 D-type flip-flop(s).
-Unit <l2p_ser> synthesized.
-
-
-Synthesizing Unit <gn4124_core>.
-    Related source file is "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/gn4124_core.vhd".
-WARNING:Xst:647 - Input <p_wr_req_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <vc_rdy_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <tx_error_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:1780 - Signal <p_wr_rdy> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <p2l_hdr_stat> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <p2l_hdr_last> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-    Found 32-bit 4-to-1 multiplexer for signal <dma_adr_o>.
-    Found 32-bit 4-to-1 multiplexer for signal <dma_dat_o>.
-    Found 1-bit register for signal <l2p_rdy>.
-    Found 1-bit register for signal <l2p_rdy_t>.
-    Found 2-bit register for signal <l_wr_rdy>.
-    Found 2-bit register for signal <l_wr_rdy_t>.
-    Found 2-bit register for signal <p_rd_d_rdy>.
-    Found 2-bit register for signal <p_rd_d_rdy_t>.
-    Found 1-bit register for signal <rst_reg>.
-    Summary:
-	inferred  11 D-type flip-flop(s).
-	inferred  64 Multiplexer(s).
-Unit <gn4124_core> synthesized.
-
-
-Synthesizing Unit <gw_wrapper>.
-    Related source file is "/home/mcattin/projects/GN4124_core/hdl/gullwing/rtl/gullwing_wrapper.vhd".
-WARNING:Xst:2565 - Inout <CNTRL0_DDR2_DQ<17>> is never assigned.
-WARNING:Xst:2565 - Inout <CNTRL0_DDR2_DQ<22>> is never assigned.
-WARNING:Xst:2565 - Inout <MIC_DATA<3>> is never assigned.
-WARNING:Xst:2565 - Inout <DES_DVB_ASI> is never assigned.
-WARNING:Xst:1306 - Output <MIC_CLKA> is never assigned.
-WARNING:Xst:2565 - Inout <CNTRL0_DDR2_DQ<18>> is never assigned.
-WARNING:Xst:2565 - Inout <CNTRL0_DDR2_DQ<23>> is never assigned.
-WARNING:Xst:2565 - Inout <MIC_DATA<4>> is never assigned.
-WARNING:Xst:647 - Input <DES> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:1306 - Output <MIC_CLKB> is never assigned.
-WARNING:Xst:647 - Input <CNTRL0_RST_DQS_DIV_IN> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <SYNCSEPERATOR_F_TIMING> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:2565 - Inout <CNTRL0_DDR2_DQ<19>> is never assigned.
-WARNING:Xst:2565 - Inout <CNTRL0_DDR2_DQ<24>> is never assigned.
-WARNING:Xst:2565 - Inout <MIC_DATA<5>> is never assigned.
-WARNING:Xst:2565 - Inout <CNTRL0_DDR2_DQS_N<0>> is never assigned.
-WARNING:Xst:2565 - Inout <CNTRL0_DDR2_DQ<25>> is never assigned.
-WARNING:Xst:2565 - Inout <CNTRL0_DDR2_DQ<30>> is never assigned.
-WARNING:Xst:2565 - Inout <MIC_DATA<6>> is never assigned.
-WARNING:Xst:2565 - Inout <CNTRL0_DDR2_DQS_N<1>> is never assigned.
-WARNING:Xst:2565 - Inout <MIC_DATA<7>> is never assigned.
-WARNING:Xst:2565 - Inout <CNTRL0_DDR2_DQ<26>> is never assigned.
-WARNING:Xst:2565 - Inout <CNTRL0_DDR2_DQ<31>> is never assigned.
-WARNING:Xst:2565 - Inout <CNTRL0_DDR2_DQS_N<2>> is never assigned.
-WARNING:Xst:2565 - Inout <CNTRL0_DDR2_DQ<27>> is never assigned.
-WARNING:Xst:2565 - Inout <MIC_DATA<8>> is never assigned.
-WARNING:Xst:2565 - Inout <MIC_DATA<10>> is never assigned.
-WARNING:Xst:2565 - Inout <CNTRL0_DDR2_DQS_N<3>> is never assigned.
-WARNING:Xst:2565 - Inout <CNTRL0_DDR2_DQS<0>> is never assigned.
-WARNING:Xst:647 - Input <SPI_SS> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:2565 - Inout <CNTRL0_DDR2_DQ<28>> is never assigned.
-WARNING:Xst:2565 - Inout <MIC_DATA<9>> is never assigned.
-WARNING:Xst:2565 - Inout <CNTRL0_DDR2_DQS<1>> is never assigned.
-WARNING:Xst:2565 - Inout <MIC_DATA<11>> is never assigned.
-WARNING:Xst:2565 - Inout <CNTRL0_DDR2_DQ<29>> is never assigned.
-WARNING:Xst:647 - Input <SYS_CLKB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:2565 - Inout <MIC_DATA<12>> is never assigned.
-WARNING:Xst:2565 - Inout <CNTRL0_DDR2_DQS<2>> is never assigned.
-WARNING:Xst:1306 - Output <CNTRL0_DDR2_CKE> is never assigned.
-WARNING:Xst:2565 - Inout <CNTRL0_DDR2_DQS<3>> is never assigned.
-WARNING:Xst:2565 - Inout <MIC_DATA<13>> is never assigned.
-WARNING:Xst:2565 - Inout <MIC_DATA<14>> is never assigned.
-WARNING:Xst:2565 - Inout <MIC_DATA<20>> is never assigned.
-WARNING:Xst:2565 - Inout <MIC_DATA<15>> is never assigned.
-WARNING:Xst:2565 - Inout <MIC_DATA<21>> is never assigned.
-WARNING:Xst:2565 - Inout <GPIO<0>> is never assigned.
-WARNING:Xst:2565 - Inout <MIC_DATA<16>> is never assigned.
-WARNING:Xst:1306 - Output <CNTRL0_DDR2_A> is never assigned.
-WARNING:Xst:1306 - Output <CNTRL0_RST_DQS_DIV_OUT> is never assigned.
-WARNING:Xst:2565 - Inout <DES_SDHDN> is never assigned.
-WARNING:Xst:2565 - Inout <GPIO<1>> is never assigned.
-WARNING:Xst:2565 - Inout <MIC_DATA<17>> is never assigned.
-WARNING:Xst:2565 - Inout <MIC_DATA<22>> is never assigned.
-WARNING:Xst:1306 - Output <CNTRL0_DDR2_CAS_N> is never assigned.
-WARNING:Xst:2565 - Inout <MIC_DATA<23>> is never assigned.
-WARNING:Xst:2565 - Inout <GPIO<2>> is never assigned.
-WARNING:Xst:2565 - Inout <MIC_DATA<18>> is never assigned.
-WARNING:Xst:2565 - Inout <MIC_DATA<24>> is never assigned.
-WARNING:Xst:2565 - Inout <GPIO<3>> is never assigned.
-WARNING:Xst:2565 - Inout <MIC_DATA<19>> is never assigned.
-WARNING:Xst:2565 - Inout <MIC_DATA<30>> is never assigned.
-WARNING:Xst:2565 - Inout <GPIO<4>> is never assigned.
-WARNING:Xst:2565 - Inout <MIC_DATA<25>> is never assigned.
-WARNING:Xst:2565 - Inout <MIC_DATA<31>> is never assigned.
-WARNING:Xst:2565 - Inout <GPIO<5>> is never assigned.
-WARNING:Xst:2565 - Inout <MIC_DATA<26>> is never assigned.
-WARNING:Xst:647 - Input <PCLK_4911_1531> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <DES_PCLK> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:2565 - Inout <GPIO<6>> is never assigned.
-WARNING:Xst:2565 - Inout <MIC_DATA<27>> is never assigned.
-WARNING:Xst:647 - Input <DES_F> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:2565 - Inout <MIC_DATA<28>> is never assigned.
-WARNING:Xst:2565 - Inout <GPIO<7>> is never assigned.
-WARNING:Xst:647 - Input <DES_H> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:2565 - Inout <MIC_DATA<29>> is never assigned.
-WARNING:Xst:647 - Input <GS4911_SDOUT> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:1306 - Output <CNTRL0_DDR2_CK_N> is never assigned.
-WARNING:Xst:2565 - Inout <GPIO<9>> is never assigned.
-WARNING:Xst:647 - Input <DES_V> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <RESET_IN_N> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:1306 - Output <CNTRL0_DDR2_CS_N> is never assigned.
-WARNING:Xst:2565 - Inout <GPIO<10>> is never assigned.
-WARNING:Xst:647 - Input <L_RST33_N> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:2565 - Inout <GPIO<11>> is never assigned.
-WARNING:Xst:2565 - Inout <GPIO<12>> is never assigned.
-WARNING:Xst:1306 - Output <CNTRL0_DDR2_BA> is never assigned.
-WARNING:Xst:647 - Input <SYNCSEPERATOR_H_TIMING> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:2565 - Inout <GPIO<13>> is never assigned.
-WARNING:Xst:1306 - Output <CNTRL0_DDR2_ODT> is never assigned.
-WARNING:Xst:2565 - Inout <DES_SMPTE_BYPASS> is never assigned.
-WARNING:Xst:2565 - Inout <CNTRL0_DDR2_DQ<0>> is never assigned.
-WARNING:Xst:2565 - Inout <GPIO<14>> is never assigned.
-WARNING:Xst:2565 - Inout <CNTRL0_DDR2_DQ<1>> is never assigned.
-WARNING:Xst:2565 - Inout <GPIO<15>> is never assigned.
-WARNING:Xst:647 - Input <SPI_SCK> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:1306 - Output <CNTRL0_DDR2_WE_N> is never assigned.
-WARNING:Xst:1306 - Output <CNTRL0_DDR2_CK> is never assigned.
-WARNING:Xst:2565 - Inout <CNTRL0_DDR2_DQ<2>> is never assigned.
-WARNING:Xst:647 - Input <SYNCSEPERATOR_V_TIMING> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:2565 - Inout <CNTRL0_DDR2_DQ<3>> is never assigned.
-WARNING:Xst:1306 - Output <CNTRL0_DDR2_DM> is never assigned.
-WARNING:Xst:647 - Input <SPI_MOSI> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:2565 - Inout <CNTRL0_DDR2_DQ<4>> is never assigned.
-WARNING:Xst:2565 - Inout <CNTRL0_DDR2_DQ<5>> is never assigned.
-WARNING:Xst:2565 - Inout <CNTRL0_DDR2_DQ<6>> is never assigned.
-WARNING:Xst:2565 - Inout <CNTRL0_DDR2_DQ<10>> is never assigned.
-WARNING:Xst:2565 - Inout <CNTRL0_DDR2_DQ<7>> is never assigned.
-WARNING:Xst:2565 - Inout <CNTRL0_DDR2_DQ<11>> is never assigned.
-WARNING:Xst:2565 - Inout <SDA> is never assigned.
-WARNING:Xst:647 - Input <GS4911_LOCK_LOST> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:2565 - Inout <CNTRL0_DDR2_DQ<8>> is never assigned.
-WARNING:Xst:2565 - Inout <CNTRL0_DDR2_DQ<12>> is never assigned.
-WARNING:Xst:647 - Input <SCL> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:2565 - Inout <CNTRL0_DDR2_DQ<9>> is never assigned.
-WARNING:Xst:2565 - Inout <CNTRL0_DDR2_DQ<13>> is never assigned.
-WARNING:Xst:647 - Input <GS4911_REF_LOST> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:1306 - Output <CNTRL0_DDR2_RAS_N> is never assigned.
-WARNING:Xst:2565 - Inout <MIC_DATA<0>> is never assigned.
-WARNING:Xst:2565 - Inout <CNTRL0_DDR2_DQ<14>> is never assigned.
-WARNING:Xst:2565 - Inout <MIC_DATA<1>> is never assigned.
-WARNING:Xst:2565 - Inout <CNTRL0_DDR2_DQ<15>> is never assigned.
-WARNING:Xst:2565 - Inout <CNTRL0_DDR2_DQ<20>> is never assigned.
-WARNING:Xst:1306 - Output <SER> is never assigned.
-WARNING:Xst:647 - Input <SYS_CLK> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:2565 - Inout <MIC_DATA<2>> is never assigned.
-WARNING:Xst:2565 - Inout <CNTRL0_DDR2_DQ<16>> is never assigned.
-WARNING:Xst:2565 - Inout <CNTRL0_DDR2_DQ<21>> is never assigned.
-WARNING:Xst:646 - Signal <wb_adr<17:2>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <dummy_ctrl_reg_led<31:8>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <dummy_ctrl_reg_3> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <dummy_ctrl_reg_2> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <dummy_ctrl_reg_1<31:1>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <dma_sel_o> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <dma_adr_o<31:11>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-    Found 1-bit register for signal <dma_ack_i>.
-    Summary:
-	inferred   1 D-type flip-flop(s).
-Unit <gw_wrapper> synthesized.
-
-
-=========================================================================
-HDL Synthesis Report
-
-Macro Statistics
-# Adders/Subtractors                                   : 8
- 11-bit subtractor                                     : 1
- 2-bit adder                                           : 1
- 30-bit adder                                          : 1
- 30-bit subtractor                                     : 2
- 32-bit adder                                          : 1
- 32-bit subtractor                                     : 2
-# Counters                                             : 8
- 11-bit down counter                                   : 1
- 30-bit down counter                                   : 1
- 30-bit up counter                                     : 2
- 32-bit up counter                                     : 4
-# Registers                                            : 492
- 1-bit register                                        : 400
- 10-bit register                                       : 3
- 11-bit register                                       : 1
- 16-bit register                                       : 1
- 2-bit register                                        : 8
- 3-bit register                                        : 1
- 30-bit register                                       : 2
- 31-bit register                                       : 1
- 32-bit register                                       : 69
- 4-bit register                                        : 6
-# Comparators                                          : 9
- 11-bit comparator lessequal                           : 3
- 2-bit comparator less                                 : 1
- 30-bit comparator greater                             : 3
- 32-bit comparator equal                               : 2
-# Multiplexers                                         : 35
- 1-bit 4-to-1 multiplexer                              : 32
- 32-bit 4-to-1 multiplexer                             : 3
-
-=========================================================================
-
-=========================================================================
-*                       Advanced HDL Synthesis                          *
-=========================================================================
-
-Analyzing FSM <FSM_4> for best encoding.
-Optimizing FSM <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_current_state/FSM> on signal <p2l_dma_current_state[1:3]> with user encoding.
---------------------------------------
- State                    | Encoding
---------------------------------------
- p2l_idle                 | 000
- p2l_header               | 001
- p2l_addr_h               | 010
- p2l_addr_l               | 011
- p2l_wait_read_completion | 100
---------------------------------------
-Analyzing FSM <FSM_3> for best encoding.
-Optimizing FSM <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_current_state/FSM> on signal <l2p_dma_current_state[1:8]> with one-hot encoding.
----------------------------
- State         | Encoding
----------------------------
- l2p_idle      | 00000001
- l2p_wait_data | 10000000
- l2p_header    | 00000010
- l2p_addr_h    | 00000100
- l2p_addr_l    | 00001000
- l2p_data      | 00100000
- l2p_last_data | 00010000
- l2p_wait_rdy  | 01000000
----------------------------
-Analyzing FSM <FSM_2> for best encoding.
-Optimizing FSM <cmp_gn4124_core/cmp_dma_controller/dma_ctrl_current_state/FSM> on signal <dma_ctrl_current_state[1:7]> with one-hot encoding.
---------------------------------
- State              | Encoding
---------------------------------
- dma_idle           | 0000001
- dma_start_transfer | 0000010
- dma_transfer       | 0001000
- dma_start_chain    | 0100000
- dma_chain          | 1000000
- dma_error          | 0000100
- dma_abort          | 0010000
---------------------------------
-Analyzing FSM <FSM_1> for best encoding.
-Optimizing FSM <cmp_gn4124_core/cmp_wbmaster32/l2p_read_cpl_current_state/FSM> on signal <l2p_read_cpl_current_state[1:2]> with user encoding.
-------------------------
- State      | Encoding
-------------------------
- l2p_idle   | 00
- l2p_header | 01
- l2p_data   | 10
-------------------------
-Analyzing FSM <FSM_0> for best encoding.
-Optimizing FSM <cmp_gn4124_core/cmp_wbmaster32/wishbone_current_state/FSM> on signal <wishbone_current_state[1:4]> with one-hot encoding.
---------------------------
- State        | Encoding
---------------------------
- wb_idle      | 0001
- wb_read_fifo | 0010
- wb_cycle     | 0100
- wb_wait_ack  | 1000
---------------------------
-Reading core <../ip_cores/ram_2048x32.ngc>.
-Reading core <../ip_cores/fifo_64x512.ngc>.
-Reading core <../ip_cores/fifo_32x512.ngc>.
-Loading core <ram_2048x32> for timing and area information for instance <cmp_test_ram>.
-Loading core <fifo_64x512> for timing and area information for instance <cmp_fifo_to_wb>.
-Loading core <fifo_32x512> for timing and area information for instance <cmp_from_wb_fifo>.
-Loading core <fifo_32x512> for timing and area information for instance <cmp_addr_fifo>.
-Loading core <fifo_32x512> for timing and area information for instance <cmp_data_fifo>.
-Loading core <fifo_64x512> for timing and area information for instance <cmp_to_wb_fifo>.
-INFO:Xst:2261 - The FF/Latch <addr_fifo_din_30> in Unit <cmp_l2p_dma_master> is equivalent to the following FF/Latch, which will be removed : <addr_fifo_din_31> 
-INFO:Xst:2261 - The FF/Latch <p2l_dma_adr_o_30> in Unit <cmp_p2l_dma_master> is equivalent to the following FF/Latch, which will be removed : <p2l_dma_adr_o_31> 
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_20> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_21> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_22> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_23> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_24> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_25> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_26> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_27> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_28> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_29> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_30> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_31> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <ack_sreg_7> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <addr_fifo_din_30> (without init value) has a constant value of 0 in block <cmp_l2p_dma_master>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <p2l_dma_adr_o_30> (without init value) has a constant value of 0 in block <cmp_p2l_dma_master>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <ack_sreg_7> (without init value) has a constant value of 0 in block <cmp_dummy_stat_regs>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <ack_sreg_7> (without init value) has a constant value of 0 in block <cmp_dummy_ctrl_regs>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_3> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_4> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_5> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_6> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_7> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_8> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_9> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_10> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_11> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_12> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_13> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_14> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_15> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_16> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_17> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_18> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_19> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_6> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_6> (without init value) has a constant value of 0 in block <cmp_dummy_stat_regs>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_6> (without init value) has a constant value of 0 in block <cmp_dummy_ctrl_regs>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_5> (without init value) has a constant value of 0 in block <cmp_dummy_stat_regs>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_5> (without init value) has a constant value of 0 in block <cmp_dummy_ctrl_regs>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_4> (without init value) has a constant value of 0 in block <cmp_dummy_ctrl_regs>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_4> (without init value) has a constant value of 0 in block <cmp_dummy_stat_regs>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_3> (without init value) has a constant value of 0 in block <cmp_dummy_stat_regs>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_3> (without init value) has a constant value of 0 in block <cmp_dummy_ctrl_regs>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_2> (without init value) has a constant value of 0 in block <cmp_dummy_stat_regs>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_2> (without init value) has a constant value of 0 in block <cmp_dummy_ctrl_regs>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_1> (without init value) has a constant value of 0 in block <cmp_dummy_stat_regs>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_1> (without init value) has a constant value of 0 in block <cmp_dummy_ctrl_regs>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:2677 - Node <wb_adr_t_4> of sequential type is unconnected in block <cmp_wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_5> of sequential type is unconnected in block <cmp_wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_6> of sequential type is unconnected in block <cmp_wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_7> of sequential type is unconnected in block <cmp_wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_8> of sequential type is unconnected in block <cmp_wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_9> of sequential type is unconnected in block <cmp_wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_10> of sequential type is unconnected in block <cmp_wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_11> of sequential type is unconnected in block <cmp_wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_12> of sequential type is unconnected in block <cmp_wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_13> of sequential type is unconnected in block <cmp_wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_14> of sequential type is unconnected in block <cmp_wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_15> of sequential type is unconnected in block <cmp_wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_18> of sequential type is unconnected in block <cmp_wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_19> of sequential type is unconnected in block <cmp_wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_20> of sequential type is unconnected in block <cmp_wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_21> of sequential type is unconnected in block <cmp_wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_22> of sequential type is unconnected in block <cmp_wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_23> of sequential type is unconnected in block <cmp_wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_24> of sequential type is unconnected in block <cmp_wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_25> of sequential type is unconnected in block <cmp_wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_26> of sequential type is unconnected in block <cmp_wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_27> of sequential type is unconnected in block <cmp_wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_28> of sequential type is unconnected in block <cmp_wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_29> of sequential type is unconnected in block <cmp_wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_30> of sequential type is unconnected in block <cmp_wbmaster32>.
-WARNING:Xst:2677 - Node <dma_ctrl_carrier_addr_o_0> of sequential type is unconnected in block <cmp_dma_controller>.
-WARNING:Xst:2677 - Node <dma_ctrl_carrier_addr_o_1> of sequential type is unconnected in block <cmp_dma_controller>.
-WARNING:Xst:2677 - Node <dma_ctrl_len_o_0> of sequential type is unconnected in block <cmp_dma_controller>.
-WARNING:Xst:2677 - Node <dma_ctrl_len_o_1> of sequential type is unconnected in block <cmp_dma_controller>.
-WARNING:Xst:2404 -  FFs/Latches <addr_fifo_din<31:30>> (without init value) have a constant value of 0 in block <l2p_dma_master>.
-WARNING:Xst:2404 -  FFs/Latches <p2l_dma_adr_o<31:30>> (without init value) have a constant value of 0 in block <p2l_dma_master>.
-WARNING:Xst:2677 - Node <wb_adr_t_18> of sequential type is unconnected in block <wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_19> of sequential type is unconnected in block <wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_20> of sequential type is unconnected in block <wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_21> of sequential type is unconnected in block <wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_22> of sequential type is unconnected in block <wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_23> of sequential type is unconnected in block <wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_24> of sequential type is unconnected in block <wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_25> of sequential type is unconnected in block <wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_26> of sequential type is unconnected in block <wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_27> of sequential type is unconnected in block <wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_28> of sequential type is unconnected in block <wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_29> of sequential type is unconnected in block <wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_30> of sequential type is unconnected in block <wbmaster32>.
-
-=========================================================================
-Advanced HDL Synthesis Report
-
-Macro Statistics
-# FSMs                                                 : 5
-# Adders/Subtractors                                   : 8
- 11-bit subtractor                                     : 1
- 2-bit adder                                           : 1
- 30-bit adder                                          : 1
- 30-bit subtractor                                     : 2
- 32-bit adder                                          : 1
- 32-bit subtractor                                     : 2
-# Counters                                             : 8
- 11-bit down counter                                   : 1
- 30-bit down counter                                   : 1
- 30-bit up counter                                     : 2
- 32-bit up counter                                     : 4
-# Registers                                            : 2782
- Flip-Flops                                            : 2782
-# Comparators                                          : 9
- 11-bit comparator lessequal                           : 3
- 2-bit comparator less                                 : 1
- 30-bit comparator greater                             : 3
- 32-bit comparator equal                               : 2
-# Multiplexers                                         : 35
- 1-bit 4-to-1 multiplexer                              : 32
- 32-bit 4-to-1 multiplexer                             : 3
-
-=========================================================================
-
-=========================================================================
-*                         Low Level Synthesis                           *
-=========================================================================
-WARNING:Xst:1710 - FF/Latch <ack_sreg_7> (without init value) has a constant value of 0 in block <dummy_stat_regs_wb_slave>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_6> (without init value) has a constant value of 0 in block <dummy_stat_regs_wb_slave>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_5> (without init value) has a constant value of 0 in block <dummy_stat_regs_wb_slave>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_4> (without init value) has a constant value of 0 in block <dummy_stat_regs_wb_slave>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_3> (without init value) has a constant value of 0 in block <dummy_stat_regs_wb_slave>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_2> (without init value) has a constant value of 0 in block <dummy_stat_regs_wb_slave>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_1> (without init value) has a constant value of 0 in block <dummy_stat_regs_wb_slave>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <ack_sreg_7> (without init value) has a constant value of 0 in block <dummy_ctrl_regs_wb_slave>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_6> (without init value) has a constant value of 0 in block <dummy_ctrl_regs_wb_slave>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_5> (without init value) has a constant value of 0 in block <dummy_ctrl_regs_wb_slave>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_4> (without init value) has a constant value of 0 in block <dummy_ctrl_regs_wb_slave>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_3> (without init value) has a constant value of 0 in block <dummy_ctrl_regs_wb_slave>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_2> (without init value) has a constant value of 0 in block <dummy_ctrl_regs_wb_slave>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_1> (without init value) has a constant value of 0 in block <dummy_ctrl_regs_wb_slave>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <ack_sreg_7> (without init value) has a constant value of 0 in block <dma_controller_wb_slave>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_6> (without init value) has a constant value of 0 in block <dma_controller_wb_slave>. This FF/Latch will be trimmed during the optimization process.
-INFO:Xst:2261 - The FF/Latch <l2p_dma_sel_o_0> in Unit <l2p_dma_master> is equivalent to the following 4 FFs/Latches, which will be removed : <l2p_dma_sel_o_1> <l2p_dma_sel_o_2> <l2p_dma_sel_o_3> <l2p_dma_stb_t> 
-INFO:Xst:2261 - The FF/Latch <p2l_dma_sel_o_0> in Unit <p2l_dma_master> is equivalent to the following 4 FFs/Latches, which will be removed : <p2l_dma_sel_o_1> <p2l_dma_sel_o_2> <p2l_dma_sel_o_3> <p2l_dma_stb_t> 
-INFO:Xst:2261 - The FF/Latch <dma_stat_int_read_3> in Unit <dma_controller_wb_slave> is equivalent to the following 28 FFs/Latches, which will be removed : <dma_stat_int_read_4> <dma_stat_int_read_5> <dma_stat_int_read_6> <dma_stat_int_read_7> <dma_stat_int_read_8> <dma_stat_int_read_9> <dma_stat_int_read_10> <dma_stat_int_read_11> <dma_stat_int_read_12> <dma_stat_int_read_13> <dma_stat_int_read_14> <dma_stat_int_read_15> <dma_stat_int_read_16> <dma_stat_int_read_17> <dma_stat_int_read_18> <dma_stat_int_read_19> <dma_stat_int_read_20> <dma_stat_int_read_21> <dma_stat_int_read_22> <dma_stat_int_read_23> <dma_stat_int_read_24> <dma_stat_int_read_25> <dma_stat_int_read_26> <dma_stat_int_read_27> <dma_stat_int_read_28> <dma_stat_int_read_29> <dma_stat_int_read_30> <dma_stat_int_read_31> 
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_3> (without init value) has a constant value of 0 in block <dma_controller_wb_slave>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <rddata_reg_8> (without init value) has a constant value of 0 in block <dummy_stat_regs_wb_slave>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_24> (without init value) has a constant value of 0 in block <dummy_stat_regs_wb_slave>. This FF/Latch will be trimmed during the optimization process.
-
-Optimizing unit <gw_wrapper> ...
-
-Optimizing unit <dummy_stat_regs_wb_slave> ...
-
-Optimizing unit <dummy_ctrl_regs_wb_slave> ...
-
-Optimizing unit <p2l_decode32> ...
-
-Optimizing unit <l2p_arbiter> ...
-
-Optimizing unit <dma_controller_wb_slave> ...
-
-Optimizing unit <p2l_des> ...
-
-Optimizing unit <wbmaster32> ...
-
-Optimizing unit <l2p_dma_master> ...
-
-Optimizing unit <p2l_dma_master> ...
-
-Optimizing unit <l2p_ser> ...
-
-Optimizing unit <dma_controller> ...
-
-Optimizing unit <gn4124_core> ...
-WARNING:Xst:2677 - Node <cmp_dummy_ctrl_regs/dummy_reg_1_wr_o> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_ctrl_carrier_addr_o_0> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_ctrl_carrier_addr_o_1> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_ctrl_len_o_0> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_ctrl_len_o_1> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_31> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_30> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_29> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_28> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_27> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_26> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_25> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_24> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_23> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_22> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_21> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_20> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_19> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_18> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_17> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_16> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_15> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_14> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_13> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_12> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_11> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_10> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_9> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_8> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_7> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_6> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_5> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_4> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_3> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_2> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_1> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_0> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_load_o> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_31> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_30> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_29> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_28> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_27> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_26> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_25> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_24> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_23> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_22> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_21> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_20> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_19> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_18> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_17> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_16> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_15> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_14> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_13> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_12> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_11> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_10> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_9> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_8> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_7> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_6> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_5> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_4> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_3> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_2> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_1> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_0> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_11> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_12> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_13> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_14> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_15> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_16> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_17> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_18> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_19> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_20> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_21> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_22> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_23> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_24> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_25> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_26> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_27> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_28> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_29> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_11> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_12> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_13> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_14> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_15> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_16> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_17> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_18> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_19> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_20> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_21> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_22> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_23> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_24> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_25> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_26> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_27> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_28> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_29> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_30> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_31> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_sel_t_0> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_sel_t_1> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_sel_t_2> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_sel_t_3> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_4> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_5> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_6> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_7> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_8> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_9> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_10> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_11> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_12> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_13> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_14> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_15> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_length_0> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_length_1> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_length_2> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_length_3> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_length_4> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_length_5> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_length_6> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_length_7> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_length_8> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_length_9> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_last> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_lbe_0> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_lbe_1> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_lbe_2> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_lbe_3> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_fbe_0> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_fbe_1> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_fbe_2> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_fbe_3> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_stat_0> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_stat_1> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_be_0> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_be_1> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_be_2> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_be_3> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_addr_1> of sequential type is unconnected in block <gw_wrapper>.
-
-Mapping all equations...
-Building and optimizing final netlist ...
-Found area constraint ratio of 100 (+ 5) on block gw_wrapper, actual ratio is 23.
-Forward register balancing over carry chain cmp_gn4124_core/cmp_dma_controller/dma_ctrl_current_state_cmp_eq0000_wg_cy<0>
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/wr_rst_reg_1> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/wr_rst_reg_0> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_i> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/rd_rst_reg_2> in Unit <BU2> is equivalent to the following 2 FFs/Latches : <U0/grf.rf/rstblk/rd_rst_reg_1> <U0/grf.rf/rstblk/rd_rst_reg_0> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/wr_rst_reg_1> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/wr_rst_reg_0> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_i> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/rd_rst_reg_2> in Unit <BU2> is equivalent to the following 2 FFs/Latches : <U0/grf.rf/rstblk/rd_rst_reg_1> <U0/grf.rf/rstblk/rd_rst_reg_0> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/wr_rst_reg_1> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/wr_rst_reg_0> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_i> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/rd_rst_reg_2> in Unit <BU2> is equivalent to the following 2 FFs/Latches : <U0/grf.rf/rstblk/rd_rst_reg_1> <U0/grf.rf/rstblk/rd_rst_reg_0> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/wr_rst_reg_1> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/wr_rst_reg_0> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_i> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/rd_rst_reg_2> in Unit <BU2> is equivalent to the following 2 FFs/Latches : <U0/grf.rf/rstblk/rd_rst_reg_1> <U0/grf.rf/rstblk/rd_rst_reg_0> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/wr_rst_reg_1> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/wr_rst_reg_0> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_i> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/rd_rst_reg_2> in Unit <BU2> is equivalent to the following 2 FFs/Latches : <U0/grf.rf/rstblk/rd_rst_reg_1> <U0/grf.rf/rstblk/rd_rst_reg_0> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/wr_rst_reg_1> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/wr_rst_reg_0> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/rd_rst_reg_2> in Unit <BU2> is equivalent to the following 2 FFs/Latches : <U0/grf.rf/rstblk/rd_rst_reg_1> <U0/grf.rf/rstblk/rd_rst_reg_0> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_i> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/wr_rst_reg_1> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/wr_rst_reg_0> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/rd_rst_reg_2> in Unit <BU2> is equivalent to the following 2 FFs/Latches : <U0/grf.rf/rstblk/rd_rst_reg_1> <U0/grf.rf/rstblk/rd_rst_reg_0> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_i> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/wr_rst_reg_1> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/wr_rst_reg_0> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/rd_rst_reg_2> in Unit <BU2> is equivalent to the following 2 FFs/Latches : <U0/grf.rf/rstblk/rd_rst_reg_1> <U0/grf.rf/rstblk/rd_rst_reg_0> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_i> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/wr_rst_reg_1> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/wr_rst_reg_0> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/rd_rst_reg_2> in Unit <BU2> is equivalent to the following 2 FFs/Latches : <U0/grf.rf/rstblk/rd_rst_reg_1> <U0/grf.rf/rstblk/rd_rst_reg_0> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_i> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/wr_rst_reg_1> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/wr_rst_reg_0> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/rd_rst_reg_2> in Unit <BU2> is equivalent to the following 2 FFs/Latches : <U0/grf.rf/rstblk/rd_rst_reg_1> <U0/grf.rf/rstblk/rd_rst_reg_0> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_i> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i> 
-
-Pipelining and Register Balancing Report ...
-
-Processing Unit <gw_wrapper> :
-	Register(s) cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_10 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_10_BRB1 cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_10_BRB2.
-	Register(s) cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_11 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_11_BRB1 cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_11_BRB2.
-	Register(s) cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_12 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_12_BRB1 cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_12_BRB2.
-	Register(s) cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_13 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_13_BRB1 cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_13_BRB2.
-	Register(s) cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_14 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_14_BRB1 cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_14_BRB2.
-	Register(s) cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_15 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_15_BRB1 cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_15_BRB2.
-	Register(s) cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_16 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_16_BRB1 cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_16_BRB2.
-	Register(s) cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_17 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_17_BRB1 cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_17_BRB2.
-	Register(s) cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_18 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_18_BRB1 cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_18_BRB2.
-	Register(s) cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_19 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_19_BRB1 cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_19_BRB2.
-	Register(s) cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_2 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_2_BRB0 cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_2_BRB1 cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_2_BRB2.
-	Register(s) cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_20 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_20_BRB1 cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_20_BRB2.
-	Register(s) cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_21 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_21_BRB1 cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_21_BRB2.
-	Register(s) cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_22 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_22_BRB1 cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_22_BRB2.
-	Register(s) cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_23 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_23_BRB1 cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_23_BRB2.
-	Register(s) cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_24 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_24_BRB1 cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_24_BRB2.
-	Register(s) cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_25 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_25_BRB1 cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_25_BRB2.
-	Register(s) cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_26 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_26_BRB1 cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_26_BRB2.
-	Register(s) cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_27 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_27_BRB1 cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_27_BRB2.
-	Register(s) cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_28 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_28_BRB1 cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_28_BRB2.
-	Register(s) cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_29 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_29_BRB1 cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_29_BRB2.
-	Register(s) cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_3 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_3_BRB1 cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_3_BRB2.
-	Register(s) cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_30 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_30_BRB1 cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_30_BRB2.
-	Register(s) cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_31 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_31_BRB1 cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_31_BRB2.
-	Register(s) cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_4 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_4_BRB1 cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_4_BRB2.
-	Register(s) cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_5 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_5_BRB1 cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_5_BRB2.
-	Register(s) cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_6 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_6_BRB1 cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_6_BRB2.
-	Register(s) cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_7 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_7_BRB1 cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_7_BRB2.
-	Register(s) cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_8 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_8_BRB1 cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_8_BRB2.
-	Register(s) cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_9 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_9_BRB1 cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_9_BRB2.
-	Register(s) cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/ack_sreg_2 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/ack_sreg_2_BRB0 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/ack_sreg_2_BRB1 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/ack_sreg_2_BRB2.
-	Register(s) cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/ack_sreg_3 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/ack_sreg_3_BRB0 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/ack_sreg_3_BRB1 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/ack_sreg_3_BRB2.
-	Register(s) cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/ack_sreg_4 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/ack_sreg_4_BRB0 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/ack_sreg_4_BRB1 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/ack_sreg_4_BRB2.
-	Register(s) cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/ack_sreg_5 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/ack_sreg_5_BRB0 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/ack_sreg_5_BRB1 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/ack_sreg_5_BRB2.
-	Register(s) cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_attrib_lw has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_attrib_lw_BRB0 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_attrib_lw_BRB1.
-	Register(s) cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_cstart_lw has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_cstart_lw_BRB0 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_cstart_lw_BRB1.
-	Register(s) cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_ctrl_lw has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_ctrl_lw_BRB0 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_ctrl_lw_BRB1.
-	Register(s) cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_hstarth_lw has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_hstarth_lw_BRB0 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_hstarth_lw_BRB1.
-	Register(s) cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_hstartl_lw has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_hstartl_lw_BRB0 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_hstartl_lw_BRB1.
-	Register(s) cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_len_lw has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_len_lw_BRB0 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_len_lw_BRB1.
-	Register(s) cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_nexth_lw has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_nexth_lw_BRB0 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_nexth_lw_BRB1.
-	Register(s) cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_nextl_lw has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_nextl_lw_BRB0 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_nextl_lw_BRB1.
-	Register(s) cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_lw has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_lw_BRB0 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_lw_BRB1.
-	Register(s) cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_24 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_24_BRB0 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_24_BRB1 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_24_BRB2 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_24_BRB3.
-	Register(s) cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_8 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_8_BRB0 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_8_BRB1 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_8_BRB3.
-	Register(s) cmp_gn4124_core/cmp_dma_controller/dma_cstart_reg_0 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_cstart_reg_0_BRB0 cmp_gn4124_core/cmp_dma_controller/dma_cstart_reg_0_BRB1 cmp_gn4124_core/cmp_dma_controller/dma_cstart_reg_0_BRB2.
-	Register(s) cmp_gn4124_core/cmp_dma_controller/dma_cstart_reg_1 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_cstart_reg_1_BRB1 cmp_gn4124_core/cmp_dma_controller/dma_cstart_reg_1_BRB2.
-	Register(s) cmp_gn4124_core/cmp_dma_controller/dma_len_reg_0 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_len_reg_0_BRB0 cmp_gn4124_core/cmp_dma_controller/dma_len_reg_0_BRB1 cmp_gn4124_core/cmp_dma_controller/dma_len_reg_0_BRB2.
-	Register(s) cmp_gn4124_core/cmp_dma_controller/dma_len_reg_1 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_len_reg_1_BRB1 cmp_gn4124_core/cmp_dma_controller/dma_len_reg_1_BRB2.
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_0 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_0_BRB0 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_0_BRB1 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_0_BRB2.
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_1 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_1_BRB0 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_1_BRB1 .
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_10 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_10_BRB0 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_10_BRB1 .
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_11 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_11_BRB0 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_11_BRB1 .
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_12 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_12_BRB0 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_12_BRB1 .
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_13 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_13_BRB0 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_13_BRB1 .
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_14 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_14_BRB0 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_14_BRB1 .
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_15 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_15_BRB0 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_15_BRB1 .
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_16 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_16_BRB0 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_16_BRB1 .
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_17 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_17_BRB0 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_17_BRB1 .
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_18 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_18_BRB0 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_18_BRB1 .
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_19 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_19_BRB0 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_19_BRB1 .
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_2 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_2_BRB0 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_2_BRB1 .
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_20 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_20_BRB0 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_20_BRB1 .
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_21 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_21_BRB0 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_21_BRB1 .
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_22 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_22_BRB0 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_22_BRB1 .
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_23 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_23_BRB0 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_23_BRB1 .
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_24 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_24_BRB0 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_24_BRB1 .
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_25 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_25_BRB0 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_25_BRB1 .
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_26 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_26_BRB0 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_26_BRB1 .
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_27 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_27_BRB0 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_27_BRB1 .
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_28 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_28_BRB0 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_28_BRB1 .
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_29 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_29_BRB0 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_29_BRB1 .
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_3 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_3_BRB0 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_3_BRB1 .
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_30 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_30_BRB0 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_30_BRB1 .
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_31 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_31_BRB0 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_31_BRB1 .
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_4 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_4_BRB0 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_4_BRB1 .
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_5 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_5_BRB0 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_5_BRB1 .
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_6 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_6_BRB0 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_6_BRB1 .
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_7 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_7_BRB0 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_7_BRB1 .
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_8 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_8_BRB0 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_8_BRB1 .
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_9 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_9_BRB0 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_9_BRB1 .
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_0 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_0_BRB1 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_0_BRB2 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_0_BRB3 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_0_BRB4 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_0_BRB5 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_0_BRB6 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_0_BRB8.
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_1 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_1_BRB1 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_1_BRB3 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_1_BRB5.
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_10 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_10_BRB1 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_10_BRB3 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_10_BRB5.
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_11 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_11_BRB1 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_11_BRB3 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_11_BRB5.
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_12 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_12_BRB1 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_12_BRB3 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_12_BRB5.
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_13 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_13_BRB1 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_13_BRB3 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_13_BRB5.
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_14 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_14_BRB1 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_14_BRB3 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_14_BRB5.
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_15 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_15_BRB1 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_15_BRB3 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_15_BRB5.
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_16 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_16_BRB1 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_16_BRB3 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_16_BRB5.
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_17 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_17_BRB1 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_17_BRB3 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_17_BRB5.
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_18 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_18_BRB1 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_18_BRB3 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_18_BRB5.
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_19 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_19_BRB1 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_19_BRB3 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_19_BRB5.
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_2 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_2_BRB1 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_2_BRB3 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_2_BRB5.
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_20 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_20_BRB1 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_20_BRB3 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_20_BRB5.
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_21 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_21_BRB1 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_21_BRB3 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_21_BRB5.
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_22 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_22_BRB1 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_22_BRB3 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_22_BRB5.
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_23 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_23_BRB1 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_23_BRB3 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_23_BRB5.
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_24 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_24_BRB1 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_24_BRB3 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_24_BRB5.
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_25 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_25_BRB1 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_25_BRB3 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_25_BRB5.
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_26 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_26_BRB1 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_26_BRB3 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_26_BRB5.
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_27 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_27_BRB1 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_27_BRB3 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_27_BRB5.
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_28 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_28_BRB1 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_28_BRB3 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_28_BRB5.
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_29 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_29_BRB1 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_29_BRB3 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_29_BRB5.
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_3 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_3_BRB1 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_3_BRB3 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_3_BRB5.
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_30 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_30_BRB1 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_30_BRB3 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_30_BRB5.
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_31 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_31_BRB1 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_31_BRB3 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_31_BRB5.
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_4 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_4_BRB1 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_4_BRB3 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_4_BRB5.
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_5 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_5_BRB1 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_5_BRB3 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_5_BRB5.
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_6 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_6_BRB1 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_6_BRB3 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_6_BRB5.
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_7 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_7_BRB1 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_7_BRB3 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_7_BRB5.
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_8 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_8_BRB1 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_8_BRB3 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_8_BRB5.
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_9 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_9_BRB1 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_9_BRB3 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_9_BRB5.
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_dframe_o has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_dframe_o_BRB1 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_dframe_o_BRB2 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_dframe_o_BRB3 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_dframe_o_BRB4 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_dframe_o_BRB5.
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_dframe_t has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_dframe_t_BRB1 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_dframe_t_BRB3 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_dframe_t_BRB5.
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_valid_o has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_valid_o_BRB1 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_valid_o_BRB3 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_valid_o_BRB5.
-	Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_valid_t has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_valid_t_BRB1 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_valid_t_BRB3 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_valid_t_BRB5.
-	Register(s) cmp_gn4124_core/cmp_l2p_ser/dframe_d has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_ser/dframe_d_BRB0 cmp_gn4124_core/cmp_l2p_ser/dframe_d_BRB1 cmp_gn4124_core/cmp_l2p_ser/dframe_d_BRB2.
-	Register(s) cmp_gn4124_core/cmp_l2p_ser/valid_d has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_ser/valid_d_BRB0 cmp_gn4124_core/cmp_l2p_ser/valid_d_BRB1 .
-	Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_0 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_0_BRB0 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_0_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_0_BRB2 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_0_BRB3.
-	Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_1 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_1_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_1_BRB3.
-	Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_10 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_10_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_10_BRB3.
-	Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_11 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_11_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_11_BRB3.
-	Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_12 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_12_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_12_BRB3.
-	Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_13 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_13_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_13_BRB3.
-	Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_14 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_14_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_14_BRB3.
-	Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_15 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_15_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_15_BRB3.
-	Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_16 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_16_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_16_BRB3.
-	Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_17 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_17_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_17_BRB3.
-	Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_18 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_18_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_18_BRB3.
-	Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_19 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_19_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_19_BRB3.
-	Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_2 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_2_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_2_BRB3.
-	Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_20 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_20_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_20_BRB3.
-	Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_21 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_21_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_21_BRB3.
-	Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_22 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_22_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_22_BRB3.
-	Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_23 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_23_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_23_BRB3.
-	Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_24 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_24_BRB2 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_24_BRB3.
-	Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_25 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_25_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_25_BRB3.
-	Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_26 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_26_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_26_BRB3.
-	Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_27 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_27_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_27_BRB3.
-	Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_28 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_28_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_28_BRB3.
-	Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_29 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_29_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_29_BRB3.
-	Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_3 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_3_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_3_BRB3.
-	Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_30 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_30_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_30_BRB3.
-	Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_31 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_31_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_31_BRB3.
-	Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_4 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_4_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_4_BRB3.
-	Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_5 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_5_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_5_BRB3.
-	Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_6 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_6_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_6_BRB3.
-	Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_7 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_7_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_7_BRB3.
-	Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_8 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_8_BRB0 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_8_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_8_BRB2 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_8_BRB3.
-	Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_9 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_9_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_9_BRB3.
-Unit <gw_wrapper> processed.
-Replicating register cmp_gn4124_core/cmp_l2p_dma_master/l2p_edb_o to handle IOB=TRUE attribute
-Replicating register cmp_dummy_ctrl_regs/dummy_reg_led_int_7 to handle IOB=TRUE attribute
-Replicating register cmp_dummy_ctrl_regs/dummy_reg_led_int_6 to handle IOB=TRUE attribute
-Replicating register cmp_dummy_ctrl_regs/dummy_reg_led_int_5 to handle IOB=TRUE attribute
-Replicating register cmp_dummy_ctrl_regs/dummy_reg_led_int_4 to handle IOB=TRUE attribute
-Replicating register cmp_dummy_ctrl_regs/dummy_reg_led_int_3 to handle IOB=TRUE attribute
-Replicating register cmp_dummy_ctrl_regs/dummy_reg_led_int_2 to handle IOB=TRUE attribute
-Replicating register cmp_dummy_ctrl_regs/dummy_reg_led_int_1 to handle IOB=TRUE attribute
-Replicating register cmp_dummy_ctrl_regs/dummy_reg_led_int_0 to handle IOB=TRUE attribute
-
-FlipFlop cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/ack_in_progress has been replicated 1 time(s)
-
-Final Macro Processing ...
-
-Processing Unit <gw_wrapper> :
-	Found 4-bit shift register for signal <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/ack_sreg_2_BRB0>.
-	Found 4-bit shift register for signal <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/ack_sreg_2_BRB1>.
-	Found 4-bit shift register for signal <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/ack_sreg_2_BRB2>.
-	Found 2-bit shift register for signal <cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_dframe_o_BRB5>.
-	Found 2-bit shift register for signal <cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_valid_o_BRB5>.
-Unit <gw_wrapper> processed.
-
-=========================================================================
-Final Register Report
-
-Macro Statistics
-# Registers                                            : 3032
- Flip-Flops                                            : 3032
-# Shift Registers                                      : 5
- 2-bit shift register                                  : 2
- 4-bit shift register                                  : 3
-
-=========================================================================
-
-=========================================================================
-*                           Partition Report                            *
-=========================================================================
-
-Partition Implementation Status
--------------------------------
-
-  No Partitions were found in this design.
-
--------------------------------
-
-=========================================================================
-*                            Final Report                               *
-=========================================================================
-Final Results
-RTL Top Level Output File Name     : gw_wrapper.ngr
-Top Level Output File Name         : gw_wrapper
-Output Format                      : NGC
-Optimization Goal                  : Speed
-Keep Hierarchy                     : No
-
-Design Statistics
-# IOs                              : 273
-
-Cell Usage :
-# BELS                             : 4209
-#      GND                         : 7
-#      INV                         : 140
-#      LUT1                        : 275
-#      LUT2                        : 372
-#      LUT2_D                      : 7
-#      LUT2_L                      : 13
-#      LUT3                        : 755
-#      LUT3_D                      : 10
-#      LUT3_L                      : 9
-#      LUT4                        : 939
-#      LUT4_D                      : 23
-#      LUT4_L                      : 239
-#      MUXCY                       : 791
-#      MUXF5                       : 83
-#      VCC                         : 7
-#      XORCY                       : 539
-# FlipFlops/Latches                : 3857
-#      FD                          : 99
-#      FDC                         : 1089
-#      FDCE                        : 2424
-#      FDDRRSE                     : 1
-#      FDE                         : 66
-#      FDP                         : 94
-#      FDPE                        : 50
-#      IFDDRRSE                    : 18
-#      OFDDRRSE                    : 16
-# RAMS                             : 11
-#      RAMB16BWE                   : 11
-# Shift Registers                  : 5
-#      SRL16                       : 5
-# Clock Buffers                    : 4
-#      BUFG                        : 4
-# IO Buffers                       : 45
-#      IBUF                        : 14
-#      IBUFDS                      : 1
-#      IBUFGDS                     : 2
-#      OBUF                        : 27
-#      OBUFDS                      : 1
-=========================================================================
-
-Device utilization summary:
----------------------------
-
-Selected Device : 3s1400afg484-5 
-
- Number of Slices:                     2669  out of  11264    23%  
- Number of Slice Flip Flops:           3840  out of  22528    17%  
- Number of 4 input LUTs:               2787  out of  22528    12%  
-    Number used as logic:              2782
-    Number used as Shift registers:       5
- Number of IOs:                         273
- Number of bonded IOBs:                  79  out of    375    21%  
-    IOB Flip Flops:                      17
- Number of BRAMs:                        11  out of     32    34%  
- Number of GCLKs:                         4  out of     24    16%  
-
----------------------------
-Partition Resource Summary:
----------------------------
-
-  No Partitions were found in this design.
-
----------------------------
-
-
-=========================================================================
-TIMING REPORT
-
-NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
-      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
-      GENERATED AFTER PLACE-and-ROUTE.
-
-Clock Information:
-------------------
------------------------------------+-----------------------------------------------------------------------------------------------+-------+
-Clock Signal                       | Clock buffer(FF name)                                                                         | Load  |
------------------------------------+-----------------------------------------------------------------------------------------------+-------+
-L_CLKp                             | IBUFDS+BUFG                                                                                   | 1246  |
-cmp_test_ram/BU2/dbiterr           | NONE(cmp_test_ram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[3].ram.r/s3a_init.ram/dpram.ram)| 4     |
-P2L_CLKp                           | IBUFGDS+BUFG                                                                                  | 2616  |
-P2L_CLKn                           | IBUFGDS+BUFG                                                                                  | 53    |
------------------------------------+-----------------------------------------------------------------------------------------------+-------+
-INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
-
-Asynchronous Control Signals Information:
-----------------------------------------
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+-------+
-Control Signal                                                                                                                                                             | Buffer(FF name)                                                                                           | Load  |
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+-------+
-cmp_gn4124_core/rst_n_inv1_INV_0_5(cmp_gn4124_core/rst_n_inv1_INV_0_5:O)                                                                                                   | NONE(cmp_gn4124_core/cmp_p2l_dma_master/completion_error)                                                 | 466   |
-cmp_gn4124_core/rst_n_inv1_INV_0_1(cmp_gn4124_core/rst_n_inv1_INV_0_1:O)                                                                                                   | NONE(cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_attrib_load_o)                      | 465   |
-cmp_gn4124_core/rst_n_inv1_INV_0_2(cmp_gn4124_core/rst_n_inv1_INV_0_2:O)                                                                                                   | NONE(cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/ack_in_progress)                        | 465   |
-cmp_gn4124_core/rst_n_inv1_INV_0_3(cmp_gn4124_core/rst_n_inv1_INV_0_3:O)                                                                                                   | NONE(cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_0)                                                 | 465   |
-cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rst_n_i_inv(cmp_gn4124_core/rst_n_inv1_INV_0:O)                                                               | NONE(cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_10_BRB1)                                           | 463   |
-cmp_gn4124_core/rst_n_inv1_INV_0_4(cmp_gn4124_core/rst_n_inv1_INV_0_4:O)                                                                                                   | NONE(cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_wr)                                                     | 431   |
-L_RST_N_inv(cmp_gn4124_core/rst_n_a_i_inv1_INV_0:O)                                                                                                                        | NONE(cmp_dummy_ctrl_regs/ack_in_progress)                                                                 | 172   |
-cmp_gn4124_core/cmp_l2p_dma_master/cmp_addr_fifo/BU2/U0/grf.rf/rstblk/wr_rst_reg<1>(cmp_gn4124_core/cmp_l2p_dma_master/cmp_addr_fifo/BU2/U0/grf.rf/rstblk/wr_rst_reg_1:Q)  | NONE(cmp_gn4124_core/cmp_l2p_dma_master/cmp_addr_fifo/BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_1) | 45    |
-cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/BU2/U0/grf.rf/rstblk/wr_rst_reg<1>(cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/BU2/U0/grf.rf/rstblk/wr_rst_reg_1:Q)  | NONE(cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_1) | 45    |
-cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/BU2/U0/grf.rf/rstblk/wr_rst_reg<1>(cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/BU2/U0/grf.rf/rstblk/wr_rst_reg_1:Q)| NONE(cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_1)| 45    |
-cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/rstblk/wr_rst_reg<1>(cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/rstblk/wr_rst_reg_1:Q)        | NONE(cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_1)    | 45    |
-cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/BU2/U0/grf.rf/rstblk/wr_rst_reg<1>(cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/BU2/U0/grf.rf/rstblk/wr_rst_reg_1:Q)    | NONE(cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_1)  | 45    |
-cmp_gn4124_core/cmp_l2p_dma_master/cmp_addr_fifo/BU2/U0/grf.rf/rstblk/rd_rst_reg<1>(cmp_gn4124_core/cmp_l2p_dma_master/cmp_addr_fifo/BU2/U0/grf.rf/rstblk/rd_rst_reg_1:Q)  | NONE(cmp_gn4124_core/cmp_l2p_dma_master/cmp_addr_fifo/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_0)                | 36    |
-cmp_gn4124_core/cmp_l2p_dma_master/cmp_addr_fifo/BU2/U0/grf.rf/rstblk/wr_rst_reg<0>(cmp_gn4124_core/cmp_l2p_dma_master/cmp_addr_fifo/BU2/U0/grf.rf/rstblk/wr_rst_reg_0:Q)  | NONE(cmp_gn4124_core/cmp_l2p_dma_master/cmp_addr_fifo/BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_0)               | 36    |
-cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/BU2/U0/grf.rf/rstblk/rd_rst_reg<1>(cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/BU2/U0/grf.rf/rstblk/rd_rst_reg_1:Q)  | NONE(cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_0)                | 36    |
-cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/BU2/U0/grf.rf/rstblk/wr_rst_reg<0>(cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/BU2/U0/grf.rf/rstblk/wr_rst_reg_0:Q)  | NONE(cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_0)               | 36    |
-cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/BU2/U0/grf.rf/rstblk/rd_rst_reg<1>(cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/BU2/U0/grf.rf/rstblk/rd_rst_reg_1:Q)| NONE(cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_0)               | 36    |
-cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/BU2/U0/grf.rf/rstblk/wr_rst_reg<0>(cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/BU2/U0/grf.rf/rstblk/wr_rst_reg_0:Q)| NONE(cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_0)              | 36    |
-cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/rstblk/rd_rst_reg<1>(cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/rstblk/rd_rst_reg_1:Q)        | NONE(cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_0)                   | 36    |
-cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/rstblk/wr_rst_reg<0>(cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/rstblk/wr_rst_reg_0:Q)        | NONE(cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_0)                  | 36    |
-cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/BU2/U0/grf.rf/rstblk/rd_rst_reg<1>(cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/BU2/U0/grf.rf/rstblk/rd_rst_reg_1:Q)    | NONE(cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_0)                 | 36    |
-cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/BU2/U0/grf.rf/rstblk/wr_rst_reg<0>(cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/BU2/U0/grf.rf/rstblk/wr_rst_reg_0:Q)    | NONE(cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_0)                | 36    |
-cmp_gn4124_core/cmp_l2p_dma_master/cmp_addr_fifo/BU2/U0/grf.rf/rstblk/rd_rst_reg<2>(cmp_gn4124_core/cmp_l2p_dma_master/cmp_addr_fifo/BU2/U0/grf.rf/rstblk/rd_rst_reg_2:Q)  | NONE(cmp_gn4124_core/cmp_l2p_dma_master/cmp_addr_fifo/BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i)      | 21    |
-cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/BU2/U0/grf.rf/rstblk/rd_rst_reg<2>(cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/BU2/U0/grf.rf/rstblk/rd_rst_reg_2:Q)  | NONE(cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i)      | 21    |
-cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/BU2/U0/grf.rf/rstblk/rd_rst_reg<2>(cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/BU2/U0/grf.rf/rstblk/rd_rst_reg_2:Q)| NONE(cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i)     | 21    |
-cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/rstblk/rd_rst_reg<2>(cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/rstblk/rd_rst_reg_2:Q)        | NONE(cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i)         | 21    |
-cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/BU2/U0/grf.rf/rstblk/rd_rst_reg<2>(cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/BU2/U0/grf.rf/rstblk/rd_rst_reg_2:Q)    | NONE(cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i)       | 21    |
-cmp_gn4124_core/cmp_l2p_dma_master/cmp_addr_fifo/BU2/U0/grf.rf/rstblk/rd_rst_comb(cmp_gn4124_core/cmp_l2p_dma_master/cmp_addr_fifo/BU2/U0/grf.rf/rstblk/rd_rst_comb1:O)    | NONE(cmp_gn4124_core/cmp_l2p_dma_master/cmp_addr_fifo/BU2/U0/grf.rf/rstblk/rd_rst_reg_0)                  | 3     |
-cmp_gn4124_core/cmp_l2p_dma_master/cmp_addr_fifo/BU2/U0/grf.rf/rstblk/rst_d2(cmp_gn4124_core/cmp_l2p_dma_master/cmp_addr_fifo/BU2/U0/grf.rf/rstblk/rst_d2:Q)               | NONE(cmp_gn4124_core/cmp_l2p_dma_master/cmp_addr_fifo/BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i)     | 3     |
-cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/BU2/U0/grf.rf/rstblk/rd_rst_comb(cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/BU2/U0/grf.rf/rstblk/rd_rst_comb1:O)    | NONE(cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/BU2/U0/grf.rf/rstblk/rd_rst_reg_0)                  | 3     |
-cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/BU2/U0/grf.rf/rstblk/rst_d2(cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/BU2/U0/grf.rf/rstblk/rst_d2:Q)               | NONE(cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i)     | 3     |
-cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/BU2/U0/grf.rf/rstblk/rd_rst_comb(cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/BU2/U0/grf.rf/rstblk/rd_rst_comb1:O)  | NONE(cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/BU2/U0/grf.rf/rstblk/rd_rst_reg_0)                 | 3     |
-cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/BU2/U0/grf.rf/rstblk/rst_d2(cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/BU2/U0/grf.rf/rstblk/rst_d2:Q)             | NONE(cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i)    | 3     |
-cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/rstblk/rd_rst_comb(cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/rstblk/rd_rst_comb1:O)          | NONE(cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/rstblk/rd_rst_reg_0)                     | 3     |
-cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/rstblk/rst_d2(cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/rstblk/rst_d2:Q)                     | NONE(cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i)        | 3     |
-cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/BU2/U0/grf.rf/rstblk/rd_rst_comb(cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/BU2/U0/grf.rf/rstblk/rd_rst_comb1:O)      | NONE(cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/BU2/U0/grf.rf/rstblk/rd_rst_reg_0)                   | 3     |
-cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/BU2/U0/grf.rf/rstblk/rst_d2(cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/BU2/U0/grf.rf/rstblk/rst_d2:Q)                 | NONE(cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i)      | 3     |
-cmp_gn4124_core/cmp_l2p_dma_master/cmp_addr_fifo/BU2/U0/grf.rf/rstblk/wr_rst_comb(cmp_gn4124_core/cmp_l2p_dma_master/cmp_addr_fifo/BU2/U0/grf.rf/rstblk/wr_rst_comb1:O)    | NONE(cmp_gn4124_core/cmp_l2p_dma_master/cmp_addr_fifo/BU2/U0/grf.rf/rstblk/wr_rst_reg_0)                  | 2     |
-cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/BU2/U0/grf.rf/rstblk/wr_rst_comb(cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/BU2/U0/grf.rf/rstblk/wr_rst_comb1:O)    | NONE(cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/BU2/U0/grf.rf/rstblk/wr_rst_reg_0)                  | 2     |
-cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/BU2/U0/grf.rf/rstblk/wr_rst_comb(cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/BU2/U0/grf.rf/rstblk/wr_rst_comb1:O)  | NONE(cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/BU2/U0/grf.rf/rstblk/wr_rst_reg_0)                 | 2     |
-cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/rstblk/wr_rst_comb(cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/rstblk/wr_rst_comb1:O)          | NONE(cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/rstblk/wr_rst_reg_0)                     | 2     |
-cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/BU2/U0/grf.rf/rstblk/wr_rst_comb(cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/BU2/U0/grf.rf/rstblk/wr_rst_comb1:O)      | NONE(cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/BU2/U0/grf.rf/rstblk/wr_rst_reg_0)                   | 2     |
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+-------+
-
-Timing Summary:
----------------
-Speed Grade: -5
-
-   Minimum period: 7.682ns (Maximum Frequency: 130.175MHz)
-   Minimum input arrival time before clock: 2.030ns
-   Maximum output required time after clock: 6.668ns
-   Maximum combinational path delay: No path found
-
-Timing Detail:
---------------
-All values displayed in nanoseconds (ns)
-
-=========================================================================
-Timing constraint: Default period analysis for Clock 'L_CLKp'
-  Clock period: 7.682ns (frequency: 130.175MHz)
-  Total number of paths / destination ports: 13373 / 2304
--------------------------------------------------------------------------
-Delay:               7.682ns (Levels of Logic = 35)
-  Source:            cmp_gn4124_core/cmp_p2l_dma_master/wb_write_cnt_0 (FF)
-  Destination:       cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_cyc_t (FF)
-  Source Clock:      L_CLKp rising
-  Destination Clock: L_CLKp rising
-
-  Data Path: cmp_gn4124_core/cmp_p2l_dma_master/wb_write_cnt_0 to cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_cyc_t
-                                Gate     Net
-    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
-    ----------------------------------------  ------------
-     FDCE:C->Q             2   0.495   0.488  cmp_gn4124_core/cmp_p2l_dma_master/wb_write_cnt_0 (cmp_gn4124_core/cmp_p2l_dma_master/wb_write_cnt_0)
-     LUT1:I0->O            1   0.561   0.000  cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<0>_rt (cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<0>_rt)
-     MUXCY:S->O            1   0.523   0.000  cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<0> (cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<0>)
-     MUXCY:CI->O           1   0.065   0.000  cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<1> (cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<1>)
-     MUXCY:CI->O           1   0.065   0.000  cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<2> (cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<2>)
-     MUXCY:CI->O           1   0.065   0.000  cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<3> (cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<3>)
-     MUXCY:CI->O           1   0.065   0.000  cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<4> (cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<4>)
-     MUXCY:CI->O           1   0.065   0.000  cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<5> (cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<5>)
-     MUXCY:CI->O           1   0.065   0.000  cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<6> (cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<6>)
-     MUXCY:CI->O           1   0.065   0.000  cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<7> (cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<7>)
-     MUXCY:CI->O           1   0.065   0.000  cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<8> (cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<8>)
-     MUXCY:CI->O           1   0.065   0.000  cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<9> (cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<9>)
-     MUXCY:CI->O           1   0.065   0.000  cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<10> (cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<10>)
-     MUXCY:CI->O           1   0.065   0.000  cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<11> (cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<11>)
-     MUXCY:CI->O           1   0.065   0.000  cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<12> (cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<12>)
-     MUXCY:CI->O           1   0.065   0.000  cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<13> (cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<13>)
-     MUXCY:CI->O           1   0.065   0.000  cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<14> (cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<14>)
-     MUXCY:CI->O           1   0.065   0.000  cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<15> (cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<15>)
-     MUXCY:CI->O           1   0.065   0.000  cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<16> (cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<16>)
-     MUXCY:CI->O           1   0.065   0.000  cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<17> (cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<17>)
-     MUXCY:CI->O           1   0.065   0.000  cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<18> (cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<18>)
-     MUXCY:CI->O           1   0.065   0.000  cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<19> (cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<19>)
-     MUXCY:CI->O           1   0.065   0.000  cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<20> (cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<20>)
-     MUXCY:CI->O           1   0.065   0.000  cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<21> (cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<21>)
-     MUXCY:CI->O           1   0.065   0.000  cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<22> (cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<22>)
-     MUXCY:CI->O           1   0.065   0.000  cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<23> (cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<23>)
-     MUXCY:CI->O           1   0.065   0.000  cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<24> (cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<24>)
-     MUXCY:CI->O           1   0.065   0.000  cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<25> (cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<25>)
-     MUXCY:CI->O           1   0.065   0.000  cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<26> (cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<26>)
-     MUXCY:CI->O           1   0.065   0.000  cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<27> (cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<27>)
-     MUXCY:CI->O           1   0.065   0.000  cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<28> (cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<28>)
-     MUXCY:CI->O           1   0.065   0.000  cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<29> (cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<29>)
-     MUXCY:CI->O           0   0.065   0.000  cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<30> (cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_cy<30>)
-     XORCY:CI->O           1   0.654   0.359  cmp_gn4124_core/cmp_p2l_dma_master/Msub_p2l_dma_cyc_t_addsub0000_xor<31> (cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_cyc_t_addsub0000<31>)
-     LUT4:I3->O            1   0.561   0.000  cmp_gn4124_core/cmp_p2l_dma_master/Mcompar_p2l_dma_cyc_t_cmp_eq0000_lut<15> (cmp_gn4124_core/cmp_p2l_dma_master/Mcompar_p2l_dma_cyc_t_cmp_eq0000_lut<15>)
-     MUXCY:S->O            1   0.637   0.380  cmp_gn4124_core/cmp_p2l_dma_master/Mcompar_p2l_dma_cyc_t_cmp_eq0000_cy<15> (cmp_gn4124_core/cmp_p2l_dma_master/Mcompar_p2l_dma_cyc_t_cmp_eq0000_cy<15>)
-     LUT3:I2->O            1   0.561   0.357  cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_cyc_t_not00011 (cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_cyc_t_not0001)
-     FDCE:CE                   0.156          cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_cyc_t
-    ----------------------------------------
-    Total                      7.682ns (6.098ns logic, 1.584ns route)
-                                       (79.4% logic, 20.6% route)
-
-=========================================================================
-Timing constraint: Default period analysis for Clock 'P2L_CLKp'
-  Clock period: 6.300ns (frequency: 158.734MHz)
-  Total number of paths / destination ports: 25073 / 4114
--------------------------------------------------------------------------
-Delay:               6.300ns (Levels of Logic = 5)
-  Source:            cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_current_state_FSM_FFd7 (FF)
-  Destination:       cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_10 (FF)
-  Source Clock:      P2L_CLKp rising
-  Destination Clock: P2L_CLKp rising
-
-  Data Path: cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_current_state_FSM_FFd7 to cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_10
-                                Gate     Net
-    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
-    ----------------------------------------  ------------
-     FDC:C->Q             45   0.495   1.078  cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_current_state_FSM_FFd7 (cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_current_state_FSM_FFd7)
-     LUT4_D:I3->O          2   0.561   0.382  cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_req_o_mux0000121 (cmp_gn4124_core/cmp_l2p_dma_master/N49)
-     LUT4_L:I3->LO         1   0.561   0.102  cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_mux0000<0>1_SW0 (N257)
-     LUT4:I3->O           27   0.561   1.138  cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_mux0000<0>1 (cmp_gn4124_core/cmp_l2p_dma_master/N0)
-     LUT2_L:I1->LO         1   0.562   0.102  cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_mux0000<31>5 (cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_mux0000<31>5)
-     LUT4:I3->O            1   0.561   0.000  cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_mux0000<31>14 (cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_mux0000<31>)
-     FDC:D                     0.197          cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_31
-    ----------------------------------------
-    Total                      6.300ns (3.498ns logic, 2.802ns route)
-                                       (55.5% logic, 44.5% route)
-
-=========================================================================
-Timing constraint: Default OFFSET IN BEFORE for Clock 'L_CLKp'
-  Total number of paths / destination ports: 8 / 8
--------------------------------------------------------------------------
-Offset:              2.030ns (Levels of Logic = 2)
-  Source:            DEBUG<7> (PAD)
-  Destination:       cmp_dummy_stat_regs/rddata_reg_7 (FF)
-  Destination Clock: L_CLKp rising
-
-  Data Path: DEBUG<7> to cmp_dummy_stat_regs/rddata_reg_7
-                                Gate     Net
-    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
-    ----------------------------------------  ------------
-     IBUF:I->O             1   0.824   0.357  DEBUG_7_IBUF (DEBUG_7_IBUF)
-     MUXF5:S->O            1   0.652   0.000  cmp_dummy_stat_regs/Mmux_rddata_reg_mux000054_f5 (cmp_dummy_stat_regs/rddata_reg_mux0000<7>)
-     FDCE:D                    0.197          cmp_dummy_stat_regs/rddata_reg_7
-    ----------------------------------------
-    Total                      2.030ns (1.673ns logic, 0.357ns route)
-                                       (82.4% logic, 17.6% route)
-
-=========================================================================
-Timing constraint: Default OFFSET IN BEFORE for Clock 'P2L_CLKn'
-  Total number of paths / destination ports: 18 / 18
--------------------------------------------------------------------------
-Offset:              1.021ns (Levels of Logic = 0)
-  Source:            P2L_DATA<15> (PAD)
-  Destination:       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[15].U (UNKNOWN)
-  Destination Clock: P2L_CLKn rising
-
-  Data Path: P2L_DATA<15> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[15].U
-                                Gate     Net
-    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
-    ----------------------------------------  ------------
-     IFDDRRSE:D                1.021          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[15].U
-    ----------------------------------------
-    Total                      1.021ns (1.021ns logic, 0.000ns route)
-                                       (100.0% logic, 0.0% route)
-
-=========================================================================
-Timing constraint: Default OFFSET IN BEFORE for Clock 'P2L_CLKp'
-  Total number of paths / destination ports: 5 / 5
--------------------------------------------------------------------------
-Offset:              1.378ns (Levels of Logic = 1)
-  Source:            L_WR_RDY<1> (PAD)
-  Destination:       cmp_gn4124_core/l_wr_rdy_t_1 (FF)
-  Destination Clock: P2L_CLKp rising
-
-  Data Path: L_WR_RDY<1> to cmp_gn4124_core/l_wr_rdy_t_1
-                                Gate     Net
-    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
-    ----------------------------------------  ------------
-     IBUF:I->O             1   0.824   0.357  L_WR_RDY_1_IBUF (L_WR_RDY_1_IBUF)
-     FDC:D                     0.197          cmp_gn4124_core/l_wr_rdy_t_1
-    ----------------------------------------
-    Total                      1.378ns (1.021ns logic, 0.357ns route)
-                                       (74.1% logic, 25.9% route)
-
-=========================================================================
-Timing constraint: Default OFFSET OUT AFTER for Clock 'P2L_CLKp'
-  Total number of paths / destination ports: 8 / 6
--------------------------------------------------------------------------
-Offset:              6.297ns (Levels of Logic = 2)
-  Source:            cmp_gn4124_core/cmp_dma_controller/dma_done_irq (FF)
-  Destination:       GPIO<8> (PAD)
-  Source Clock:      P2L_CLKp rising
-
-  Data Path: cmp_gn4124_core/cmp_dma_controller/dma_done_irq to GPIO<8>
-                                Gate     Net
-    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
-    ----------------------------------------  ------------
-     FDC:C->Q              2   0.495   0.488  cmp_gn4124_core/cmp_dma_controller/dma_done_irq (cmp_gn4124_core/cmp_dma_controller/dma_done_irq)
-     LUT3:I0->O            1   0.561   0.357  irq_to_gn41241 (irq_to_gn4124)
-     OBUF:I->O                 4.396          GPIO_8_OBUF (GPIO<8>)
-    ----------------------------------------
-    Total                      6.297ns (5.452ns logic, 0.845ns route)
-                                       (86.6% logic, 13.4% route)
-
-=========================================================================
-Timing constraint: Default OFFSET OUT AFTER for Clock 'L_CLKp'
-  Total number of paths / destination ports: 9 / 9
--------------------------------------------------------------------------
-Offset:              6.668ns (Levels of Logic = 2)
-  Source:            cmp_gn4124_core/cmp_wbmaster32/wb_dat_o_t_0 (FF)
-  Destination:       GPIO<8> (PAD)
-  Source Clock:      L_CLKp rising
-
-  Data Path: cmp_gn4124_core/cmp_wbmaster32/wb_dat_o_t_0 to GPIO<8>
-                                Gate     Net
-    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
-    ----------------------------------------  ------------
-     FDCE:C->Q            13   0.495   0.859  cmp_gn4124_core/cmp_wbmaster32/wb_dat_o_t_0 (cmp_gn4124_core/cmp_wbmaster32/wb_dat_o_t_0)
-     LUT3:I2->O            1   0.561   0.357  irq_to_gn41241 (irq_to_gn4124)
-     OBUF:I->O                 4.396          GPIO_8_OBUF (GPIO<8>)
-    ----------------------------------------
-    Total                      6.668ns (5.452ns logic, 1.216ns route)
-                                       (81.8% logic, 18.2% route)
-
-=========================================================================
-Timing constraint: Default OFFSET OUT AFTER for Clock 'P2L_CLKn'
-  Total number of paths / destination ports: 20 / 20
--------------------------------------------------------------------------
-Offset:              5.248ns (Levels of Logic = 1)
-  Source:            cmp_gn4124_core/cmp_l2p_ser/l2p_valid_o (FF)
-  Destination:       L2P_VALID (PAD)
-  Source Clock:      P2L_CLKn rising
-
-  Data Path: cmp_gn4124_core/cmp_l2p_ser/l2p_valid_o to L2P_VALID
-                                Gate     Net
-    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
-    ----------------------------------------  ------------
-     FDC:C->Q              1   0.495   0.357  cmp_gn4124_core/cmp_l2p_ser/l2p_valid_o (cmp_gn4124_core/cmp_l2p_ser/l2p_valid_o)
-     OBUF:I->O                 4.396          L2P_VALID_OBUF (L2P_VALID)
-    ----------------------------------------
-    Total                      5.248ns (4.891ns logic, 0.357ns route)
-                                       (93.2% logic, 6.8% route)
-
-=========================================================================
-
-
-Total REAL time to Xst completion: 137.00 secs
-Total CPU time to Xst completion: 132.48 secs
- 
---> 
-
-
-Total memory usage is 205136 kilobytes
-
-Number of errors   :    0 (   0 filtered)
-Number of warnings :  466 (   0 filtered)
-Number of infos    :   85 (   0 filtered)
-
diff --git a/hdl/gullwing/ise_project/gw_wrapper.twr b/hdl/gullwing/ise_project/gw_wrapper.twr
deleted file mode 100644
index 02eaff2c0ead2454c112190694e920b4697c5722..0000000000000000000000000000000000000000
--- a/hdl/gullwing/ise_project/gw_wrapper.twr
+++ /dev/null
@@ -1,15554 +0,0 @@
---------------------------------------------------------------------------------
-Release 12.2 Trace  (lin)
-Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
-
-/opt/Xilinx/12.2/ISE_DS/ISE/bin/lin/unwrapped/trce -intstyle ise -v 3 -s 5 -n 3
--fastpaths -xml gw_wrapper.twx gw_wrapper.ncd -o gw_wrapper.twr gw_wrapper.pcf
-
-Design file:              gw_wrapper.ncd
-Physical constraint file: gw_wrapper.pcf
-Device,package,speed:     xc3s1400a,fg484,-5 (PRODUCTION 1.41 2010-06-22)
-Report level:             verbose report
-
-Environment Variable      Effect 
---------------------      ------ 
-NONE                      No environment variables were set
---------------------------------------------------------------------------------
-
-INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more 
-   information, see the TSI report.  Please consult the Xilinx Command Line 
-   Tools User Guide for information on generating a TSI report.
-INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
-   option. All paths that are not constrained will be reported in the 
-   unconstrained paths section(s) of the report.
-INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
-   a 50 Ohm transmission line loading model.  For the details of this model, 
-   and for more information on accounting for different loading conditions, 
-   please see the device datasheet.
-INFO:Timing:3390 - This architecture does not support a default System Jitter 
-   value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock 
-   Uncertainty calculation.
-INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and 
-   'Phase Error' calculations, these terms will be zero in the Clock 
-   Uncertainty calculation.  Please make appropriate modification to 
-   SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase 
-   Error.
-
-================================================================================
-Timing constraint: NET "L_WR_RDY<1>/L_WR_RDY_1_IBUF" MAXDELAY = 2 ns;
-
- 0 nets analyzed, 0 failing nets detected.
- 0 timing errors detected.
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: NET "L_WR_RDY<1>/L_WR_RDY_1_IBUF" MAXDELAY = 2 ns;
-
- 0 nets analyzed, 0 failing nets detected.
- 0 timing errors detected.
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: NET "L_WR_RDY<0>/L_WR_RDY_0_IBUF" MAXDELAY = 2 ns;
-
- 0 nets analyzed, 0 failing nets detected.
- 0 timing errors detected.
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: NET "L_WR_RDY<0>/L_WR_RDY_0_IBUF" MAXDELAY = 2 ns;
-
- 0 nets analyzed, 0 failing nets detected.
- 0 timing errors detected.
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: NET "L2P_RDY/L2P_RDY_IBUF" MAXDELAY = 2 ns;
-
- 0 nets analyzed, 0 failing nets detected.
- 0 timing errors detected.
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: NET "P_RD_D_RDY<1>/P_RD_D_RDY_1_IBUF" MAXDELAY = 2 ns;
-
- 0 nets analyzed, 0 failing nets detected.
- 0 timing errors detected.
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: NET "P_RD_D_RDY<0>/P_RD_D_RDY_0_IBUF" MAXDELAY = 2 ns;
-
- 0 nets analyzed, 0 failing nets detected.
- 0 timing errors detected.
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: NET "VC_RDY<1>_IBUF" MAXDELAY = 2 ns;
-
- 0 nets analyzed, 0 failing nets detected.
- 0 timing errors detected.
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: NET "VC_RDY<1>_IBUF" MAXDELAY = 2 ns;
-
- 1 net analyzed, 0 failing nets detected.
- 0 timing errors detected.
- Maximum net delay is   0.000ns.
---------------------------------------------------------------------------------
-Slack:                  2.000ns VC_RDY<1>_IBUF
-Report:    0.000ns delay meets   2.000ns timing constraint by 2.000ns
-From                              To                                Delay(ns)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: NET "VC_RDY<0>_IBUF" MAXDELAY = 2 ns;
-
- 0 nets analyzed, 0 failing nets detected.
- 0 timing errors detected.
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: NET "VC_RDY<0>_IBUF" MAXDELAY = 2 ns;
-
- 1 net analyzed, 0 failing nets detected.
- 0 timing errors detected.
- Maximum net delay is   0.000ns.
---------------------------------------------------------------------------------
-Slack:                  2.000ns VC_RDY<0>_IBUF
-Report:    0.000ns delay meets   2.000ns timing constraint by 2.000ns
-From                              To                                Delay(ns)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: NET "cmp_gn4124_core/clk_n_buf" MAXDELAY = 0.1 ns;
-
- 1 net analyzed, 0 failing nets detected.
- 0 timing errors detected.
- Maximum net delay is   0.022ns.
---------------------------------------------------------------------------------
-Slack:                  0.078ns cmp_gn4124_core/clk_n_buf
-Report:    0.022ns delay meets   0.100ns timing constraint by 0.078ns
-From                              To                                Delay(ns)
-E12.I                             BUFGMUX_X2Y11.I0                      0.022  
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: NET "cmp_gn4124_core/clk_p_buf" MAXDELAY = 0.1 ns;
-
- 1 net analyzed, 0 failing nets detected.
- 0 timing errors detected.
- Maximum net delay is   0.022ns.
---------------------------------------------------------------------------------
-Slack:                  0.078ns cmp_gn4124_core/clk_p_buf
-Report:    0.022ns delay meets   0.100ns timing constraint by 0.078ns
-From                              To                                Delay(ns)
-C12.I                             BUFGMUX_X2Y10.I0                      0.022  
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TS_U_TO_J = MAXDELAY FROM TIMEGRP "U_CLK" TO TIMEGRP "J_CLK" 
-15 ns;
-
- 18 paths analyzed, 18 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors)
- Maximum delay is   4.946ns.
---------------------------------------------------------------------------------
-
-Paths for end point U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[8].I_NE0.U_TARGET (SLICE_X67Y110.CE), 1 path
---------------------------------------------------------------------------------
-Slack (setup paths):    10.054ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               U_icon_pro/U0/U_ICON/U_iDATA_CMD (FF)
-  Destination:          U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[8].I_NE0.U_TARGET (FF)
-  Requirement:          15.000ns
-  Data Path Delay:      4.946ns (Levels of Logic = 1)
-  Clock Path Skew:      0.000ns
-  Source Clock:         U_icon_pro/U0/iUPDATE_OUT rising
-  Destination Clock:    icon_control0<0> rising at 0.000ns
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: U_icon_pro/U0/U_ICON/U_iDATA_CMD to U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[8].I_NE0.U_TARGET
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X78Y143.YQ     Tcko                  0.596   U_icon_pro/U0/U_ICON/iDATA_CMD
-                                                       U_icon_pro/U0/U_ICON/U_iDATA_CMD
-    SLICE_X75Y120.G2     net (fanout=8)        2.260   U_icon_pro/U0/U_ICON/iDATA_CMD
-    SLICE_X75Y120.Y      Tilo                  0.561   U_icon_pro/U0/U_ICON/U_CMD/iTARGET_CE
-                                                       U_icon_pro/U0/U_ICON/U_CMD/U_TARGET_CE
-    SLICE_X67Y110.CE     net (fanout=7)        1.374   U_icon_pro/U0/U_ICON/U_CMD/iTARGET_CE
-    SLICE_X67Y110.CLK    Tceck                 0.155   U_icon_pro/U0/U_ICON/U_CMD/iTARGET<8>
-                                                       U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[8].I_NE0.U_TARGET
-    -------------------------------------------------  ---------------------------
-    Total                                      4.946ns (1.312ns logic, 3.634ns route)
-                                                       (26.5% logic, 73.5% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[10].I_NE0.U_TARGET (SLICE_X67Y110.CE), 1 path
---------------------------------------------------------------------------------
-Slack (setup paths):    10.054ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               U_icon_pro/U0/U_ICON/U_iDATA_CMD (FF)
-  Destination:          U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[10].I_NE0.U_TARGET (FF)
-  Requirement:          15.000ns
-  Data Path Delay:      4.946ns (Levels of Logic = 1)
-  Clock Path Skew:      0.000ns
-  Source Clock:         U_icon_pro/U0/iUPDATE_OUT rising
-  Destination Clock:    icon_control0<0> rising at 0.000ns
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: U_icon_pro/U0/U_ICON/U_iDATA_CMD to U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[10].I_NE0.U_TARGET
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X78Y143.YQ     Tcko                  0.596   U_icon_pro/U0/U_ICON/iDATA_CMD
-                                                       U_icon_pro/U0/U_ICON/U_iDATA_CMD
-    SLICE_X75Y120.G2     net (fanout=8)        2.260   U_icon_pro/U0/U_ICON/iDATA_CMD
-    SLICE_X75Y120.Y      Tilo                  0.561   U_icon_pro/U0/U_ICON/U_CMD/iTARGET_CE
-                                                       U_icon_pro/U0/U_ICON/U_CMD/U_TARGET_CE
-    SLICE_X67Y110.CE     net (fanout=7)        1.374   U_icon_pro/U0/U_ICON/U_CMD/iTARGET_CE
-    SLICE_X67Y110.CLK    Tceck                 0.155   U_icon_pro/U0/U_ICON/U_CMD/iTARGET<8>
-                                                       U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[10].I_NE0.U_TARGET
-    -------------------------------------------------  ---------------------------
-    Total                                      4.946ns (1.312ns logic, 3.634ns route)
-                                                       (26.5% logic, 73.5% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[9].I_NE0.U_TARGET (SLICE_X68Y111.CE), 1 path
---------------------------------------------------------------------------------
-Slack (setup paths):    10.305ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               U_icon_pro/U0/U_ICON/U_iDATA_CMD (FF)
-  Destination:          U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[9].I_NE0.U_TARGET (FF)
-  Requirement:          15.000ns
-  Data Path Delay:      4.695ns (Levels of Logic = 1)
-  Clock Path Skew:      0.000ns
-  Source Clock:         U_icon_pro/U0/iUPDATE_OUT rising
-  Destination Clock:    icon_control0<0> rising at 0.000ns
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: U_icon_pro/U0/U_ICON/U_iDATA_CMD to U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[9].I_NE0.U_TARGET
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X78Y143.YQ     Tcko                  0.596   U_icon_pro/U0/U_ICON/iDATA_CMD
-                                                       U_icon_pro/U0/U_ICON/U_iDATA_CMD
-    SLICE_X75Y120.G2     net (fanout=8)        2.260   U_icon_pro/U0/U_ICON/iDATA_CMD
-    SLICE_X75Y120.Y      Tilo                  0.561   U_icon_pro/U0/U_ICON/U_CMD/iTARGET_CE
-                                                       U_icon_pro/U0/U_ICON/U_CMD/U_TARGET_CE
-    SLICE_X68Y111.CE     net (fanout=7)        1.123   U_icon_pro/U0/U_ICON/U_CMD/iTARGET_CE
-    SLICE_X68Y111.CLK    Tceck                 0.155   U_icon_pro/U0/U_ICON/U_CMD/iTARGET<9>
-                                                       U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[9].I_NE0.U_TARGET
-    -------------------------------------------------  ---------------------------
-    Total                                      4.695ns (1.312ns logic, 3.383ns route)
-                                                       (27.9% logic, 72.1% route)
-
---------------------------------------------------------------------------------
-Hold Paths: TS_U_TO_J = MAXDELAY FROM TIMEGRP "U_CLK" TO TIMEGRP "J_CLK" 15 ns;
---------------------------------------------------------------------------------
-
-Paths for end point U_icon_pro/U0/U_ICON/U_SYNC/G_SYNC_WORD[1].I_NE0.U_FDR (SLICE_X69Y126.SR), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      1.952ns (requirement - (clock path skew + uncertainty - data path))
-  Source:               U_icon_pro/U0/U_ICON/U_iDATA_CMD (FF)
-  Destination:          U_icon_pro/U0/U_ICON/U_SYNC/G_SYNC_WORD[1].I_NE0.U_FDR (FF)
-  Requirement:          0.000ns
-  Data Path Delay:      1.952ns (Levels of Logic = 0)
-  Positive Clock Path Skew: 0.000ns
-  Source Clock:         U_icon_pro/U0/iUPDATE_OUT rising
-  Destination Clock:    icon_control0<0> rising at 0.000ns
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: U_icon_pro/U0/U_ICON/U_iDATA_CMD to U_icon_pro/U0/U_ICON/U_SYNC/G_SYNC_WORD[1].I_NE0.U_FDR
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X78Y143.YQ     Tcko                  0.477   U_icon_pro/U0/U_ICON/iDATA_CMD
-                                                       U_icon_pro/U0/U_ICON/U_iDATA_CMD
-    SLICE_X69Y126.SR     net (fanout=8)        1.185   U_icon_pro/U0/U_ICON/iDATA_CMD
-    SLICE_X69Y126.CLK    Tcksr       (-Th)    -0.290   U_icon_pro/U0/U_ICON/U_SYNC/iSYNC_WORD<1>
-                                                       U_icon_pro/U0/U_ICON/U_SYNC/G_SYNC_WORD[1].I_NE0.U_FDR
-    -------------------------------------------------  ---------------------------
-    Total                                      1.952ns (0.767ns logic, 1.185ns route)
-                                                       (39.3% logic, 60.7% route)
---------------------------------------------------------------------------------
-
-Paths for end point U_icon_pro/U0/U_ICON/U_SYNC/G_SYNC_WORD[0].I_NE0.U_FDR (SLICE_X69Y126.SR), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      1.952ns (requirement - (clock path skew + uncertainty - data path))
-  Source:               U_icon_pro/U0/U_ICON/U_iDATA_CMD (FF)
-  Destination:          U_icon_pro/U0/U_ICON/U_SYNC/G_SYNC_WORD[0].I_NE0.U_FDR (FF)
-  Requirement:          0.000ns
-  Data Path Delay:      1.952ns (Levels of Logic = 0)
-  Positive Clock Path Skew: 0.000ns
-  Source Clock:         U_icon_pro/U0/iUPDATE_OUT rising
-  Destination Clock:    icon_control0<0> rising at 0.000ns
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: U_icon_pro/U0/U_ICON/U_iDATA_CMD to U_icon_pro/U0/U_ICON/U_SYNC/G_SYNC_WORD[0].I_NE0.U_FDR
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X78Y143.YQ     Tcko                  0.477   U_icon_pro/U0/U_ICON/iDATA_CMD
-                                                       U_icon_pro/U0/U_ICON/U_iDATA_CMD
-    SLICE_X69Y126.SR     net (fanout=8)        1.185   U_icon_pro/U0/U_ICON/iDATA_CMD
-    SLICE_X69Y126.CLK    Tcksr       (-Th)    -0.290   U_icon_pro/U0/U_ICON/U_SYNC/iSYNC_WORD<1>
-                                                       U_icon_pro/U0/U_ICON/U_SYNC/G_SYNC_WORD[0].I_NE0.U_FDR
-    -------------------------------------------------  ---------------------------
-    Total                                      1.952ns (0.767ns logic, 1.185ns route)
-                                                       (39.3% logic, 60.7% route)
---------------------------------------------------------------------------------
-
-Paths for end point U_icon_pro/U0/U_ICON/U_SYNC/G_SYNC_WORD[3].I_NE0.U_FDR (SLICE_X69Y127.SR), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      1.952ns (requirement - (clock path skew + uncertainty - data path))
-  Source:               U_icon_pro/U0/U_ICON/U_iDATA_CMD (FF)
-  Destination:          U_icon_pro/U0/U_ICON/U_SYNC/G_SYNC_WORD[3].I_NE0.U_FDR (FF)
-  Requirement:          0.000ns
-  Data Path Delay:      1.952ns (Levels of Logic = 0)
-  Positive Clock Path Skew: 0.000ns
-  Source Clock:         U_icon_pro/U0/iUPDATE_OUT rising
-  Destination Clock:    icon_control0<0> rising at 0.000ns
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: U_icon_pro/U0/U_ICON/U_iDATA_CMD to U_icon_pro/U0/U_ICON/U_SYNC/G_SYNC_WORD[3].I_NE0.U_FDR
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X78Y143.YQ     Tcko                  0.477   U_icon_pro/U0/U_ICON/iDATA_CMD
-                                                       U_icon_pro/U0/U_ICON/U_iDATA_CMD
-    SLICE_X69Y127.SR     net (fanout=8)        1.185   U_icon_pro/U0/U_ICON/iDATA_CMD
-    SLICE_X69Y127.CLK    Tcksr       (-Th)    -0.290   U_icon_pro/U0/U_ICON/U_SYNC/iSYNC_WORD<3>
-                                                       U_icon_pro/U0/U_ICON/U_SYNC/G_SYNC_WORD[3].I_NE0.U_FDR
-    -------------------------------------------------  ---------------------------
-    Total                                      1.952ns (0.767ns logic, 1.185ns route)
-                                                       (39.3% logic, 60.7% route)
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TS_U_TO_U = MAXDELAY FROM TIMEGRP "U_CLK" TO TIMEGRP "U_CLK" 
-15 ns;
-
- 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors)
- Maximum delay is   1.303ns.
---------------------------------------------------------------------------------
-
-Paths for end point U_icon_pro/U0/U_ICON/U_iDATA_CMD (SLICE_X78Y143.BY), 1 path
---------------------------------------------------------------------------------
-Slack (setup paths):    13.697ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               U_icon_pro/U0/U_ICON/U_iDATA_CMD (FF)
-  Destination:          U_icon_pro/U0/U_ICON/U_iDATA_CMD (FF)
-  Requirement:          15.000ns
-  Data Path Delay:      1.303ns (Levels of Logic = 0)
-  Clock Path Skew:      0.000ns
-  Source Clock:         U_icon_pro/U0/iUPDATE_OUT rising
-  Destination Clock:    U_icon_pro/U0/iUPDATE_OUT rising
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: U_icon_pro/U0/U_ICON/U_iDATA_CMD to U_icon_pro/U0/U_ICON/U_iDATA_CMD
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X78Y143.YQ     Tcko                  0.596   U_icon_pro/U0/U_ICON/iDATA_CMD
-                                                       U_icon_pro/U0/U_ICON/U_iDATA_CMD
-    SLICE_X78Y143.BY     net (fanout=8)        0.427   U_icon_pro/U0/U_ICON/iDATA_CMD
-    SLICE_X78Y143.CLK    Tdick                 0.280   U_icon_pro/U0/U_ICON/iDATA_CMD
-                                                       U_icon_pro/U0/U_ICON/U_iDATA_CMD
-    -------------------------------------------------  ---------------------------
-    Total                                      1.303ns (0.876ns logic, 0.427ns route)
-                                                       (67.2% logic, 32.8% route)
-
---------------------------------------------------------------------------------
-Hold Paths: TS_U_TO_U = MAXDELAY FROM TIMEGRP "U_CLK" TO TIMEGRP "U_CLK" 15 ns;
---------------------------------------------------------------------------------
-
-Paths for end point U_icon_pro/U0/U_ICON/U_iDATA_CMD (SLICE_X78Y143.BY), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.955ns (requirement - (clock path skew + uncertainty - data path))
-  Source:               U_icon_pro/U0/U_ICON/U_iDATA_CMD (FF)
-  Destination:          U_icon_pro/U0/U_ICON/U_iDATA_CMD (FF)
-  Requirement:          0.000ns
-  Data Path Delay:      0.955ns (Levels of Logic = 0)
-  Positive Clock Path Skew: 0.000ns
-  Source Clock:         U_icon_pro/U0/iUPDATE_OUT rising
-  Destination Clock:    U_icon_pro/U0/iUPDATE_OUT rising
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: U_icon_pro/U0/U_ICON/U_iDATA_CMD to U_icon_pro/U0/U_ICON/U_iDATA_CMD
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X78Y143.YQ     Tcko                  0.477   U_icon_pro/U0/U_ICON/iDATA_CMD
-                                                       U_icon_pro/U0/U_ICON/U_iDATA_CMD
-    SLICE_X78Y143.BY     net (fanout=8)        0.341   U_icon_pro/U0/U_ICON/iDATA_CMD
-    SLICE_X78Y143.CLK    Tckdi       (-Th)    -0.137   U_icon_pro/U0/U_ICON/iDATA_CMD
-                                                       U_icon_pro/U0/U_ICON/U_iDATA_CMD
-    -------------------------------------------------  ---------------------------
-    Total                                      0.955ns (0.614ns logic, 0.341ns route)
-                                                       (64.3% logic, 35.7% route)
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: PATH "TS_J_TO_D_path" TIG;
-
- 528 paths analyzed, 171 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors)
---------------------------------------------------------------------------------
-
-Paths for end point U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.U_MCNT/G[0].U_FDRE (SLICE_X51Y71.CE), 3 paths
---------------------------------------------------------------------------------
-Delay (setup path):     6.457ns (data path - clock path skew + uncertainty)
-  Source:               U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL (FF)
-  Destination:          U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.U_MCNT/G[0].U_FDRE (FF)
-  Data Path Delay:      6.457ns (Levels of Logic = 1)
-  Clock Path Skew:      0.000ns
-  Source Clock:         icon_control0<0> rising
-  Destination Clock:    cmp_gn4124_core/clk_p rising
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL to U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.U_MCNT/G[0].U_FDRE
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X50Y72.COUT    Twosco                3.614   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH/O
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL.CE
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXL
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH
-    SLICE_X48Y71.F2      net (fanout=3)        1.084   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH/O
-    SLICE_X48Y71.X       Tilo                  0.601   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/MCNT_en
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.I_MCNT_en_SRLC16.U_MCNT_en
-    SLICE_X51Y71.CE      net (fanout=4)        1.003   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/MCNT_en
-    SLICE_X51Y71.CLK     Tceck                 0.155   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/MCNT<0>
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.U_MCNT/G[0].U_FDRE
-    -------------------------------------------------  ---------------------------
-    Total                                      6.457ns (4.370ns logic, 2.087ns route)
-                                                       (67.7% logic, 32.3% route)
-
---------------------------------------------------------------------------------
-Delay (setup path):     6.451ns (data path - clock path skew + uncertainty)
-  Source:               U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH (FF)
-  Destination:          U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.U_MCNT/G[0].U_FDRE (FF)
-  Data Path Delay:      6.451ns (Levels of Logic = 1)
-  Clock Path Skew:      0.000ns
-  Source Clock:         icon_control0<0> rising
-  Destination Clock:    cmp_gn4124_core/clk_p rising
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH to U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.U_MCNT/G[0].U_FDRE
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X50Y72.COUT    Twosco                3.608   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH/O
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL.CE
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH
-    SLICE_X48Y71.F2      net (fanout=3)        1.084   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH/O
-    SLICE_X48Y71.X       Tilo                  0.601   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/MCNT_en
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.I_MCNT_en_SRLC16.U_MCNT_en
-    SLICE_X51Y71.CE      net (fanout=4)        1.003   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/MCNT_en
-    SLICE_X51Y71.CLK     Tceck                 0.155   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/MCNT<0>
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.U_MCNT/G[0].U_FDRE
-    -------------------------------------------------  ---------------------------
-    Total                                      6.451ns (4.364ns logic, 2.087ns route)
-                                                       (67.6% logic, 32.4% route)
-
---------------------------------------------------------------------------------
-Delay (setup path):     4.240ns (data path - clock path skew + uncertainty)
-  Source:               U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.I_MCNT_en_SRLC16.U_MCNT_en (FF)
-  Destination:          U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.U_MCNT/G[0].U_FDRE (FF)
-  Data Path Delay:      4.240ns (Levels of Logic = 0)
-  Clock Path Skew:      0.000ns
-  Source Clock:         icon_control0<0> rising
-  Destination Clock:    cmp_gn4124_core/clk_p rising
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.I_MCNT_en_SRLC16.U_MCNT_en to U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.U_MCNT/G[0].U_FDRE
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X48Y71.X       Treg                  3.082   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/MCNT_en
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.I_MCNT_en_SRLC16.U_MCNT_en.CE
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.I_MCNT_en_SRLC16.U_MCNT_en
-    SLICE_X51Y71.CE      net (fanout=4)        1.003   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/MCNT_en
-    SLICE_X51Y71.CLK     Tceck                 0.155   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/MCNT<0>
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.U_MCNT/G[0].U_FDRE
-    -------------------------------------------------  ---------------------------
-    Total                                      4.240ns (3.237ns logic, 1.003ns route)
-                                                       (76.3% logic, 23.7% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.U_MCNT/G[1].U_FDRE (SLICE_X51Y71.CE), 3 paths
---------------------------------------------------------------------------------
-Delay (setup path):     6.457ns (data path - clock path skew + uncertainty)
-  Source:               U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL (FF)
-  Destination:          U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.U_MCNT/G[1].U_FDRE (FF)
-  Data Path Delay:      6.457ns (Levels of Logic = 1)
-  Clock Path Skew:      0.000ns
-  Source Clock:         icon_control0<0> rising
-  Destination Clock:    cmp_gn4124_core/clk_p rising
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL to U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.U_MCNT/G[1].U_FDRE
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X50Y72.COUT    Twosco                3.614   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH/O
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL.CE
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXL
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH
-    SLICE_X48Y71.F2      net (fanout=3)        1.084   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH/O
-    SLICE_X48Y71.X       Tilo                  0.601   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/MCNT_en
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.I_MCNT_en_SRLC16.U_MCNT_en
-    SLICE_X51Y71.CE      net (fanout=4)        1.003   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/MCNT_en
-    SLICE_X51Y71.CLK     Tceck                 0.155   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/MCNT<0>
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.U_MCNT/G[1].U_FDRE
-    -------------------------------------------------  ---------------------------
-    Total                                      6.457ns (4.370ns logic, 2.087ns route)
-                                                       (67.7% logic, 32.3% route)
-
---------------------------------------------------------------------------------
-Delay (setup path):     6.451ns (data path - clock path skew + uncertainty)
-  Source:               U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH (FF)
-  Destination:          U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.U_MCNT/G[1].U_FDRE (FF)
-  Data Path Delay:      6.451ns (Levels of Logic = 1)
-  Clock Path Skew:      0.000ns
-  Source Clock:         icon_control0<0> rising
-  Destination Clock:    cmp_gn4124_core/clk_p rising
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH to U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.U_MCNT/G[1].U_FDRE
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X50Y72.COUT    Twosco                3.608   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH/O
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL.CE
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH
-    SLICE_X48Y71.F2      net (fanout=3)        1.084   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH/O
-    SLICE_X48Y71.X       Tilo                  0.601   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/MCNT_en
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.I_MCNT_en_SRLC16.U_MCNT_en
-    SLICE_X51Y71.CE      net (fanout=4)        1.003   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/MCNT_en
-    SLICE_X51Y71.CLK     Tceck                 0.155   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/MCNT<0>
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.U_MCNT/G[1].U_FDRE
-    -------------------------------------------------  ---------------------------
-    Total                                      6.451ns (4.364ns logic, 2.087ns route)
-                                                       (67.6% logic, 32.4% route)
-
---------------------------------------------------------------------------------
-Delay (setup path):     4.240ns (data path - clock path skew + uncertainty)
-  Source:               U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.I_MCNT_en_SRLC16.U_MCNT_en (FF)
-  Destination:          U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.U_MCNT/G[1].U_FDRE (FF)
-  Data Path Delay:      4.240ns (Levels of Logic = 0)
-  Clock Path Skew:      0.000ns
-  Source Clock:         icon_control0<0> rising
-  Destination Clock:    cmp_gn4124_core/clk_p rising
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.I_MCNT_en_SRLC16.U_MCNT_en to U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.U_MCNT/G[1].U_FDRE
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X48Y71.X       Treg                  3.082   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/MCNT_en
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.I_MCNT_en_SRLC16.U_MCNT_en.CE
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.I_MCNT_en_SRLC16.U_MCNT_en
-    SLICE_X51Y71.CE      net (fanout=4)        1.003   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/MCNT_en
-    SLICE_X51Y71.CLK     Tceck                 0.155   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/MCNT<0>
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.U_MCNT/G[1].U_FDRE
-    -------------------------------------------------  ---------------------------
-    Total                                      4.240ns (3.237ns logic, 1.003ns route)
-                                                       (76.3% logic, 23.7% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_DOUT (SLICE_X61Y85.BY), 3 paths
---------------------------------------------------------------------------------
-Delay (setup path):     6.429ns (data path - clock path skew + uncertainty)
-  Source:               U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL (FF)
-  Destination:          U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_DOUT (FF)
-  Data Path Delay:      6.429ns (Levels of Logic = 1)
-  Clock Path Skew:      0.000ns
-  Source Clock:         icon_control0<0> rising
-  Destination Clock:    cmp_gn4124_core/clk_p rising
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL to U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_DOUT
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X48Y78.COUT    Twosco                3.614   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH/O
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL.CE
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXL
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH
-    SLICE_X50Y78.G1      net (fanout=3)        0.904   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH/O
-    SLICE_X50Y78.Y       Tilo                  0.616   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/DOUT_flag
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.I_DOUT_flag_SRLC16.U_DOUT_flag
-    SLICE_X61Y85.BY      net (fanout=1)        1.048   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/DOUT_flag
-    SLICE_X61Y85.CLK     Tdick                 0.247   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/trigCondIn<4>
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_DOUT
-    -------------------------------------------------  ---------------------------
-    Total                                      6.429ns (4.477ns logic, 1.952ns route)
-                                                       (69.6% logic, 30.4% route)
-
---------------------------------------------------------------------------------
-Delay (setup path):     6.423ns (data path - clock path skew + uncertainty)
-  Source:               U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH (FF)
-  Destination:          U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_DOUT (FF)
-  Data Path Delay:      6.423ns (Levels of Logic = 1)
-  Clock Path Skew:      0.000ns
-  Source Clock:         icon_control0<0> rising
-  Destination Clock:    cmp_gn4124_core/clk_p rising
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH to U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_DOUT
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X48Y78.COUT    Twosco                3.608   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH/O
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL.CE
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH
-    SLICE_X50Y78.G1      net (fanout=3)        0.904   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH/O
-    SLICE_X50Y78.Y       Tilo                  0.616   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/DOUT_flag
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.I_DOUT_flag_SRLC16.U_DOUT_flag
-    SLICE_X61Y85.BY      net (fanout=1)        1.048   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/DOUT_flag
-    SLICE_X61Y85.CLK     Tdick                 0.247   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/trigCondIn<4>
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_DOUT
-    -------------------------------------------------  ---------------------------
-    Total                                      6.423ns (4.471ns logic, 1.952ns route)
-                                                       (69.6% logic, 30.4% route)
-
---------------------------------------------------------------------------------
-Delay (setup path):     4.392ns (data path - clock path skew + uncertainty)
-  Source:               U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.I_DOUT_flag_SRLC16.U_DOUT_flag (FF)
-  Destination:          U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_DOUT (FF)
-  Data Path Delay:      4.392ns (Levels of Logic = 0)
-  Clock Path Skew:      0.000ns
-  Source Clock:         icon_control0<0> rising
-  Destination Clock:    cmp_gn4124_core/clk_p rising
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.I_DOUT_flag_SRLC16.U_DOUT_flag to U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_DOUT
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X50Y78.Y       Treg                  3.097   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/DOUT_flag
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.I_DOUT_flag_SRLC16.U_DOUT_flag.CE
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.I_DOUT_flag_SRLC16.U_DOUT_flag
-    SLICE_X61Y85.BY      net (fanout=1)        1.048   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/DOUT_flag
-    SLICE_X61Y85.CLK     Tdick                 0.247   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/trigCondIn<4>
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_DOUT
-    -------------------------------------------------  ---------------------------
-    Total                                      4.392ns (3.344ns logic, 1.048ns route)
-                                                       (76.1% logic, 23.9% route)
-
---------------------------------------------------------------------------------
-
-Hold Paths: PATH "TS_J_TO_D_path" TIG;
---------------------------------------------------------------------------------
-
-Paths for end point U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[0].U_iCAP_ADDR (SLICE_X59Y52.G4), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      1.083ns (requirement - (clock path skew + uncertainty - data path))
-  Source:               U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[0].U_SEL (FF)
-  Destination:          U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[0].U_iCAP_ADDR (FF)
-  Requirement:          -2147483.647ns
-  Data Path Delay:      1.083ns (Levels of Logic = 1)
-  Clock Path Skew:      0.000ns
-  Source Clock:         icon_control0<0> rising
-  Destination Clock:    cmp_gn4124_core/clk_p rising
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[0].U_SEL to U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[0].U_iCAP_ADDR
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X59Y53.YQ      Tcko                  0.419   U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec<1>
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[0].U_SEL
-    SLICE_X59Y52.G4      net (fanout=2)        0.258   U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec<1>
-    SLICE_X59Y52.CLK     Tckg        (-Th)    -0.406   U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR<0>
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[0].U_CAP_ADDR_MUX
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[0].U_iCAP_ADDR
-    -------------------------------------------------  ---------------------------
-    Total                                      1.083ns (0.825ns logic, 0.258ns route)
-                                                       (76.2% logic, 23.8% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[2].U_iCAP_ADDR (SLICE_X59Y46.G4), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      1.113ns (requirement - (clock path skew + uncertainty - data path))
-  Source:               U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[2].U_SEL (FF)
-  Destination:          U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[2].U_iCAP_ADDR (FF)
-  Requirement:          -2147483.647ns
-  Data Path Delay:      1.113ns (Levels of Logic = 1)
-  Clock Path Skew:      0.000ns
-  Source Clock:         icon_control0<0> rising
-  Destination Clock:    cmp_gn4124_core/clk_p rising
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[2].U_SEL to U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[2].U_iCAP_ADDR
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X58Y47.XQ      Tcko                  0.417   U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec<3>
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[2].U_SEL
-    SLICE_X59Y46.G4      net (fanout=2)        0.290   U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec<3>
-    SLICE_X59Y46.CLK     Tckg        (-Th)    -0.406   U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR<2>
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[2].U_CAP_ADDR_MUX
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[2].U_iCAP_ADDR
-    -------------------------------------------------  ---------------------------
-    Total                                      1.113ns (0.823ns logic, 0.290ns route)
-                                                       (73.9% logic, 26.1% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[8].U_iCAP_ADDR (SLICE_X58Y51.G4), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      1.168ns (requirement - (clock path skew + uncertainty - data path))
-  Source:               U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[8].U_SEL (FF)
-  Destination:          U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[8].U_iCAP_ADDR (FF)
-  Requirement:          -2147483.647ns
-  Data Path Delay:      1.168ns (Levels of Logic = 1)
-  Clock Path Skew:      0.000ns
-  Source Clock:         icon_control0<0> rising
-  Destination Clock:    cmp_gn4124_core/clk_p rising
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[8].U_SEL to U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[8].U_iCAP_ADDR
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X59Y51.YQ      Tcko                  0.419   U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec<9>
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[8].U_SEL
-    SLICE_X58Y51.G4      net (fanout=2)        0.299   U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec<9>
-    SLICE_X58Y51.CLK     Tckg        (-Th)    -0.450   U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR<8>
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[8].U_CAP_ADDR_MUX
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[8].U_iCAP_ADDR
-    -------------------------------------------------  ---------------------------
-    Total                                      1.168ns (0.869ns logic, 0.299ns route)
-                                                       (74.4% logic, 25.6% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: PATH "TS_D_TO_J_path" TIG;
-
- 663 paths analyzed, 468 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors)
---------------------------------------------------------------------------------
-
-Paths for end point U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO (SLICE_X65Y113.F2), 17 paths
---------------------------------------------------------------------------------
-Delay (setup path):     6.193ns (data path - clock path skew + uncertainty)
-  Source:               U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_STATE1 (FF)
-  Destination:          U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO (FF)
-  Data Path Delay:      6.193ns (Levels of Logic = 4)
-  Clock Path Skew:      0.000ns
-  Source Clock:         cmp_gn4124_core/clk_p rising
-  Destination Clock:    icon_control0<0> rising
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_STATE1 to U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X54Y69.YQ      Tcko                  0.596   U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/STATE_dstat<1>
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_STATE1
-    SLICE_X54Y68.F4      net (fanout=1)        0.300   U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/STATE_dstat<1>
-    SLICE_X54Y68.X       Tilo                  0.601   U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_13
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_13
-    SLICE_X65Y89.F3      net (fanout=1)        1.371   U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_13
-    SLICE_X65Y89.X       Tif5x                 0.791   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<15>
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8_G
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8
-    SLICE_X65Y100.G3     net (fanout=1)        0.540   U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8
-    SLICE_X65Y100.X      Tif5x                 0.791   U_ila_pro_0/U0/iDATA<216>
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_2_f5_F
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_2_f5
-    SLICE_X65Y113.F2     net (fanout=1)        0.601   U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/TDO_mux_in<0>1
-    SLICE_X65Y113.CLK    Tfck                  0.602   U_ila_pro_0/U0/I_YES_D.U_ILA/iSTAT_DOUT
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O96
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO
-    -------------------------------------------------  ---------------------------
-    Total                                      6.193ns (3.381ns logic, 2.812ns route)
-                                                       (54.6% logic, 45.4% route)
-
---------------------------------------------------------------------------------
-Delay (setup path):     6.169ns (data path - clock path skew + uncertainty)
-  Source:               U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_STATE0 (FF)
-  Destination:          U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO (FF)
-  Data Path Delay:      6.169ns (Levels of Logic = 4)
-  Clock Path Skew:      0.000ns
-  Source Clock:         cmp_gn4124_core/clk_p rising
-  Destination Clock:    icon_control0<0> rising
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_STATE0 to U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X55Y69.YQ      Tcko                  0.524   U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/STATE_dstat<0>
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_STATE0
-    SLICE_X54Y68.F2      net (fanout=1)        0.348   U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/STATE_dstat<0>
-    SLICE_X54Y68.X       Tilo                  0.601   U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_13
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_13
-    SLICE_X65Y89.F3      net (fanout=1)        1.371   U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_13
-    SLICE_X65Y89.X       Tif5x                 0.791   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<15>
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8_G
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8
-    SLICE_X65Y100.G3     net (fanout=1)        0.540   U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8
-    SLICE_X65Y100.X      Tif5x                 0.791   U_ila_pro_0/U0/iDATA<216>
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_2_f5_F
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_2_f5
-    SLICE_X65Y113.F2     net (fanout=1)        0.601   U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/TDO_mux_in<0>1
-    SLICE_X65Y113.CLK    Tfck                  0.602   U_ila_pro_0/U0/I_YES_D.U_ILA/iSTAT_DOUT
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O96
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO
-    -------------------------------------------------  ---------------------------
-    Total                                      6.169ns (3.309ns logic, 2.860ns route)
-                                                       (53.6% logic, 46.4% route)
-
---------------------------------------------------------------------------------
-Delay (setup path):     5.258ns (data path - clock path skew + uncertainty)
-  Source:               U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/G_NS[3].U_NSQ (FF)
-  Destination:          U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO (FF)
-  Data Path Delay:      5.258ns (Levels of Logic = 4)
-  Clock Path Skew:      0.000ns
-  Source Clock:         cmp_gn4124_core/clk_p rising
-  Destination Clock:    icon_control0<0> rising
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/G_NS[3].U_NSQ to U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X58Y70.YQ      Tcko                  0.596   U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/NS_dstat<2>
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/G_NS[3].U_NSQ
-    SLICE_X59Y73.F1      net (fanout=1)        0.601   U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/NS_dstat<3>
-    SLICE_X59Y73.F5      Tif5                  0.688   U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_9_f5
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_101
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_9_f5
-    SLICE_X59Y72.FXINB   net (fanout=1)        0.000   U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_9_f5
-    SLICE_X59Y72.Y       Tif6y                 0.239   U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_7_f6
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_7_f6
-    SLICE_X65Y100.F4     net (fanout=1)        1.140   U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_7_f6
-    SLICE_X65Y100.X      Tif5x                 0.791   U_ila_pro_0/U0/iDATA<216>
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_2_f5_G
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_2_f5
-    SLICE_X65Y113.F2     net (fanout=1)        0.601   U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/TDO_mux_in<0>1
-    SLICE_X65Y113.CLK    Tfck                  0.602   U_ila_pro_0/U0/I_YES_D.U_ILA/iSTAT_DOUT
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O96
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO
-    -------------------------------------------------  ---------------------------
-    Total                                      5.258ns (2.916ns logic, 2.342ns route)
-                                                       (55.5% logic, 44.5% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[12].SI_CFG/I_NOLUT6.I_SRL_T2.U_SRLC16E (SLICE_X64Y85.G1), 5 paths
---------------------------------------------------------------------------------
-Delay (setup path):     3.694ns (data path)
-  Source:               U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/I_MC_YES.U_MC/U_DOUT (FF)
-  Destination:          U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[12].SI_CFG/I_NOLUT6.I_SRL_T2.U_SRLC16E (FF)
-  Data Path Delay:      3.694ns (Levels of Logic = 2)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-
-  Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/I_MC_YES.U_MC/U_DOUT to U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[12].SI_CFG/I_NOLUT6.I_SRL_T2.U_SRLC16E
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X60Y86.XQ      Tcko                  0.521   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/trigCondIn<0>
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/I_MC_YES.U_MC/U_DOUT
-    SLICE_X64Y89.G2      net (fanout=35)       1.039   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/trigCondIn<0>
-    SLICE_X64Y89.X       Tif5x                 0.853   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<42>
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[12].U_MUS.U_MUX/U_CS_MUX/I3.U_MUX8/Mmux_O_7
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[12].U_MUS.U_MUX/U_CS_MUX/I3.U_MUX8/Mmux_O_5_f5
-    SLICE_X65Y87.F2      net (fanout=1)        0.314   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[12].U_MUS.U_MUX/U_CS_MUX/I3.U_MUX8/Mmux_O_5_f5
-    SLICE_X65Y87.X       Tilo                  0.562   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<40>
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<38>
-    SLICE_X64Y85.G1      net (fanout=1)        0.405   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/mux_out<12>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.694ns (1.936ns logic, 1.758ns route)
-                                                       (52.4% logic, 47.6% route)
-
---------------------------------------------------------------------------------
-Delay (setup path):     3.607ns (data path)
-  Source:               U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_DOUT (FF)
-  Destination:          U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[12].SI_CFG/I_NOLUT6.I_SRL_T2.U_SRLC16E (FF)
-  Data Path Delay:      3.607ns (Levels of Logic = 2)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-
-  Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_DOUT to U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[12].SI_CFG/I_NOLUT6.I_SRL_T2.U_SRLC16E
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X60Y86.YQ      Tcko                  0.596   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/trigCondIn<0>
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_DOUT
-    SLICE_X64Y89.F4      net (fanout=19)       0.877   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/trigCondIn<2>
-    SLICE_X64Y89.X       Tif5x                 0.853   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<42>
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[12].U_MUS.U_MUX/U_CS_MUX/I3.U_MUX8/Mmux_O_6
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[12].U_MUS.U_MUX/U_CS_MUX/I3.U_MUX8/Mmux_O_5_f5
-    SLICE_X65Y87.F2      net (fanout=1)        0.314   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[12].U_MUS.U_MUX/U_CS_MUX/I3.U_MUX8/Mmux_O_5_f5
-    SLICE_X65Y87.X       Tilo                  0.562   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<40>
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<38>
-    SLICE_X64Y85.G1      net (fanout=1)        0.405   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/mux_out<12>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.607ns (2.011ns logic, 1.596ns route)
-                                                       (55.8% logic, 44.2% route)
-
---------------------------------------------------------------------------------
-Delay (setup path):     3.575ns (data path)
-  Source:               U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/I_MC_YES.U_MC/U_DOUT (FF)
-  Destination:          U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[12].SI_CFG/I_NOLUT6.I_SRL_T2.U_SRLC16E (FF)
-  Data Path Delay:      3.575ns (Levels of Logic = 2)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-
-  Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/I_MC_YES.U_MC/U_DOUT to U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[12].SI_CFG/I_NOLUT6.I_SRL_T2.U_SRLC16E
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X60Y87.YQ      Tcko                  0.596   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/trigCondIn<1>
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/I_MC_YES.U_MC/U_DOUT
-    SLICE_X64Y89.G3      net (fanout=19)       0.845   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/trigCondIn<1>
-    SLICE_X64Y89.X       Tif5x                 0.853   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<42>
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[12].U_MUS.U_MUX/U_CS_MUX/I3.U_MUX8/Mmux_O_7
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[12].U_MUS.U_MUX/U_CS_MUX/I3.U_MUX8/Mmux_O_5_f5
-    SLICE_X65Y87.F2      net (fanout=1)        0.314   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[12].U_MUS.U_MUX/U_CS_MUX/I3.U_MUX8/Mmux_O_5_f5
-    SLICE_X65Y87.X       Tilo                  0.562   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<40>
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<38>
-    SLICE_X64Y85.G1      net (fanout=1)        0.405   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/mux_out<12>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.575ns (2.011ns logic, 1.564ns route)
-                                                       (56.3% logic, 43.7% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/S0_CFG/I_NOLUT6.I_SRL_T2.U_SRLC16E (SLICE_X54Y90.G1), 5 paths
---------------------------------------------------------------------------------
-Delay (setup path):     3.685ns (data path)
-  Source:               U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_DOUT (FF)
-  Destination:          U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/S0_CFG/I_NOLUT6.I_SRL_T2.U_SRLC16E (FF)
-  Data Path Delay:      3.685ns (Levels of Logic = 2)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-
-  Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_DOUT to U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/S0_CFG/I_NOLUT6.I_SRL_T2.U_SRLC16E
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X60Y86.YQ      Tcko                  0.596   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/trigCondIn<0>
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_DOUT
-    SLICE_X58Y88.F2      net (fanout=19)       0.714   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/trigCondIn<2>
-    SLICE_X58Y88.X       Tif5x                 0.853   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_MUS.U_MUX0/U_CS_MUX/I3.U_MUX8/Mmux_O_5_f5
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_MUS.U_MUX0/U_CS_MUX/I3.U_MUX8/Mmux_O_6
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_MUS.U_MUX0/U_CS_MUX/I3.U_MUX8/Mmux_O_5_f5
-    SLICE_X58Y89.F1      net (fanout=1)        0.115   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_MUS.U_MUX0/U_CS_MUX/I3.U_MUX8/Mmux_O_5_f5
-    SLICE_X58Y89.X       Tilo                  0.601   U_ila_pro_0/U0/iDATA<250>
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<2>
-    SLICE_X54Y90.G1      net (fanout=1)        0.806   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/mux_out<0>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.685ns (2.050ns logic, 1.635ns route)
-                                                       (55.6% logic, 44.4% route)
-
---------------------------------------------------------------------------------
-Delay (setup path):     3.587ns (data path)
-  Source:               U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/I_MC_YES.U_MC/U_DOUT (FF)
-  Destination:          U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/S0_CFG/I_NOLUT6.I_SRL_T2.U_SRLC16E (FF)
-  Data Path Delay:      3.587ns (Levels of Logic = 2)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-
-  Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/I_MC_YES.U_MC/U_DOUT to U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/S0_CFG/I_NOLUT6.I_SRL_T2.U_SRLC16E
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X60Y87.YQ      Tcko                  0.596   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/trigCondIn<1>
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/I_MC_YES.U_MC/U_DOUT
-    SLICE_X58Y88.G4      net (fanout=19)       0.616   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/trigCondIn<1>
-    SLICE_X58Y88.X       Tif5x                 0.853   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_MUS.U_MUX0/U_CS_MUX/I3.U_MUX8/Mmux_O_5_f5
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_MUS.U_MUX0/U_CS_MUX/I3.U_MUX8/Mmux_O_7
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_MUS.U_MUX0/U_CS_MUX/I3.U_MUX8/Mmux_O_5_f5
-    SLICE_X58Y89.F1      net (fanout=1)        0.115   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_MUS.U_MUX0/U_CS_MUX/I3.U_MUX8/Mmux_O_5_f5
-    SLICE_X58Y89.X       Tilo                  0.601   U_ila_pro_0/U0/iDATA<250>
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<2>
-    SLICE_X54Y90.G1      net (fanout=1)        0.806   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/mux_out<0>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.587ns (2.050ns logic, 1.537ns route)
-                                                       (57.2% logic, 42.8% route)
-
---------------------------------------------------------------------------------
-Delay (setup path):     3.468ns (data path)
-  Source:               U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/I_MC_YES.U_MC/U_DOUT (FF)
-  Destination:          U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/S0_CFG/I_NOLUT6.I_SRL_T2.U_SRLC16E (FF)
-  Data Path Delay:      3.468ns (Levels of Logic = 2)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-
-  Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/I_MC_YES.U_MC/U_DOUT to U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/S0_CFG/I_NOLUT6.I_SRL_T2.U_SRLC16E
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X60Y86.XQ      Tcko                  0.521   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/trigCondIn<0>
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/I_MC_YES.U_MC/U_DOUT
-    SLICE_X58Y88.G2      net (fanout=35)       0.572   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/trigCondIn<0>
-    SLICE_X58Y88.X       Tif5x                 0.853   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_MUS.U_MUX0/U_CS_MUX/I3.U_MUX8/Mmux_O_5_f5
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_MUS.U_MUX0/U_CS_MUX/I3.U_MUX8/Mmux_O_7
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_MUS.U_MUX0/U_CS_MUX/I3.U_MUX8/Mmux_O_5_f5
-    SLICE_X58Y89.F1      net (fanout=1)        0.115   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_MUS.U_MUX0/U_CS_MUX/I3.U_MUX8/Mmux_O_5_f5
-    SLICE_X58Y89.X       Tilo                  0.601   U_ila_pro_0/U0/iDATA<250>
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<2>
-    SLICE_X54Y90.G1      net (fanout=1)        0.806   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/mux_out<0>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.468ns (1.975ns logic, 1.493ns route)
-                                                       (56.9% logic, 43.1% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TS_J_CLK = PERIOD TIMEGRP "J_CLK" 30 ns HIGH 50%;
-
- 5140 paths analyzed, 735 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
- Minimum period is  13.619ns.
---------------------------------------------------------------------------------
-
-Paths for end point U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO (SLICE_X65Y113.F4), 795 paths
---------------------------------------------------------------------------------
-Slack (setup path):     16.381ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               U_icon_pro/U0/U_ICON/U_SYNC/U_SYNC (FF)
-  Destination:          U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO (FF)
-  Requirement:          30.000ns
-  Data Path Delay:      13.619ns (Levels of Logic = 10)
-  Clock Path Skew:      0.000ns
-  Source Clock:         icon_control0<0> rising at 0.000ns
-  Destination Clock:    icon_control0<0> rising at 30.000ns
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: U_icon_pro/U0/U_ICON/U_SYNC/U_SYNC to U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X68Y121.YQ     Tcko                  0.596   U_icon_pro/U0/U_ICON/iSYNC
-                                                       U_icon_pro/U0/U_ICON/U_SYNC/U_SYNC
-    SLICE_X72Y121.F3     net (fanout=2)        0.550   U_icon_pro/U0/U_ICON/iSYNC
-    SLICE_X72Y121.X      Tilo                  0.601   U_icon_pro/U0/U_ICON/U_CTRL_OUT/iDATA_VALID
-                                                       U_icon_pro/U0/U_ICON/U_CTRL_OUT/U_DATA_VALID
-    SLICE_X57Y76.G2      net (fanout=32)       3.528   U_icon_pro/U0/U_ICON/U_CTRL_OUT/iDATA_VALID
-    SLICE_X57Y76.Y       Tilo                  0.561   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_5_TO_8.U_TCL/I_NMU_EQ2.U_iDOUT/iCFG_DIN
-                                                       U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[4].U_LCE
-    SLICE_X65Y109.F1     net (fanout=12)       2.109   icon_control0<8>
-    SLICE_X65Y109.COUT   Topcyf                1.026   U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<3>
-                                                       U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<2>
-                                                       U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<2>
-                                                       U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<3>
-    SLICE_X65Y110.CIN    net (fanout=1)        0.000   U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<3>
-    SLICE_X65Y110.COUT   Tbyp                  0.130   U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<5>
-                                                       U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<4>
-                                                       U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<5>
-    SLICE_X65Y111.CIN    net (fanout=1)        0.000   U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<5>
-    SLICE_X65Y111.COUT   Tbyp                  0.130   U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/ACTRESET_pulse
-                                                       U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<6>
-                                                       U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<7>
-    SLICE_X65Y112.CIN    net (fanout=1)        0.000   U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<7>
-    SLICE_X65Y112.XB     Tcinxb                0.216   icon_control0<35>
-                                                       U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<8>
-    SLICE_X66Y116.F2     net (fanout=3)        0.569   U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<8>
-    SLICE_X66Y116.X      Tif5x                 0.853   U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_15_f5
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_15_f5_G
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_15_f5
-    SLICE_X68Y118.G2     net (fanout=1)        0.360   U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_15_f5
-    SLICE_X68Y118.Y      Tilo                  0.616   U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O48
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O21
-    SLICE_X68Y118.F4     net (fanout=1)        0.035   U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O21/O
-    SLICE_X68Y118.X      Tilo                  0.601   U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O48
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O48
-    SLICE_X65Y113.F4     net (fanout=1)        0.536   U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O48
-    SLICE_X65Y113.CLK    Tfck                  0.602   U_ila_pro_0/U0/I_YES_D.U_ILA/iSTAT_DOUT
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O96
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO
-    -------------------------------------------------  ---------------------------
-    Total                                     13.619ns (5.932ns logic, 7.687ns route)
-                                                       (43.6% logic, 56.4% route)
-
---------------------------------------------------------------------------------
-Slack (setup path):     16.392ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               U_icon_pro/U0/U_ICON/U_SYNC/U_SYNC (FF)
-  Destination:          U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO (FF)
-  Requirement:          30.000ns
-  Data Path Delay:      13.608ns (Levels of Logic = 11)
-  Clock Path Skew:      0.000ns
-  Source Clock:         icon_control0<0> rising at 0.000ns
-  Destination Clock:    icon_control0<0> rising at 30.000ns
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: U_icon_pro/U0/U_ICON/U_SYNC/U_SYNC to U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X68Y121.YQ     Tcko                  0.596   U_icon_pro/U0/U_ICON/iSYNC
-                                                       U_icon_pro/U0/U_ICON/U_SYNC/U_SYNC
-    SLICE_X72Y121.F3     net (fanout=2)        0.550   U_icon_pro/U0/U_ICON/iSYNC
-    SLICE_X72Y121.X      Tilo                  0.601   U_icon_pro/U0/U_ICON/U_CTRL_OUT/iDATA_VALID
-                                                       U_icon_pro/U0/U_ICON/U_CTRL_OUT/U_DATA_VALID
-    SLICE_X68Y74.G1      net (fanout=32)       4.054   U_icon_pro/U0/U_ICON/U_CTRL_OUT/iDATA_VALID
-    SLICE_X68Y74.Y       Tilo                  0.616   cmp_gn4124_core/cmp_p2l_des/p2l_data_o<31>
-                                                       U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[10].U_LCE
-    SLICE_X65Y108.G2     net (fanout=9)        1.404   icon_control0<14>
-    SLICE_X65Y108.COUT   Topcyg                1.009   U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<1>
-                                                       U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<1>
-                                                       U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<1>
-    SLICE_X65Y109.CIN    net (fanout=1)        0.000   U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<1>
-    SLICE_X65Y109.COUT   Tbyp                  0.130   U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<3>
-                                                       U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<2>
-                                                       U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<3>
-    SLICE_X65Y110.CIN    net (fanout=1)        0.000   U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<3>
-    SLICE_X65Y110.COUT   Tbyp                  0.130   U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<5>
-                                                       U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<4>
-                                                       U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<5>
-    SLICE_X65Y111.CIN    net (fanout=1)        0.000   U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<5>
-    SLICE_X65Y111.COUT   Tbyp                  0.130   U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/ACTRESET_pulse
-                                                       U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<6>
-                                                       U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<7>
-    SLICE_X65Y112.CIN    net (fanout=1)        0.000   U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<7>
-    SLICE_X65Y112.XB     Tcinxb                0.216   icon_control0<35>
-                                                       U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<8>
-    SLICE_X66Y116.F2     net (fanout=3)        0.569   U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<8>
-    SLICE_X66Y116.X      Tif5x                 0.853   U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_15_f5
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_15_f5_G
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_15_f5
-    SLICE_X68Y118.G2     net (fanout=1)        0.360   U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_15_f5
-    SLICE_X68Y118.Y      Tilo                  0.616   U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O48
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O21
-    SLICE_X68Y118.F4     net (fanout=1)        0.035   U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O21/O
-    SLICE_X68Y118.X      Tilo                  0.601   U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O48
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O48
-    SLICE_X65Y113.F4     net (fanout=1)        0.536   U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O48
-    SLICE_X65Y113.CLK    Tfck                  0.602   U_ila_pro_0/U0/I_YES_D.U_ILA/iSTAT_DOUT
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O96
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO
-    -------------------------------------------------  ---------------------------
-    Total                                     13.608ns (6.100ns logic, 7.508ns route)
-                                                       (44.8% logic, 55.2% route)
-
---------------------------------------------------------------------------------
-Slack (setup path):     16.427ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[11].I_NE0.U_TARGET (FF)
-  Destination:          U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO (FF)
-  Requirement:          30.000ns
-  Data Path Delay:      13.573ns (Levels of Logic = 11)
-  Clock Path Skew:      0.000ns
-  Source Clock:         icon_control0<0> rising at 0.000ns
-  Destination Clock:    icon_control0<0> rising at 30.000ns
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[11].I_NE0.U_TARGET to U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X72Y115.YQ     Tcko                  0.596   U_icon_pro/U0/U_ICON/U_CMD/iTARGET<11>
-                                                       U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[11].I_NE0.U_TARGET
-    SLICE_X56Y92.F3      net (fanout=17)       3.069   U_icon_pro/U0/U_ICON/U_CMD/iTARGET<11>
-    SLICE_X56Y92.X       Tilo                  0.601   U_icon_pro/U0/U_ICON/iCOMMAND_SEL<5>
-                                                       U_icon_pro/U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[5].U_LUT
-    SLICE_X51Y75.G3      net (fanout=2)        1.248   U_icon_pro/U0/U_ICON/iCOMMAND_SEL<5>
-    SLICE_X51Y75.Y       Tilo                  0.561   U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCE/iCFG_DIN
-                                                       U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[5].U_LCE
-    SLICE_X65Y108.G4     net (fanout=53)       1.711   icon_control0<9>
-    SLICE_X65Y108.COUT   Topcyg                1.009   U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<1>
-                                                       U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<1>
-                                                       U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<1>
-    SLICE_X65Y109.CIN    net (fanout=1)        0.000   U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<1>
-    SLICE_X65Y109.COUT   Tbyp                  0.130   U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<3>
-                                                       U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<2>
-                                                       U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<3>
-    SLICE_X65Y110.CIN    net (fanout=1)        0.000   U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<3>
-    SLICE_X65Y110.COUT   Tbyp                  0.130   U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<5>
-                                                       U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<4>
-                                                       U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<5>
-    SLICE_X65Y111.CIN    net (fanout=1)        0.000   U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<5>
-    SLICE_X65Y111.COUT   Tbyp                  0.130   U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/ACTRESET_pulse
-                                                       U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<6>
-                                                       U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<7>
-    SLICE_X65Y112.CIN    net (fanout=1)        0.000   U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<7>
-    SLICE_X65Y112.XB     Tcinxb                0.216   icon_control0<35>
-                                                       U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<8>
-    SLICE_X66Y116.F2     net (fanout=3)        0.569   U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<8>
-    SLICE_X66Y116.X      Tif5x                 0.853   U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_15_f5
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_15_f5_G
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_15_f5
-    SLICE_X68Y118.G2     net (fanout=1)        0.360   U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_15_f5
-    SLICE_X68Y118.Y      Tilo                  0.616   U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O48
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O21
-    SLICE_X68Y118.F4     net (fanout=1)        0.035   U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O21/O
-    SLICE_X68Y118.X      Tilo                  0.601   U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O48
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O48
-    SLICE_X65Y113.F4     net (fanout=1)        0.536   U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O48
-    SLICE_X65Y113.CLK    Tfck                  0.602   U_ila_pro_0/U0/I_YES_D.U_ILA/iSTAT_DOUT
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O96
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO
-    -------------------------------------------------  ---------------------------
-    Total                                     13.573ns (6.045ns logic, 7.528ns route)
-                                                       (44.5% logic, 55.5% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO (SLICE_X65Y113.F1), 354 paths
---------------------------------------------------------------------------------
-Slack (setup path):     18.011ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               U_icon_pro/U0/U_ICON/U_SYNC/U_SYNC (FF)
-  Destination:          U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO (FF)
-  Requirement:          30.000ns
-  Data Path Delay:      11.989ns (Levels of Logic = 8)
-  Clock Path Skew:      0.000ns
-  Source Clock:         icon_control0<0> rising at 0.000ns
-  Destination Clock:    icon_control0<0> rising at 30.000ns
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: U_icon_pro/U0/U_ICON/U_SYNC/U_SYNC to U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X68Y121.YQ     Tcko                  0.596   U_icon_pro/U0/U_ICON/iSYNC
-                                                       U_icon_pro/U0/U_ICON/U_SYNC/U_SYNC
-    SLICE_X72Y121.F3     net (fanout=2)        0.550   U_icon_pro/U0/U_ICON/iSYNC
-    SLICE_X72Y121.X      Tilo                  0.601   U_icon_pro/U0/U_ICON/U_CTRL_OUT/iDATA_VALID
-                                                       U_icon_pro/U0/U_ICON/U_CTRL_OUT/U_DATA_VALID
-    SLICE_X57Y76.G2      net (fanout=32)       3.528   U_icon_pro/U0/U_ICON/U_CTRL_OUT/iDATA_VALID
-    SLICE_X57Y76.Y       Tilo                  0.561   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_5_TO_8.U_TCL/I_NMU_EQ2.U_iDOUT/iCFG_DIN
-                                                       U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[4].U_LCE
-    SLICE_X65Y109.F1     net (fanout=12)       2.109   icon_control0<8>
-    SLICE_X65Y109.COUT   Topcyf                1.026   U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<3>
-                                                       U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<2>
-                                                       U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<2>
-                                                       U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<3>
-    SLICE_X65Y110.CIN    net (fanout=1)        0.000   U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<3>
-    SLICE_X65Y110.COUT   Tbyp                  0.130   U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<5>
-                                                       U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<4>
-                                                       U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<5>
-    SLICE_X65Y111.CIN    net (fanout=1)        0.000   U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<5>
-    SLICE_X65Y111.COUT   Tbyp                  0.130   U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/ACTRESET_pulse
-                                                       U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<6>
-                                                       U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<7>
-    SLICE_X65Y112.CIN    net (fanout=1)        0.000   U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<7>
-    SLICE_X65Y112.XB     Tcinxb                0.216   icon_control0<35>
-                                                       U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<8>
-    SLICE_X67Y117.F3     net (fanout=3)        0.539   U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<8>
-    SLICE_X67Y117.X      Tilo                  0.562   U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O2
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O2
-    SLICE_X65Y113.F1     net (fanout=1)        0.839   U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O2
-    SLICE_X65Y113.CLK    Tfck                  0.602   U_ila_pro_0/U0/I_YES_D.U_ILA/iSTAT_DOUT
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O96
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO
-    -------------------------------------------------  ---------------------------
-    Total                                     11.989ns (4.424ns logic, 7.565ns route)
-                                                       (36.9% logic, 63.1% route)
-
---------------------------------------------------------------------------------
-Slack (setup path):     18.022ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               U_icon_pro/U0/U_ICON/U_SYNC/U_SYNC (FF)
-  Destination:          U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO (FF)
-  Requirement:          30.000ns
-  Data Path Delay:      11.978ns (Levels of Logic = 9)
-  Clock Path Skew:      0.000ns
-  Source Clock:         icon_control0<0> rising at 0.000ns
-  Destination Clock:    icon_control0<0> rising at 30.000ns
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: U_icon_pro/U0/U_ICON/U_SYNC/U_SYNC to U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X68Y121.YQ     Tcko                  0.596   U_icon_pro/U0/U_ICON/iSYNC
-                                                       U_icon_pro/U0/U_ICON/U_SYNC/U_SYNC
-    SLICE_X72Y121.F3     net (fanout=2)        0.550   U_icon_pro/U0/U_ICON/iSYNC
-    SLICE_X72Y121.X      Tilo                  0.601   U_icon_pro/U0/U_ICON/U_CTRL_OUT/iDATA_VALID
-                                                       U_icon_pro/U0/U_ICON/U_CTRL_OUT/U_DATA_VALID
-    SLICE_X68Y74.G1      net (fanout=32)       4.054   U_icon_pro/U0/U_ICON/U_CTRL_OUT/iDATA_VALID
-    SLICE_X68Y74.Y       Tilo                  0.616   cmp_gn4124_core/cmp_p2l_des/p2l_data_o<31>
-                                                       U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[10].U_LCE
-    SLICE_X65Y108.G2     net (fanout=9)        1.404   icon_control0<14>
-    SLICE_X65Y108.COUT   Topcyg                1.009   U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<1>
-                                                       U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<1>
-                                                       U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<1>
-    SLICE_X65Y109.CIN    net (fanout=1)        0.000   U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<1>
-    SLICE_X65Y109.COUT   Tbyp                  0.130   U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<3>
-                                                       U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<2>
-                                                       U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<3>
-    SLICE_X65Y110.CIN    net (fanout=1)        0.000   U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<3>
-    SLICE_X65Y110.COUT   Tbyp                  0.130   U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<5>
-                                                       U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<4>
-                                                       U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<5>
-    SLICE_X65Y111.CIN    net (fanout=1)        0.000   U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<5>
-    SLICE_X65Y111.COUT   Tbyp                  0.130   U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/ACTRESET_pulse
-                                                       U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<6>
-                                                       U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<7>
-    SLICE_X65Y112.CIN    net (fanout=1)        0.000   U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<7>
-    SLICE_X65Y112.XB     Tcinxb                0.216   icon_control0<35>
-                                                       U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<8>
-    SLICE_X67Y117.F3     net (fanout=3)        0.539   U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<8>
-    SLICE_X67Y117.X      Tilo                  0.562   U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O2
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O2
-    SLICE_X65Y113.F1     net (fanout=1)        0.839   U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O2
-    SLICE_X65Y113.CLK    Tfck                  0.602   U_ila_pro_0/U0/I_YES_D.U_ILA/iSTAT_DOUT
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O96
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO
-    -------------------------------------------------  ---------------------------
-    Total                                     11.978ns (4.592ns logic, 7.386ns route)
-                                                       (38.3% logic, 61.7% route)
-
---------------------------------------------------------------------------------
-Slack (setup path):     18.057ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[11].I_NE0.U_TARGET (FF)
-  Destination:          U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO (FF)
-  Requirement:          30.000ns
-  Data Path Delay:      11.943ns (Levels of Logic = 9)
-  Clock Path Skew:      0.000ns
-  Source Clock:         icon_control0<0> rising at 0.000ns
-  Destination Clock:    icon_control0<0> rising at 30.000ns
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[11].I_NE0.U_TARGET to U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X72Y115.YQ     Tcko                  0.596   U_icon_pro/U0/U_ICON/U_CMD/iTARGET<11>
-                                                       U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[11].I_NE0.U_TARGET
-    SLICE_X56Y92.F3      net (fanout=17)       3.069   U_icon_pro/U0/U_ICON/U_CMD/iTARGET<11>
-    SLICE_X56Y92.X       Tilo                  0.601   U_icon_pro/U0/U_ICON/iCOMMAND_SEL<5>
-                                                       U_icon_pro/U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[5].U_LUT
-    SLICE_X51Y75.G3      net (fanout=2)        1.248   U_icon_pro/U0/U_ICON/iCOMMAND_SEL<5>
-    SLICE_X51Y75.Y       Tilo                  0.561   U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCE/iCFG_DIN
-                                                       U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[5].U_LCE
-    SLICE_X65Y108.G4     net (fanout=53)       1.711   icon_control0<9>
-    SLICE_X65Y108.COUT   Topcyg                1.009   U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<1>
-                                                       U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<1>
-                                                       U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<1>
-    SLICE_X65Y109.CIN    net (fanout=1)        0.000   U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<1>
-    SLICE_X65Y109.COUT   Tbyp                  0.130   U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<3>
-                                                       U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<2>
-                                                       U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<3>
-    SLICE_X65Y110.CIN    net (fanout=1)        0.000   U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<3>
-    SLICE_X65Y110.COUT   Tbyp                  0.130   U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<5>
-                                                       U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<4>
-                                                       U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<5>
-    SLICE_X65Y111.CIN    net (fanout=1)        0.000   U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<5>
-    SLICE_X65Y111.COUT   Tbyp                  0.130   U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/ACTRESET_pulse
-                                                       U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<6>
-                                                       U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<7>
-    SLICE_X65Y112.CIN    net (fanout=1)        0.000   U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<7>
-    SLICE_X65Y112.XB     Tcinxb                0.216   icon_control0<35>
-                                                       U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<8>
-    SLICE_X67Y117.F3     net (fanout=3)        0.539   U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<8>
-    SLICE_X67Y117.X      Tilo                  0.562   U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O2
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O2
-    SLICE_X65Y113.F1     net (fanout=1)        0.839   U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O2
-    SLICE_X65Y113.CLK    Tfck                  0.602   U_ila_pro_0/U0/I_YES_D.U_ILA/iSTAT_DOUT
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O96
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO
-    -------------------------------------------------  ---------------------------
-    Total                                     11.943ns (4.537ns logic, 7.406ns route)
-                                                       (38.0% logic, 62.0% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point U_icon_pro/U0/U_ICON/U_TDO_reg (SLICE_X72Y117.G1), 49 paths
---------------------------------------------------------------------------------
-Slack (setup path):     19.044ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[8].U_BRAM/ram_rt1_s1_s16_if.ram_rt1_s1_s16_i (RAM)
-  Destination:          U_icon_pro/U0/U_ICON/U_TDO_reg (FF)
-  Requirement:          30.000ns
-  Data Path Delay:      10.956ns (Levels of Logic = 6)
-  Clock Path Skew:      0.000ns
-  Source Clock:         icon_control0<0> rising at 0.000ns
-  Destination Clock:    icon_control0<0> rising at 30.000ns
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[8].U_BRAM/ram_rt1_s1_s16_if.ram_rt1_s1_s16_i to U_icon_pro/U0/U_ICON/U_TDO_reg
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    RAMB16_X1Y0.DOA0     Trcko_DOWA            2.107   U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[8].U_BRAM/ram_rt1_s1_s16_if.ram_rt1_s1_s16_i
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[8].U_BRAM/ram_rt1_s1_s16_if.ram_rt1_s1_s16_i
-    SLICE_X74Y71.G1      net (fanout=1)        2.552   U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/localDOA<8>
-    SLICE_X74Y71.F5      Tif5                  0.709   U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_5_f7
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_10
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_8_f5
-    SLICE_X74Y70.FXINB   net (fanout=1)        0.000   U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_8_f5
-    SLICE_X74Y70.FX      Tinbfx                0.200   U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_7_f5
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_6_f6
-    SLICE_X74Y71.FXINA   net (fanout=1)        0.000   U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_6_f6
-    SLICE_X74Y71.Y       Tif6y                 0.315   U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_5_f7
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_5_f7
-    SLICE_X68Y71.F2      net (fanout=1)        0.551   U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_5_f7
-    SLICE_X68Y71.X       Tilo                  0.601   U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/muxAddrFF<1>
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/muxAddrFF<4>
-    SLICE_X65Y96.F4      net (fanout=1)        1.094   U_ila_pro_0/U0/I_YES_D.U_ILA/iDATA_DOUT
-    SLICE_X65Y96.X       Tilo                  0.562   icon_control0<3>
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_DOUT
-    SLICE_X72Y117.G1     net (fanout=1)        1.357   icon_control0<3>
-    SLICE_X72Y117.CLK    Tgck                  0.908   U_icon_pro/U0/U_ICON/iTDO
-                                                       U_icon_pro/U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_4
-                                                       U_icon_pro/U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_2_f5
-                                                       U_icon_pro/U0/U_ICON/U_TDO_reg
-    -------------------------------------------------  ---------------------------
-    Total                                     10.956ns (5.402ns logic, 5.554ns route)
-                                                       (49.3% logic, 50.7% route)
-
---------------------------------------------------------------------------------
-Slack (setup path):     19.078ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s16_if.ram_rt1_s1_s16_i (RAM)
-  Destination:          U_icon_pro/U0/U_ICON/U_TDO_reg (FF)
-  Requirement:          30.000ns
-  Data Path Delay:      10.922ns (Levels of Logic = 6)
-  Clock Path Skew:      0.000ns
-  Source Clock:         icon_control0<0> rising at 0.000ns
-  Destination Clock:    icon_control0<0> rising at 30.000ns
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s16_if.ram_rt1_s1_s16_i to U_icon_pro/U0/U_ICON/U_TDO_reg
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    RAMB16_X1Y15.DOA0    Trcko_DOWA            2.107   U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s16_if.ram_rt1_s1_s16_i
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s16_if.ram_rt1_s1_s16_i
-    SLICE_X75Y71.G1      net (fanout=1)        2.537   U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/localDOA<0>
-    SLICE_X75Y71.F5      Tif5                  0.688   U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_9_f5
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_11
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_9_f5
-    SLICE_X75Y70.FXINB   net (fanout=1)        0.000   U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_9_f5
-    SLICE_X75Y70.FX      Tinbfx                0.202   U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_8_f51
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_7_f6
-    SLICE_X74Y71.FXINB   net (fanout=1)        0.000   U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_7_f6
-    SLICE_X74Y71.Y       Tif6y                 0.315   U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_5_f7
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_5_f7
-    SLICE_X68Y71.F2      net (fanout=1)        0.551   U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_5_f7
-    SLICE_X68Y71.X       Tilo                  0.601   U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/muxAddrFF<1>
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/muxAddrFF<4>
-    SLICE_X65Y96.F4      net (fanout=1)        1.094   U_ila_pro_0/U0/I_YES_D.U_ILA/iDATA_DOUT
-    SLICE_X65Y96.X       Tilo                  0.562   icon_control0<3>
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_DOUT
-    SLICE_X72Y117.G1     net (fanout=1)        1.357   icon_control0<3>
-    SLICE_X72Y117.CLK    Tgck                  0.908   U_icon_pro/U0/U_ICON/iTDO
-                                                       U_icon_pro/U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_4
-                                                       U_icon_pro/U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_2_f5
-                                                       U_icon_pro/U0/U_ICON/U_TDO_reg
-    -------------------------------------------------  ---------------------------
-    Total                                     10.922ns (5.383ns logic, 5.539ns route)
-                                                       (49.3% logic, 50.7% route)
-
---------------------------------------------------------------------------------
-Slack (setup path):     19.591ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[2].U_BRAM/ram_rt1_s1_s16_if.ram_rt1_s1_s16_i (RAM)
-  Destination:          U_icon_pro/U0/U_ICON/U_TDO_reg (FF)
-  Requirement:          30.000ns
-  Data Path Delay:      10.409ns (Levels of Logic = 6)
-  Clock Path Skew:      0.000ns
-  Source Clock:         icon_control0<0> rising at 0.000ns
-  Destination Clock:    icon_control0<0> rising at 30.000ns
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[2].U_BRAM/ram_rt1_s1_s16_if.ram_rt1_s1_s16_i to U_icon_pro/U0/U_ICON/U_TDO_reg
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    RAMB16_X1Y13.DOA0    Trcko_DOWA            2.107   U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[2].U_BRAM/ram_rt1_s1_s16_if.ram_rt1_s1_s16_i
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[2].U_BRAM/ram_rt1_s1_s16_if.ram_rt1_s1_s16_i
-    SLICE_X75Y71.F4      net (fanout=1)        2.024   U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/localDOA<2>
-    SLICE_X75Y71.F5      Tif5                  0.688   U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_9_f5
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_102
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_9_f5
-    SLICE_X75Y70.FXINB   net (fanout=1)        0.000   U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_9_f5
-    SLICE_X75Y70.FX      Tinbfx                0.202   U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_8_f51
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_7_f6
-    SLICE_X74Y71.FXINB   net (fanout=1)        0.000   U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_7_f6
-    SLICE_X74Y71.Y       Tif6y                 0.315   U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_5_f7
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_5_f7
-    SLICE_X68Y71.F2      net (fanout=1)        0.551   U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_5_f7
-    SLICE_X68Y71.X       Tilo                  0.601   U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/muxAddrFF<1>
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/muxAddrFF<4>
-    SLICE_X65Y96.F4      net (fanout=1)        1.094   U_ila_pro_0/U0/I_YES_D.U_ILA/iDATA_DOUT
-    SLICE_X65Y96.X       Tilo                  0.562   icon_control0<3>
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_DOUT
-    SLICE_X72Y117.G1     net (fanout=1)        1.357   icon_control0<3>
-    SLICE_X72Y117.CLK    Tgck                  0.908   U_icon_pro/U0/U_ICON/iTDO
-                                                       U_icon_pro/U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_4
-                                                       U_icon_pro/U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_2_f5
-                                                       U_icon_pro/U0/U_ICON/U_TDO_reg
-    -------------------------------------------------  ---------------------------
-    Total                                     10.409ns (5.383ns logic, 5.026ns route)
-                                                       (51.7% logic, 48.3% route)
-
---------------------------------------------------------------------------------
-
-Hold Paths: TS_J_CLK = PERIOD TIMEGRP "J_CLK" 30 ns HIGH 50%;
---------------------------------------------------------------------------------
-
-Paths for end point U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.I_SRL.U_SELX (SLICE_X44Y33.BY), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.602ns (requirement - (clock path skew + uncertainty - data path))
-  Source:               U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[15].U_SEL (FF)
-  Destination:          U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.I_SRL.U_SELX (FF)
-  Requirement:          0.000ns
-  Data Path Delay:      0.602ns (Levels of Logic = 1)
-  Clock Path Skew:      0.000ns
-  Source Clock:         icon_control0<0> rising at 30.000ns
-  Destination Clock:    icon_control0<0> rising at 30.000ns
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[15].U_SEL to U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.I_SRL.U_SELX
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X45Y33.YQ      Tcko                  0.419   U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec<16>
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[15].U_SEL
-    SLICE_X44Y33.BY      net (fanout=1)        0.313   U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec<16>
-    SLICE_X44Y33.CLK     Tdh         (-Th)     0.130   U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data<0>
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.I_SRL.U_SELX
-    -------------------------------------------------  ---------------------------
-    Total                                      0.602ns (0.289ns logic, 0.313ns route)
-                                                       (48.0% logic, 52.0% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_CFG.U_CFG_FDS[46].U_REG (SLICE_X59Y92.BX), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.755ns (requirement - (clock path skew + uncertainty - data path))
-  Source:               U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_CFG.U_CFG_FDS[47].U_REG (FF)
-  Destination:          U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_CFG.U_CFG_FDS[46].U_REG (FF)
-  Requirement:          0.000ns
-  Data Path Delay:      0.755ns (Levels of Logic = 0)
-  Clock Path Skew:      0.000ns
-  Source Clock:         icon_control0<0> rising at 30.000ns
-  Destination Clock:    icon_control0<0> rising at 30.000ns
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_CFG.U_CFG_FDS[47].U_REG to U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_CFG.U_CFG_FDS[46].U_REG
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X59Y91.XQ      Tcko                  0.396   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<47>
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_CFG.U_CFG_FDS[47].U_REG
-    SLICE_X59Y92.BX      net (fanout=2)        0.297   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<47>
-    SLICE_X59Y92.CLK     Tckdi       (-Th)    -0.062   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<46>
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_CFG.U_CFG_FDS[46].U_REG
-    -------------------------------------------------  ---------------------------
-    Total                                      0.755ns (0.458ns logic, 0.297ns route)
-                                                       (60.7% logic, 39.3% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_CFG.U_CFG_FDS[30].U_REG (SLICE_X67Y91.BX), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.782ns (requirement - (clock path skew + uncertainty - data path))
-  Source:               U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_CFG.U_CFG_FDS[31].U_REG (FF)
-  Destination:          U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_CFG.U_CFG_FDS[30].U_REG (FF)
-  Requirement:          0.000ns
-  Data Path Delay:      0.782ns (Levels of Logic = 0)
-  Clock Path Skew:      0.000ns
-  Source Clock:         icon_control0<0> rising at 30.000ns
-  Destination Clock:    icon_control0<0> rising at 30.000ns
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_CFG.U_CFG_FDS[31].U_REG to U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_CFG.U_CFG_FDS[30].U_REG
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X67Y91.YQ      Tcko                  0.419   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<30>
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_CFG.U_CFG_FDS[31].U_REG
-    SLICE_X67Y91.BX      net (fanout=3)        0.301   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<31>
-    SLICE_X67Y91.CLK     Tckdi       (-Th)    -0.062   U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<30>
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_CFG.U_CFG_FDS[30].U_REG
-    -------------------------------------------------  ---------------------------
-    Total                                      0.782ns (0.481ns logic, 0.301ns route)
-                                                       (61.5% logic, 38.5% route)
-
---------------------------------------------------------------------------------
-
-Component Switching Limit Checks: TS_J_CLK = PERIOD TIMEGRP "J_CLK" 30 ns HIGH 50%;
---------------------------------------------------------------------------------
-Slack: 27.237ns (period - min period limit)
-  Period: 30.000ns
-  Min period limit: 2.763ns (361.925MHz) (Trper_CLKA)
-  Physical resource: U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[9].U_BRAM/ram_rt1_s1_s16_if.ram_rt1_s1_s16_i/CLKA
-  Logical resource: U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[9].U_BRAM/ram_rt1_s1_s16_if.ram_rt1_s1_s16_i/CLKA
-  Location pin: RAMB16_X1Y1.CLKA
-  Clock network: icon_control0<0>
---------------------------------------------------------------------------------
-Slack: 27.237ns (period - min period limit)
-  Period: 30.000ns
-  Min period limit: 2.763ns (361.925MHz) (Trper_CLKA)
-  Physical resource: U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[8].U_BRAM/ram_rt1_s1_s16_if.ram_rt1_s1_s16_i/CLKA
-  Logical resource: U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[8].U_BRAM/ram_rt1_s1_s16_if.ram_rt1_s1_s16_i/CLKA
-  Location pin: RAMB16_X1Y0.CLKA
-  Clock network: icon_control0<0>
---------------------------------------------------------------------------------
-Slack: 27.237ns (period - min period limit)
-  Period: 30.000ns
-  Min period limit: 2.763ns (361.925MHz) (Trper_CLKA)
-  Physical resource: U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[7].U_BRAM/ram_rt1_s1_s16_if.ram_rt1_s1_s16_i/CLKA
-  Logical resource: U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[7].U_BRAM/ram_rt1_s1_s16_if.ram_rt1_s1_s16_i/CLKA
-  Location pin: RAMB16_X1Y2.CLKA
-  Clock network: icon_control0<0>
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TS_p2l_clkp = PERIOD TIMEGRP "p2l_clkp_grp" 5 ns HIGH 50%;
-
- 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 component switching limit errors)
- Minimum period is   4.500ns.
---------------------------------------------------------------------------------
-
-Component Switching Limit Checks: TS_p2l_clkp = PERIOD TIMEGRP "p2l_clkp_grp" 5 ns HIGH 50%;
---------------------------------------------------------------------------------
-Slack: 0.500ns (period - min period limit)
-  Period: 5.000ns
-  Min period limit: 4.500ns (222.222MHz) ()
-  Physical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/CLKB
-  Logical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/CLKB
-  Location pin: RAMB16_X0Y5.CLKB
-  Clock network: cmp_gn4124_core/clk_p
---------------------------------------------------------------------------------
-Slack: 0.500ns (period - min period limit)
-  Period: 5.000ns
-  Min period limit: 4.500ns (222.222MHz) ()
-  Physical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s3_noinit.ram/dpram.dp36x36.ram/CLKA
-  Logical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s3_noinit.ram/dpram.dp36x36.ram/CLKA
-  Location pin: RAMB16_X0Y4.CLKA
-  Clock network: cmp_gn4124_core/clk_p
---------------------------------------------------------------------------------
-Slack: 0.500ns (period - min period limit)
-  Period: 5.000ns
-  Min period limit: 4.500ns (222.222MHz) ()
-  Physical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/CLKA
-  Logical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/CLKA
-  Location pin: RAMB16_X0Y6.CLKA
-  Clock network: cmp_gn4124_core/clk_p
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TS_p2l_clkn = PERIOD TIMEGRP "p2l_clkn_grp" 5 ns HIGH 50%;
-
- 28469 paths analyzed, 8553 endpoints analyzed, 132 failing endpoints
- 132 timing errors detected. (132 setup errors, 0 hold errors, 0 component switching limit errors)
- Minimum period is   5.820ns.
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_l2p_dma_master/l2p_address_l_25 (SLICE_X24Y125.F3), 13 paths
---------------------------------------------------------------------------------
-Slack (setup path):     -0.820ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_current_state_FSM_FFd7 (FF)
-  Destination:          cmp_gn4124_core/cmp_l2p_dma_master/l2p_address_l_25 (FF)
-  Requirement:          5.000ns
-  Data Path Delay:      5.737ns (Levels of Logic = 4)
-  Clock Path Skew:      -0.083ns (0.475 - 0.558)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 5.000ns
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_current_state_FSM_FFd7 to cmp_gn4124_core/cmp_l2p_dma_master/l2p_address_l_25
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X28Y114.XQ     Tcko                  0.521   cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_current_state_FSM_FFd7
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_current_state_FSM_FFd7
-    SLICE_X27Y107.F4     net (fanout=45)       0.972   cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_current_state_FSM_FFd7
-    SLICE_X27Y107.X      Tilo                  0.562   cmp_gn4124_core/cmp_l2p_arbiter/arb_ldm_gnt
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/l2p_address_l_mux0000<10>1_SW1
-    SLICE_X28Y117.G4     net (fanout=1)        0.858   N288
-    SLICE_X28Y117.Y      Tilo                  0.616   N279
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/l2p_address_l_mux0000<10>1
-    SLICE_X24Y125.G4     net (fanout=25)       0.915   cmp_gn4124_core/cmp_l2p_dma_master/N11
-    SLICE_X24Y125.Y      Tilo                  0.616   cmp_gn4124_core/cmp_l2p_dma_master/l2p_address_l<25>
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/l2p_address_l_mux0000<25>_SW0
-    SLICE_X24Y125.F3     net (fanout=1)        0.021   cmp_gn4124_core/cmp_l2p_dma_master/l2p_address_l_mux0000<25>_SW0/O
-    SLICE_X24Y125.CLK    Tfck                  0.656   cmp_gn4124_core/cmp_l2p_dma_master/l2p_address_l<25>
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/l2p_address_l_mux0000<25>
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/l2p_address_l_25
-    -------------------------------------------------  ---------------------------
-    Total                                      5.737ns (2.971ns logic, 2.766ns route)
-                                                       (51.8% logic, 48.2% route)
-
---------------------------------------------------------------------------------
-Slack (setup path):     -0.750ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_current_state_FSM_FFd3 (FF)
-  Destination:          cmp_gn4124_core/cmp_l2p_dma_master/l2p_address_l_25 (FF)
-  Requirement:          5.000ns
-  Data Path Delay:      5.651ns (Levels of Logic = 5)
-  Clock Path Skew:      -0.099ns (0.475 - 0.574)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 5.000ns
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_current_state_FSM_FFd3 to cmp_gn4124_core/cmp_l2p_dma_master/l2p_address_l_25
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X24Y119.YQ     Tcko                  0.596   cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_current_state_FSM_FFd3
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_current_state_FSM_FFd3
-    SLICE_X28Y116.G2     net (fanout=18)       0.848   cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_current_state_FSM_FFd3
-    SLICE_X28Y116.Y      Tilo                  0.616   N287
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/l2p_last_packet_mux000111
-    SLICE_X28Y116.F4     net (fanout=2)        0.045   cmp_gn4124_core/cmp_l2p_dma_master/N13
-    SLICE_X28Y116.X      Tilo                  0.601   N287
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/l2p_address_l_mux0000<10>1_SW0
-    SLICE_X28Y117.G1     net (fanout=1)        0.121   N287
-    SLICE_X28Y117.Y      Tilo                  0.616   N279
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/l2p_address_l_mux0000<10>1
-    SLICE_X24Y125.G4     net (fanout=25)       0.915   cmp_gn4124_core/cmp_l2p_dma_master/N11
-    SLICE_X24Y125.Y      Tilo                  0.616   cmp_gn4124_core/cmp_l2p_dma_master/l2p_address_l<25>
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/l2p_address_l_mux0000<25>_SW0
-    SLICE_X24Y125.F3     net (fanout=1)        0.021   cmp_gn4124_core/cmp_l2p_dma_master/l2p_address_l_mux0000<25>_SW0/O
-    SLICE_X24Y125.CLK    Tfck                  0.656   cmp_gn4124_core/cmp_l2p_dma_master/l2p_address_l<25>
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/l2p_address_l_mux0000<25>
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/l2p_address_l_25
-    -------------------------------------------------  ---------------------------
-    Total                                      5.651ns (3.701ns logic, 1.950ns route)
-                                                       (65.5% logic, 34.5% route)
-
---------------------------------------------------------------------------------
-Slack (setup path):     -0.526ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               cmp_gn4124_core/cmp_dma_controller/dma_ctrl_start_l2p_o (FF)
-  Destination:          cmp_gn4124_core/cmp_l2p_dma_master/l2p_address_l_25 (FF)
-  Requirement:          5.000ns
-  Data Path Delay:      5.404ns (Levels of Logic = 4)
-  Clock Path Skew:      -0.122ns (0.475 - 0.597)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 5.000ns
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: cmp_gn4124_core/cmp_dma_controller/dma_ctrl_start_l2p_o to cmp_gn4124_core/cmp_l2p_dma_master/l2p_address_l_25
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X29Y106.YQ     Tcko                  0.524   cmp_gn4124_core/cmp_dma_controller/dma_ctrl_start_l2p_o
-                                                       cmp_gn4124_core/cmp_dma_controller/dma_ctrl_start_l2p_o
-    SLICE_X27Y107.F3     net (fanout=73)       0.636   cmp_gn4124_core/cmp_dma_controller/dma_ctrl_start_l2p_o
-    SLICE_X27Y107.X      Tilo                  0.562   cmp_gn4124_core/cmp_l2p_arbiter/arb_ldm_gnt
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/l2p_address_l_mux0000<10>1_SW1
-    SLICE_X28Y117.G4     net (fanout=1)        0.858   N288
-    SLICE_X28Y117.Y      Tilo                  0.616   N279
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/l2p_address_l_mux0000<10>1
-    SLICE_X24Y125.G4     net (fanout=25)       0.915   cmp_gn4124_core/cmp_l2p_dma_master/N11
-    SLICE_X24Y125.Y      Tilo                  0.616   cmp_gn4124_core/cmp_l2p_dma_master/l2p_address_l<25>
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/l2p_address_l_mux0000<25>_SW0
-    SLICE_X24Y125.F3     net (fanout=1)        0.021   cmp_gn4124_core/cmp_l2p_dma_master/l2p_address_l_mux0000<25>_SW0/O
-    SLICE_X24Y125.CLK    Tfck                  0.656   cmp_gn4124_core/cmp_l2p_dma_master/l2p_address_l<25>
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/l2p_address_l_mux0000<25>
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/l2p_address_l_25
-    -------------------------------------------------  ---------------------------
-    Total                                      5.404ns (2.974ns logic, 2.430ns route)
-                                                       (55.0% logic, 45.0% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_11 (SLICE_X16Y126.F4), 11 paths
---------------------------------------------------------------------------------
-Slack (setup path):     -0.816ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_arbiter/arb_ldm_gnt (FF)
-  Destination:          cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_11 (FF)
-  Requirement:          5.000ns
-  Data Path Delay:      5.783ns (Levels of Logic = 5)
-  Clock Path Skew:      -0.033ns (0.523 - 0.556)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 5.000ns
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_arbiter/arb_ldm_gnt to cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_11
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X27Y107.YQ     Tcko                  0.524   cmp_gn4124_core/cmp_l2p_arbiter/arb_ldm_gnt
-                                                       cmp_gn4124_core/cmp_l2p_arbiter/arb_ldm_gnt
-    SLICE_X22Y116.G3     net (fanout=6)        1.051   cmp_gn4124_core/cmp_l2p_arbiter/arb_ldm_gnt
-    SLICE_X22Y116.Y      Tilo                  0.616   cmp_gn4124_core/l_wr_rdy<1>
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_req_o_mux0000121
-    SLICE_X22Y117.G4     net (fanout=3)        0.105   cmp_gn4124_core/cmp_l2p_dma_master/N49
-    SLICE_X22Y117.Y      Tilo                  0.616   cmp_gn4124_core/cmp_l2p_dma_master/N0
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_mux0000<0>1_SW0
-    SLICE_X22Y117.F3     net (fanout=1)        0.021   cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_mux0000<0>1_SW0/O
-    SLICE_X22Y117.X      Tilo                  0.601   cmp_gn4124_core/cmp_l2p_dma_master/N0
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_mux0000<0>1
-    SLICE_X16Y126.G3     net (fanout=27)       0.942   cmp_gn4124_core/cmp_l2p_dma_master/N0
-    SLICE_X16Y126.Y      Tilo                  0.616   cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o<11>
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_mux0000<11>5
-    SLICE_X16Y126.F4     net (fanout=1)        0.035   cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_mux0000<11>5/O
-    SLICE_X16Y126.CLK    Tfck                  0.656   cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o<11>
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_mux0000<11>14
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_11
-    -------------------------------------------------  ---------------------------
-    Total                                      5.783ns (3.629ns logic, 2.154ns route)
-                                                       (62.8% logic, 37.2% route)
-
---------------------------------------------------------------------------------
-Slack (setup path):     -0.590ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_current_state_FSM_FFd7 (FF)
-  Destination:          cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_11 (FF)
-  Requirement:          5.000ns
-  Data Path Delay:      5.555ns (Levels of Logic = 5)
-  Clock Path Skew:      -0.035ns (0.523 - 0.558)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 5.000ns
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_current_state_FSM_FFd7 to cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_11
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X28Y114.XQ     Tcko                  0.521   cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_current_state_FSM_FFd7
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_current_state_FSM_FFd7
-    SLICE_X22Y116.G2     net (fanout=45)       0.826   cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_current_state_FSM_FFd7
-    SLICE_X22Y116.Y      Tilo                  0.616   cmp_gn4124_core/l_wr_rdy<1>
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_req_o_mux0000121
-    SLICE_X22Y117.G4     net (fanout=3)        0.105   cmp_gn4124_core/cmp_l2p_dma_master/N49
-    SLICE_X22Y117.Y      Tilo                  0.616   cmp_gn4124_core/cmp_l2p_dma_master/N0
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_mux0000<0>1_SW0
-    SLICE_X22Y117.F3     net (fanout=1)        0.021   cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_mux0000<0>1_SW0/O
-    SLICE_X22Y117.X      Tilo                  0.601   cmp_gn4124_core/cmp_l2p_dma_master/N0
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_mux0000<0>1
-    SLICE_X16Y126.G3     net (fanout=27)       0.942   cmp_gn4124_core/cmp_l2p_dma_master/N0
-    SLICE_X16Y126.Y      Tilo                  0.616   cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o<11>
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_mux0000<11>5
-    SLICE_X16Y126.F4     net (fanout=1)        0.035   cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_mux0000<11>5/O
-    SLICE_X16Y126.CLK    Tfck                  0.656   cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o<11>
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_mux0000<11>14
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_11
-    -------------------------------------------------  ---------------------------
-    Total                                      5.555ns (3.626ns logic, 1.929ns route)
-                                                       (65.3% logic, 34.7% route)
-
---------------------------------------------------------------------------------
-Slack (setup path):     -0.225ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               cmp_gn4124_core/l_wr_rdy_1 (FF)
-  Destination:          cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_11 (FF)
-  Requirement:          5.000ns
-  Data Path Delay:      5.229ns (Levels of Logic = 5)
-  Clock Path Skew:      0.004ns (0.523 - 0.519)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 5.000ns
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: cmp_gn4124_core/l_wr_rdy_1 to cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_11
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X22Y116.YQ     Tcko                  0.596   cmp_gn4124_core/l_wr_rdy<1>
-                                                       cmp_gn4124_core/l_wr_rdy_1
-    SLICE_X22Y116.G1     net (fanout=2)        0.425   cmp_gn4124_core/l_wr_rdy<1>
-    SLICE_X22Y116.Y      Tilo                  0.616   cmp_gn4124_core/l_wr_rdy<1>
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_req_o_mux0000121
-    SLICE_X22Y117.G4     net (fanout=3)        0.105   cmp_gn4124_core/cmp_l2p_dma_master/N49
-    SLICE_X22Y117.Y      Tilo                  0.616   cmp_gn4124_core/cmp_l2p_dma_master/N0
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_mux0000<0>1_SW0
-    SLICE_X22Y117.F3     net (fanout=1)        0.021   cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_mux0000<0>1_SW0/O
-    SLICE_X22Y117.X      Tilo                  0.601   cmp_gn4124_core/cmp_l2p_dma_master/N0
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_mux0000<0>1
-    SLICE_X16Y126.G3     net (fanout=27)       0.942   cmp_gn4124_core/cmp_l2p_dma_master/N0
-    SLICE_X16Y126.Y      Tilo                  0.616   cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o<11>
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_mux0000<11>5
-    SLICE_X16Y126.F4     net (fanout=1)        0.035   cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_mux0000<11>5/O
-    SLICE_X16Y126.CLK    Tfck                  0.656   cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o<11>
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_mux0000<11>14
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_11
-    -------------------------------------------------  ---------------------------
-    Total                                      5.229ns (3.701ns logic, 1.528ns route)
-                                                       (70.8% logic, 29.2% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_26 (SLICE_X16Y127.F3), 11 paths
---------------------------------------------------------------------------------
-Slack (setup path):     -0.802ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_arbiter/arb_ldm_gnt (FF)
-  Destination:          cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_26 (FF)
-  Requirement:          5.000ns
-  Data Path Delay:      5.769ns (Levels of Logic = 5)
-  Clock Path Skew:      -0.033ns (0.523 - 0.556)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 5.000ns
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_arbiter/arb_ldm_gnt to cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_26
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X27Y107.YQ     Tcko                  0.524   cmp_gn4124_core/cmp_l2p_arbiter/arb_ldm_gnt
-                                                       cmp_gn4124_core/cmp_l2p_arbiter/arb_ldm_gnt
-    SLICE_X22Y116.G3     net (fanout=6)        1.051   cmp_gn4124_core/cmp_l2p_arbiter/arb_ldm_gnt
-    SLICE_X22Y116.Y      Tilo                  0.616   cmp_gn4124_core/l_wr_rdy<1>
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_req_o_mux0000121
-    SLICE_X22Y117.G4     net (fanout=3)        0.105   cmp_gn4124_core/cmp_l2p_dma_master/N49
-    SLICE_X22Y117.Y      Tilo                  0.616   cmp_gn4124_core/cmp_l2p_dma_master/N0
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_mux0000<0>1_SW0
-    SLICE_X22Y117.F3     net (fanout=1)        0.021   cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_mux0000<0>1_SW0/O
-    SLICE_X22Y117.X      Tilo                  0.601   cmp_gn4124_core/cmp_l2p_dma_master/N0
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_mux0000<0>1
-    SLICE_X16Y127.G3     net (fanout=27)       0.942   cmp_gn4124_core/cmp_l2p_dma_master/N0
-    SLICE_X16Y127.Y      Tilo                  0.616   cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o<26>
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_mux0000<26>5
-    SLICE_X16Y127.F3     net (fanout=1)        0.021   cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_mux0000<26>5/O
-    SLICE_X16Y127.CLK    Tfck                  0.656   cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o<26>
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_mux0000<26>14
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_26
-    -------------------------------------------------  ---------------------------
-    Total                                      5.769ns (3.629ns logic, 2.140ns route)
-                                                       (62.9% logic, 37.1% route)
-
---------------------------------------------------------------------------------
-Slack (setup path):     -0.576ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_current_state_FSM_FFd7 (FF)
-  Destination:          cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_26 (FF)
-  Requirement:          5.000ns
-  Data Path Delay:      5.541ns (Levels of Logic = 5)
-  Clock Path Skew:      -0.035ns (0.523 - 0.558)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 5.000ns
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_current_state_FSM_FFd7 to cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_26
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X28Y114.XQ     Tcko                  0.521   cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_current_state_FSM_FFd7
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_current_state_FSM_FFd7
-    SLICE_X22Y116.G2     net (fanout=45)       0.826   cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_current_state_FSM_FFd7
-    SLICE_X22Y116.Y      Tilo                  0.616   cmp_gn4124_core/l_wr_rdy<1>
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_req_o_mux0000121
-    SLICE_X22Y117.G4     net (fanout=3)        0.105   cmp_gn4124_core/cmp_l2p_dma_master/N49
-    SLICE_X22Y117.Y      Tilo                  0.616   cmp_gn4124_core/cmp_l2p_dma_master/N0
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_mux0000<0>1_SW0
-    SLICE_X22Y117.F3     net (fanout=1)        0.021   cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_mux0000<0>1_SW0/O
-    SLICE_X22Y117.X      Tilo                  0.601   cmp_gn4124_core/cmp_l2p_dma_master/N0
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_mux0000<0>1
-    SLICE_X16Y127.G3     net (fanout=27)       0.942   cmp_gn4124_core/cmp_l2p_dma_master/N0
-    SLICE_X16Y127.Y      Tilo                  0.616   cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o<26>
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_mux0000<26>5
-    SLICE_X16Y127.F3     net (fanout=1)        0.021   cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_mux0000<26>5/O
-    SLICE_X16Y127.CLK    Tfck                  0.656   cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o<26>
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_mux0000<26>14
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_26
-    -------------------------------------------------  ---------------------------
-    Total                                      5.541ns (3.626ns logic, 1.915ns route)
-                                                       (65.4% logic, 34.6% route)
-
---------------------------------------------------------------------------------
-Slack (setup path):     -0.211ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               cmp_gn4124_core/l_wr_rdy_1 (FF)
-  Destination:          cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_26 (FF)
-  Requirement:          5.000ns
-  Data Path Delay:      5.215ns (Levels of Logic = 5)
-  Clock Path Skew:      0.004ns (0.523 - 0.519)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 5.000ns
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: cmp_gn4124_core/l_wr_rdy_1 to cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_26
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X22Y116.YQ     Tcko                  0.596   cmp_gn4124_core/l_wr_rdy<1>
-                                                       cmp_gn4124_core/l_wr_rdy_1
-    SLICE_X22Y116.G1     net (fanout=2)        0.425   cmp_gn4124_core/l_wr_rdy<1>
-    SLICE_X22Y116.Y      Tilo                  0.616   cmp_gn4124_core/l_wr_rdy<1>
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_req_o_mux0000121
-    SLICE_X22Y117.G4     net (fanout=3)        0.105   cmp_gn4124_core/cmp_l2p_dma_master/N49
-    SLICE_X22Y117.Y      Tilo                  0.616   cmp_gn4124_core/cmp_l2p_dma_master/N0
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_mux0000<0>1_SW0
-    SLICE_X22Y117.F3     net (fanout=1)        0.021   cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_mux0000<0>1_SW0/O
-    SLICE_X22Y117.X      Tilo                  0.601   cmp_gn4124_core/cmp_l2p_dma_master/N0
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_mux0000<0>1
-    SLICE_X16Y127.G3     net (fanout=27)       0.942   cmp_gn4124_core/cmp_l2p_dma_master/N0
-    SLICE_X16Y127.Y      Tilo                  0.616   cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o<26>
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_mux0000<26>5
-    SLICE_X16Y127.F3     net (fanout=1)        0.021   cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_mux0000<26>5/O
-    SLICE_X16Y127.CLK    Tfck                  0.656   cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o<26>
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_mux0000<26>14
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_26
-    -------------------------------------------------  ---------------------------
-    Total                                      5.215ns (3.701ns logic, 1.514ns route)
-                                                       (71.0% logic, 29.0% route)
-
---------------------------------------------------------------------------------
-
-Hold Paths: TS_p2l_clkn = PERIOD TIMEGRP "p2l_clkn_grp" 5 ns HIGH 50%;
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/p2l_data_o_1 (SLICE_X70Y98.BX), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.337ns (requirement - (clock path skew + uncertainty - data path))
-  Source:               cmp_gn4124_core/cmp_p2l_des/p2l_data_sdr_l_1 (FF)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/p2l_data_o_1 (FF)
-  Requirement:          0.000ns
-  Data Path Delay:      0.818ns (Levels of Logic = 0)
-  Clock Path Skew:      0.481ns (2.894 - 2.413)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 5.000ns
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 5.000ns
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: cmp_gn4124_core/cmp_p2l_des/p2l_data_sdr_l_1 to cmp_gn4124_core/cmp_p2l_des/p2l_data_o_1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X73Y98.YQ      Tcko                  0.419   cmp_gn4124_core/cmp_p2l_des/p2l_data_sdr_l<1>
-                                                       cmp_gn4124_core/cmp_p2l_des/p2l_data_sdr_l_1
-    SLICE_X70Y98.BX      net (fanout=1)        0.297   cmp_gn4124_core/cmp_p2l_des/p2l_data_sdr_l<1>
-    SLICE_X70Y98.CLK     Tckdi       (-Th)    -0.102   cmp_gn4124_core/cmp_p2l_des/p2l_data_o<1>
-                                                       cmp_gn4124_core/cmp_p2l_des/p2l_data_o_1
-    -------------------------------------------------  ---------------------------
-    Total                                      0.818ns (0.521ns logic, 0.297ns route)
-                                                       (63.7% logic, 36.3% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point U_ila_pro_0/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[178].I_SRLT_NE_0.DLY9/SRL16E (SLICE_X72Y6.BX), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.530ns (requirement - (clock path skew + uncertainty - data path))
-  Source:               U_ila_pro_0/U0/I_DQ.G_DW[178].U_DQ (FF)
-  Destination:          U_ila_pro_0/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[178].I_SRLT_NE_0.DLY9/SRL16E (FF)
-  Requirement:          0.000ns
-  Data Path Delay:      0.531ns (Levels of Logic = 1)
-  Clock Path Skew:      0.001ns (0.004 - 0.003)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 5.000ns
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 5.000ns
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: U_ila_pro_0/U0/I_DQ.G_DW[178].U_DQ to U_ila_pro_0/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[178].I_SRLT_NE_0.DLY9/SRL16E
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X73Y6.XQ       Tcko                  0.396   U_ila_pro_0/U0/iDATA<178>
-                                                       U_ila_pro_0/U0/I_DQ.G_DW[178].U_DQ
-    SLICE_X72Y6.BX       net (fanout=1)        0.287   U_ila_pro_0/U0/iDATA<178>
-    SLICE_X72Y6.CLK      Tdh         (-Th)     0.152   U_ila_pro_0/U0/I_YES_D.U_ILA/iDATA<178>
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[178].I_SRLT_NE_0.DLY9/SRL16E
-    -------------------------------------------------  ---------------------------
-    Total                                      0.531ns (0.244ns logic, 0.287ns route)
-                                                       (46.0% logic, 54.0% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point U_ila_pro_0/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[181].I_SRLT_NE_0.DLY9/SRL16E (SLICE_X72Y67.BX), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.546ns (requirement - (clock path skew + uncertainty - data path))
-  Source:               U_ila_pro_0/U0/I_DQ.G_DW[181].U_DQ (FF)
-  Destination:          U_ila_pro_0/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[181].I_SRLT_NE_0.DLY9/SRL16E (FF)
-  Requirement:          0.000ns
-  Data Path Delay:      0.554ns (Levels of Logic = 1)
-  Clock Path Skew:      0.008ns (0.054 - 0.046)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 5.000ns
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 5.000ns
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: U_ila_pro_0/U0/I_DQ.G_DW[181].U_DQ to U_ila_pro_0/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[181].I_SRLT_NE_0.DLY9/SRL16E
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X73Y66.YQ      Tcko                  0.419   U_ila_pro_0/U0/iDATA<181>
-                                                       U_ila_pro_0/U0/I_DQ.G_DW[181].U_DQ
-    SLICE_X72Y67.BX      net (fanout=1)        0.287   U_ila_pro_0/U0/iDATA<181>
-    SLICE_X72Y67.CLK     Tdh         (-Th)     0.152   U_ila_pro_0/U0/I_YES_D.U_ILA/iDATA<181>
-                                                       U_ila_pro_0/U0/I_YES_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[181].I_SRLT_NE_0.DLY9/SRL16E
-    -------------------------------------------------  ---------------------------
-    Total                                      0.554ns (0.267ns logic, 0.287ns route)
-                                                       (48.2% logic, 51.8% route)
-
---------------------------------------------------------------------------------
-
-Component Switching Limit Checks: TS_p2l_clkn = PERIOD TIMEGRP "p2l_clkn_grp" 5 ns HIGH 50%;
---------------------------------------------------------------------------------
-Slack: 0.500ns (period - min period limit)
-  Period: 5.000ns
-  Min period limit: 4.500ns (222.222MHz) ()
-  Physical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/CLKB
-  Logical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/CLKB
-  Location pin: RAMB16_X0Y5.CLKB
-  Clock network: cmp_gn4124_core/clk_p
---------------------------------------------------------------------------------
-Slack: 0.500ns (period - min period limit)
-  Period: 5.000ns
-  Min period limit: 4.500ns (222.222MHz) ()
-  Physical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s3_noinit.ram/dpram.dp36x36.ram/CLKA
-  Logical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s3_noinit.ram/dpram.dp36x36.ram/CLKA
-  Location pin: RAMB16_X0Y4.CLKA
-  Clock network: cmp_gn4124_core/clk_p
---------------------------------------------------------------------------------
-Slack: 0.500ns (period - min period limit)
-  Period: 5.000ns
-  Min period limit: 4.500ns (222.222MHz) ()
-  Physical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/CLKA
-  Logical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/CLKA
-  Location pin: RAMB16_X0Y6.CLKA
-  Clock network: cmp_gn4124_core/clk_p
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "L2P_CLKn" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKn" 
-HIGH;
-
- 2 paths analyzed, 1 endpoint analyzed, 0 failing endpoints
- 0 timing errors detected.
- Minimum allowable offset is   6.263ns.
---------------------------------------------------------------------------------
-
-Paths for end point L2P_CLKn (Y21.PAD), 2 paths
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.237ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_l2p_clk_ddr_ff.L2P_CLK_int/ODDR2/N/FF1 (FF)
-  Destination:          L2P_CLKn (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.346ns (Levels of Logic = 0)
-  Clock Path Delay:     2.917ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_l2p_clk_ddr_ff.L2P_CLK_int/ODDR2/N/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.739   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.922   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    Y21.OTCLK2           net (fanout=2809)     1.022   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.917ns (1.873ns logic, 1.044ns route)
-                                                       (64.2% logic, 35.8% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_l2p_clk_ddr_ff.L2P_CLK_int/ODDR2/N/FF1 to L2P_CLKn
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    Y21.PAD              Tiockp                3.346   L2P_CLKn
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_l2p_clk_ddr_ff.L2P_CLK_int/ODDR2/N/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/L2P_CLK_BUF/N
-                                                       L2P_CLKn
-    -------------------------------------------------  ---------------------------
-    Total                                      3.346ns (3.346ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.239ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_l2p_clk_ddr_ff.L2P_CLK_int/ODDR2/N/FF0 (FF)
-  Destination:          L2P_CLKn (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.346ns (Levels of Logic = 0)
-  Clock Path Delay:     2.915ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_l2p_clk_ddr_ff.L2P_CLK_int/ODDR2/N/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.661   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    Y21.OTCLK1           net (fanout=50)       1.020   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.915ns (1.873ns logic, 1.042ns route)
-                                                       (64.3% logic, 35.7% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_l2p_clk_ddr_ff.L2P_CLK_int/ODDR2/N/FF0 to L2P_CLKn
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    Y21.PAD              Tiockp                3.346   L2P_CLKn
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_l2p_clk_ddr_ff.L2P_CLK_int/ODDR2/N/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/L2P_CLK_BUF/N
-                                                       L2P_CLKn
-    -------------------------------------------------  ---------------------------
-    Total                                      3.346ns (3.346ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-Fastest Paths: COMP "L2P_CLKn" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKn" HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point L2P_CLKn (Y21.PAD), 2 paths
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.247ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_l2p_clk_ddr_ff.L2P_CLK_int/ODDR2/N/FF1 (FF)
-  Destination:          L2P_CLKn (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Data Path Delay:      2.773ns (Levels of Logic = 0)
-  Clock Path Delay:     2.474ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_l2p_clk_ddr_ff.L2P_CLK_int/ODDR2/N/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.733   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.738   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    Y21.OTCLK2           net (fanout=2809)     0.869   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.474ns (1.588ns logic, 0.886ns route)
-                                                       (64.2% logic, 35.8% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_l2p_clk_ddr_ff.L2P_CLK_int/ODDR2/N/FF1 to L2P_CLKn
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    Y21.PAD              Tiockp                2.773   L2P_CLKn
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_l2p_clk_ddr_ff.L2P_CLK_int/ODDR2/N/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/L2P_CLK_BUF/N
-                                                       L2P_CLKn
-    -------------------------------------------------  ---------------------------
-    Total                                      2.773ns (2.773ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.244ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_l2p_clk_ddr_ff.L2P_CLK_int/ODDR2/N/FF0 (FF)
-  Destination:          L2P_CLKn (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Data Path Delay:      2.773ns (Levels of Logic = 0)
-  Clock Path Delay:     2.471ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_l2p_clk_ddr_ff.L2P_CLK_int/ODDR2/N/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.470   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    Y21.OTCLK1           net (fanout=50)       0.867   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.471ns (1.587ns logic, 0.884ns route)
-                                                       (64.2% logic, 35.8% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_l2p_clk_ddr_ff.L2P_CLK_int/ODDR2/N/FF0 to L2P_CLKn
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    Y21.PAD              Tiockp                2.773   L2P_CLKn
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_l2p_clk_ddr_ff.L2P_CLK_int/ODDR2/N/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/L2P_CLK_BUF/N
-                                                       L2P_CLKn
-    -------------------------------------------------  ---------------------------
-    Total                                      2.773ns (2.773ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "L2P_CLKp" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKp" 
-HIGH;
-
- 2 paths analyzed, 1 endpoint analyzed, 0 failing endpoints
- 0 timing errors detected.
- Minimum allowable offset is   6.263ns.
---------------------------------------------------------------------------------
-
-Paths for end point L2P_CLKp (AA22.PAD), 2 paths
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.237ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_l2p_clk_ddr_ff.L2P_CLK_int/ODDR2/FF1 (FF)
-  Destination:          L2P_CLKp (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.346ns (Levels of Logic = 0)
-  Clock Path Delay:     2.917ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_l2p_clk_ddr_ff.L2P_CLK_int/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.661   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    AA22.OTCLK2          net (fanout=2809)     1.022   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.917ns (1.873ns logic, 1.044ns route)
-                                                       (64.2% logic, 35.8% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_l2p_clk_ddr_ff.L2P_CLK_int/ODDR2/FF1 to L2P_CLKp
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    AA22.PAD             Tiockp                3.346   L2P_CLKp
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_l2p_clk_ddr_ff.L2P_CLK_int/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/L2P_CLK_BUF
-                                                       L2P_CLKp
-    -------------------------------------------------  ---------------------------
-    Total                                      3.346ns (3.346ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.239ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_l2p_clk_ddr_ff.L2P_CLK_int/ODDR2/FF0 (FF)
-  Destination:          L2P_CLKp (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.346ns (Levels of Logic = 0)
-  Clock Path Delay:     2.915ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_l2p_clk_ddr_ff.L2P_CLK_int/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.739   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.922   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    AA22.OTCLK1          net (fanout=50)       1.020   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.915ns (1.873ns logic, 1.042ns route)
-                                                       (64.3% logic, 35.7% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_l2p_clk_ddr_ff.L2P_CLK_int/ODDR2/FF0 to L2P_CLKp
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    AA22.PAD             Tiockp                3.346   L2P_CLKp
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_l2p_clk_ddr_ff.L2P_CLK_int/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/L2P_CLK_BUF
-                                                       L2P_CLKp
-    -------------------------------------------------  ---------------------------
-    Total                                      3.346ns (3.346ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-Fastest Paths: COMP "L2P_CLKp" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKp" HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point L2P_CLKp (AA22.PAD), 2 paths
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.246ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_l2p_clk_ddr_ff.L2P_CLK_int/ODDR2/FF1 (FF)
-  Destination:          L2P_CLKp (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Data Path Delay:      2.773ns (Levels of Logic = 0)
-  Clock Path Delay:     2.473ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_l2p_clk_ddr_ff.L2P_CLK_int/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.470   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    AA22.OTCLK2          net (fanout=2809)     0.869   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.473ns (1.587ns logic, 0.886ns route)
-                                                       (64.2% logic, 35.8% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_l2p_clk_ddr_ff.L2P_CLK_int/ODDR2/FF1 to L2P_CLKp
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    AA22.PAD             Tiockp                2.773   L2P_CLKp
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_l2p_clk_ddr_ff.L2P_CLK_int/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/L2P_CLK_BUF
-                                                       L2P_CLKp
-    -------------------------------------------------  ---------------------------
-    Total                                      2.773ns (2.773ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.245ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_l2p_clk_ddr_ff.L2P_CLK_int/ODDR2/FF0 (FF)
-  Destination:          L2P_CLKp (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Data Path Delay:      2.773ns (Levels of Logic = 0)
-  Clock Path Delay:     2.472ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_l2p_clk_ddr_ff.L2P_CLK_int/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.733   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.738   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    AA22.OTCLK1          net (fanout=50)       0.867   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.472ns (1.588ns logic, 0.884ns route)
-                                                       (64.2% logic, 35.8% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_l2p_clk_ddr_ff.L2P_CLK_int/ODDR2/FF0 to L2P_CLKp
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    AA22.PAD             Tiockp                2.773   L2P_CLKp
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_l2p_clk_ddr_ff.L2P_CLK_int/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/L2P_CLK_BUF
-                                                       L2P_CLKp
-    -------------------------------------------------  ---------------------------
-    Total                                      2.773ns (2.773ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "L2P_DATA<0>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKp" 
-HIGH;
-
- 2 paths analyzed, 1 endpoint analyzed, 0 failing endpoints
- 0 timing errors detected.
- Minimum allowable offset is   6.170ns.
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<0> (V22.PAD), 2 paths
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.330ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[0].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<0> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.913ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[0].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.661   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    V22.OTCLK2           net (fanout=2809)     1.018   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.913ns (1.873ns logic, 1.040ns route)
-                                                       (64.3% logic, 35.7% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[0].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<0>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    V22.PAD              Tiockp                3.257   L2P_DATA<0>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[0].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[0].U/OBUF1
-                                                       L2P_DATA<0>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.333ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[0].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<0> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.910ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[0].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.739   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.922   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    V22.OTCLK1           net (fanout=50)       1.015   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.910ns (1.873ns logic, 1.037ns route)
-                                                       (64.4% logic, 35.6% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[0].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<0>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    V22.PAD              Tiockp                3.257   L2P_DATA<0>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[0].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[0].U/OBUF1
-                                                       L2P_DATA<0>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-Fastest Paths: COMP "L2P_DATA<0>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKp" HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<0> (V22.PAD), 2 paths
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.154ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[0].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<0> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.470ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[0].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.470   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    V22.OTCLK2           net (fanout=2809)     0.866   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.470ns (1.587ns logic, 0.883ns route)
-                                                       (64.3% logic, 35.7% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[0].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<0>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    V22.PAD              Tiockp                2.684   L2P_DATA<0>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[0].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[0].U/OBUF1
-                                                       L2P_DATA<0>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.151ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[0].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<0> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.467ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[0].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.733   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.738   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    V22.OTCLK1           net (fanout=50)       0.862   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.467ns (1.588ns logic, 0.879ns route)
-                                                       (64.4% logic, 35.6% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[0].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<0>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    V22.PAD              Tiockp                2.684   L2P_DATA<0>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[0].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[0].U/OBUF1
-                                                       L2P_DATA<0>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "L2P_DATA<0>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKn" 
-HIGH;
-
- 2 paths analyzed, 1 endpoint analyzed, 0 failing endpoints
- 0 timing errors detected.
- Minimum allowable offset is   6.170ns.
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<0> (V22.PAD), 2 paths
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.330ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[0].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<0> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.913ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[0].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.739   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.922   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    V22.OTCLK2           net (fanout=2809)     1.018   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.913ns (1.873ns logic, 1.040ns route)
-                                                       (64.3% logic, 35.7% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[0].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<0>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    V22.PAD              Tiockp                3.257   L2P_DATA<0>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[0].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[0].U/OBUF1
-                                                       L2P_DATA<0>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.333ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[0].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<0> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.910ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[0].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.661   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    V22.OTCLK1           net (fanout=50)       1.015   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.910ns (1.873ns logic, 1.037ns route)
-                                                       (64.4% logic, 35.6% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[0].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<0>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    V22.PAD              Tiockp                3.257   L2P_DATA<0>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[0].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[0].U/OBUF1
-                                                       L2P_DATA<0>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-Fastest Paths: COMP "L2P_DATA<0>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKn" HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<0> (V22.PAD), 2 paths
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.155ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[0].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<0> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.471ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[0].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.733   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.738   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    V22.OTCLK2           net (fanout=2809)     0.866   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.471ns (1.588ns logic, 0.883ns route)
-                                                       (64.3% logic, 35.7% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[0].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<0>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    V22.PAD              Tiockp                2.684   L2P_DATA<0>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[0].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[0].U/OBUF1
-                                                       L2P_DATA<0>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.150ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[0].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<0> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.466ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[0].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.470   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    V22.OTCLK1           net (fanout=50)       0.862   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.466ns (1.587ns logic, 0.879ns route)
-                                                       (64.4% logic, 35.6% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[0].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<0>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    V22.PAD              Tiockp                2.684   L2P_DATA<0>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[0].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[0].U/OBUF1
-                                                       L2P_DATA<0>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "L2P_DATA<10>" OFFSET = OUT 6.5 ns AFTER COMP 
-"P2L_CLKp" HIGH;
-
- 2 paths analyzed, 1 endpoint analyzed, 0 failing endpoints
- 0 timing errors detected.
- Minimum allowable offset is   6.125ns.
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<10> (R19.PAD), 2 paths
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.375ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[10].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<10> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.868ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[10].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.661   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    R19.OTCLK2           net (fanout=2809)     0.973   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.868ns (1.873ns logic, 0.995ns route)
-                                                       (65.3% logic, 34.7% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[10].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<10>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    R19.PAD              Tiockp                3.257   L2P_DATA<10>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[10].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[10].U/OBUF1
-                                                       L2P_DATA<10>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.381ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[10].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<10> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.862ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[10].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.739   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.922   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    R19.OTCLK1           net (fanout=50)       0.967   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.862ns (1.873ns logic, 0.989ns route)
-                                                       (65.4% logic, 34.6% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[10].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<10>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    R19.PAD              Tiockp                3.257   L2P_DATA<10>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[10].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[10].U/OBUF1
-                                                       L2P_DATA<10>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-Fastest Paths: COMP "L2P_DATA<10>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKp" HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<10> (R19.PAD), 2 paths
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.115ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[10].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<10> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.431ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[10].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.470   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    R19.OTCLK2           net (fanout=2809)     0.827   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.431ns (1.587ns logic, 0.844ns route)
-                                                       (65.3% logic, 34.7% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[10].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<10>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    R19.PAD              Tiockp                2.684   L2P_DATA<10>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[10].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[10].U/OBUF1
-                                                       L2P_DATA<10>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.111ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[10].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<10> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.427ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[10].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.733   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.738   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    R19.OTCLK1           net (fanout=50)       0.822   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.427ns (1.588ns logic, 0.839ns route)
-                                                       (65.4% logic, 34.6% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[10].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<10>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    R19.PAD              Tiockp                2.684   L2P_DATA<10>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[10].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[10].U/OBUF1
-                                                       L2P_DATA<10>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "L2P_DATA<10>" OFFSET = OUT 6.5 ns AFTER COMP 
-"P2L_CLKn" HIGH;
-
- 2 paths analyzed, 1 endpoint analyzed, 0 failing endpoints
- 0 timing errors detected.
- Minimum allowable offset is   6.125ns.
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<10> (R19.PAD), 2 paths
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.375ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[10].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<10> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.868ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[10].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.739   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.922   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    R19.OTCLK2           net (fanout=2809)     0.973   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.868ns (1.873ns logic, 0.995ns route)
-                                                       (65.3% logic, 34.7% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[10].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<10>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    R19.PAD              Tiockp                3.257   L2P_DATA<10>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[10].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[10].U/OBUF1
-                                                       L2P_DATA<10>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.381ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[10].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<10> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.862ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[10].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.661   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    R19.OTCLK1           net (fanout=50)       0.967   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.862ns (1.873ns logic, 0.989ns route)
-                                                       (65.4% logic, 34.6% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[10].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<10>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    R19.PAD              Tiockp                3.257   L2P_DATA<10>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[10].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[10].U/OBUF1
-                                                       L2P_DATA<10>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-Fastest Paths: COMP "L2P_DATA<10>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKn" HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<10> (R19.PAD), 2 paths
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.116ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[10].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<10> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.432ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[10].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.733   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.738   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    R19.OTCLK2           net (fanout=2809)     0.827   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.432ns (1.588ns logic, 0.844ns route)
-                                                       (65.3% logic, 34.7% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[10].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<10>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    R19.PAD              Tiockp                2.684   L2P_DATA<10>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[10].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[10].U/OBUF1
-                                                       L2P_DATA<10>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.110ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[10].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<10> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.426ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[10].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.470   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    R19.OTCLK1           net (fanout=50)       0.822   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.426ns (1.587ns logic, 0.839ns route)
-                                                       (65.4% logic, 34.6% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[10].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<10>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    R19.PAD              Tiockp                2.684   L2P_DATA<10>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[10].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[10].U/OBUF1
-                                                       L2P_DATA<10>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "L2P_DATA<11>" OFFSET = OUT 6.5 ns AFTER COMP 
-"P2L_CLKp" HIGH;
-
- 2 paths analyzed, 1 endpoint analyzed, 0 failing endpoints
- 0 timing errors detected.
- Minimum allowable offset is   6.164ns.
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<11> (N18.PAD), 2 paths
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.336ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[11].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<11> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.907ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[11].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.661   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    N18.OTCLK2           net (fanout=2809)     1.012   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.907ns (1.873ns logic, 1.034ns route)
-                                                       (64.4% logic, 35.6% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[11].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<11>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    N18.PAD              Tiockp                3.257   L2P_DATA<11>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[11].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[11].U/OBUF1
-                                                       L2P_DATA<11>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.371ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[11].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<11> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.872ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[11].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.739   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.922   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    N18.OTCLK1           net (fanout=50)       0.977   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.872ns (1.873ns logic, 0.999ns route)
-                                                       (65.2% logic, 34.8% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[11].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<11>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    N18.PAD              Tiockp                3.257   L2P_DATA<11>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[11].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[11].U/OBUF1
-                                                       L2P_DATA<11>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-Fastest Paths: COMP "L2P_DATA<11>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKp" HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<11> (N18.PAD), 2 paths
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.148ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[11].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<11> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.464ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[11].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.470   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    N18.OTCLK2           net (fanout=2809)     0.860   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.464ns (1.587ns logic, 0.877ns route)
-                                                       (64.4% logic, 35.6% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[11].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<11>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    N18.PAD              Tiockp                2.684   L2P_DATA<11>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[11].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[11].U/OBUF1
-                                                       L2P_DATA<11>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.120ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[11].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<11> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.436ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[11].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.733   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.738   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    N18.OTCLK1           net (fanout=50)       0.831   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.436ns (1.588ns logic, 0.848ns route)
-                                                       (65.2% logic, 34.8% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[11].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<11>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    N18.PAD              Tiockp                2.684   L2P_DATA<11>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[11].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[11].U/OBUF1
-                                                       L2P_DATA<11>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "L2P_DATA<11>" OFFSET = OUT 6.5 ns AFTER COMP 
-"P2L_CLKn" HIGH;
-
- 2 paths analyzed, 1 endpoint analyzed, 0 failing endpoints
- 0 timing errors detected.
- Minimum allowable offset is   6.164ns.
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<11> (N18.PAD), 2 paths
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.336ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[11].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<11> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.907ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[11].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.739   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.922   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    N18.OTCLK2           net (fanout=2809)     1.012   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.907ns (1.873ns logic, 1.034ns route)
-                                                       (64.4% logic, 35.6% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[11].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<11>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    N18.PAD              Tiockp                3.257   L2P_DATA<11>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[11].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[11].U/OBUF1
-                                                       L2P_DATA<11>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.371ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[11].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<11> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.872ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[11].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.661   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    N18.OTCLK1           net (fanout=50)       0.977   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.872ns (1.873ns logic, 0.999ns route)
-                                                       (65.2% logic, 34.8% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[11].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<11>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    N18.PAD              Tiockp                3.257   L2P_DATA<11>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[11].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[11].U/OBUF1
-                                                       L2P_DATA<11>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-Fastest Paths: COMP "L2P_DATA<11>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKn" HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<11> (N18.PAD), 2 paths
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.149ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[11].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<11> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.465ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[11].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.733   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.738   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    N18.OTCLK2           net (fanout=2809)     0.860   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.465ns (1.588ns logic, 0.877ns route)
-                                                       (64.4% logic, 35.6% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[11].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<11>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    N18.PAD              Tiockp                2.684   L2P_DATA<11>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[11].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[11].U/OBUF1
-                                                       L2P_DATA<11>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.119ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[11].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<11> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.435ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[11].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.470   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    N18.OTCLK1           net (fanout=50)       0.831   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.435ns (1.587ns logic, 0.848ns route)
-                                                       (65.2% logic, 34.8% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[11].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<11>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    N18.PAD              Tiockp                2.684   L2P_DATA<11>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[11].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[11].U/OBUF1
-                                                       L2P_DATA<11>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "L2P_DATA<12>" OFFSET = OUT 6.5 ns AFTER COMP 
-"P2L_CLKp" HIGH;
-
- 2 paths analyzed, 1 endpoint analyzed, 0 failing endpoints
- 0 timing errors detected.
- Minimum allowable offset is   6.187ns.
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<12> (U19.PAD), 2 paths
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.313ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[12].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<12> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.930ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[12].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.661   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    U19.OTCLK2           net (fanout=2809)     1.035   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.930ns (1.873ns logic, 1.057ns route)
-                                                       (63.9% logic, 36.1% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[12].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<12>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    U19.PAD              Tiockp                3.257   L2P_DATA<12>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[12].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[12].U/OBUF1
-                                                       L2P_DATA<12>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.319ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[12].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<12> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.924ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[12].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.739   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.922   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    U19.OTCLK1           net (fanout=50)       1.029   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.924ns (1.873ns logic, 1.051ns route)
-                                                       (64.1% logic, 35.9% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[12].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<12>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    U19.PAD              Tiockp                3.257   L2P_DATA<12>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[12].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[12].U/OBUF1
-                                                       L2P_DATA<12>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-Fastest Paths: COMP "L2P_DATA<12>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKp" HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<12> (U19.PAD), 2 paths
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.168ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[12].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<12> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.484ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[12].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.470   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    U19.OTCLK2           net (fanout=2809)     0.880   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.484ns (1.587ns logic, 0.897ns route)
-                                                       (63.9% logic, 36.1% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[12].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<12>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    U19.PAD              Tiockp                2.684   L2P_DATA<12>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[12].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[12].U/OBUF1
-                                                       L2P_DATA<12>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.164ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[12].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<12> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.480ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[12].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.733   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.738   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    U19.OTCLK1           net (fanout=50)       0.875   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.480ns (1.588ns logic, 0.892ns route)
-                                                       (64.0% logic, 36.0% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[12].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<12>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    U19.PAD              Tiockp                2.684   L2P_DATA<12>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[12].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[12].U/OBUF1
-                                                       L2P_DATA<12>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "L2P_DATA<12>" OFFSET = OUT 6.5 ns AFTER COMP 
-"P2L_CLKn" HIGH;
-
- 2 paths analyzed, 1 endpoint analyzed, 0 failing endpoints
- 0 timing errors detected.
- Minimum allowable offset is   6.187ns.
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<12> (U19.PAD), 2 paths
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.313ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[12].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<12> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.930ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[12].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.739   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.922   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    U19.OTCLK2           net (fanout=2809)     1.035   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.930ns (1.873ns logic, 1.057ns route)
-                                                       (63.9% logic, 36.1% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[12].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<12>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    U19.PAD              Tiockp                3.257   L2P_DATA<12>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[12].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[12].U/OBUF1
-                                                       L2P_DATA<12>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.319ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[12].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<12> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.924ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[12].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.661   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    U19.OTCLK1           net (fanout=50)       1.029   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.924ns (1.873ns logic, 1.051ns route)
-                                                       (64.1% logic, 35.9% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[12].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<12>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    U19.PAD              Tiockp                3.257   L2P_DATA<12>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[12].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[12].U/OBUF1
-                                                       L2P_DATA<12>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-Fastest Paths: COMP "L2P_DATA<12>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKn" HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<12> (U19.PAD), 2 paths
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.169ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[12].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<12> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.485ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[12].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.733   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.738   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    U19.OTCLK2           net (fanout=2809)     0.880   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.485ns (1.588ns logic, 0.897ns route)
-                                                       (63.9% logic, 36.1% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[12].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<12>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    U19.PAD              Tiockp                2.684   L2P_DATA<12>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[12].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[12].U/OBUF1
-                                                       L2P_DATA<12>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.163ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[12].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<12> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.479ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[12].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.470   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    U19.OTCLK1           net (fanout=50)       0.875   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.479ns (1.587ns logic, 0.892ns route)
-                                                       (64.0% logic, 36.0% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[12].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<12>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    U19.PAD              Tiockp                2.684   L2P_DATA<12>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[12].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[12].U/OBUF1
-                                                       L2P_DATA<12>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "L2P_DATA<13>" OFFSET = OUT 6.5 ns AFTER COMP 
-"P2L_CLKp" HIGH;
-
- 2 paths analyzed, 1 endpoint analyzed, 0 failing endpoints
- 0 timing errors detected.
- Minimum allowable offset is   6.183ns.
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<13> (U21.PAD), 2 paths
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.317ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[13].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<13> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.926ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[13].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.661   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    U21.OTCLK2           net (fanout=2809)     1.031   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.926ns (1.873ns logic, 1.053ns route)
-                                                       (64.0% logic, 36.0% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[13].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<13>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    U21.PAD              Tiockp                3.257   L2P_DATA<13>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[13].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[13].U/OBUF1
-                                                       L2P_DATA<13>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.322ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[13].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<13> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.921ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[13].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.739   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.922   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    U21.OTCLK1           net (fanout=50)       1.026   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.921ns (1.873ns logic, 1.048ns route)
-                                                       (64.1% logic, 35.9% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[13].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<13>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    U21.PAD              Tiockp                3.257   L2P_DATA<13>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[13].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[13].U/OBUF1
-                                                       L2P_DATA<13>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-Fastest Paths: COMP "L2P_DATA<13>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKp" HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<13> (U21.PAD), 2 paths
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.165ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[13].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<13> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.481ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[13].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.470   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    U21.OTCLK2           net (fanout=2809)     0.877   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.481ns (1.587ns logic, 0.894ns route)
-                                                       (64.0% logic, 36.0% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[13].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<13>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    U21.PAD              Tiockp                2.684   L2P_DATA<13>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[13].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[13].U/OBUF1
-                                                       L2P_DATA<13>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.161ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[13].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<13> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.477ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[13].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.733   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.738   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    U21.OTCLK1           net (fanout=50)       0.872   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.477ns (1.588ns logic, 0.889ns route)
-                                                       (64.1% logic, 35.9% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[13].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<13>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    U21.PAD              Tiockp                2.684   L2P_DATA<13>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[13].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[13].U/OBUF1
-                                                       L2P_DATA<13>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "L2P_DATA<13>" OFFSET = OUT 6.5 ns AFTER COMP 
-"P2L_CLKn" HIGH;
-
- 2 paths analyzed, 1 endpoint analyzed, 0 failing endpoints
- 0 timing errors detected.
- Minimum allowable offset is   6.183ns.
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<13> (U21.PAD), 2 paths
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.317ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[13].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<13> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.926ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[13].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.739   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.922   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    U21.OTCLK2           net (fanout=2809)     1.031   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.926ns (1.873ns logic, 1.053ns route)
-                                                       (64.0% logic, 36.0% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[13].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<13>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    U21.PAD              Tiockp                3.257   L2P_DATA<13>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[13].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[13].U/OBUF1
-                                                       L2P_DATA<13>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.322ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[13].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<13> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.921ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[13].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.661   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    U21.OTCLK1           net (fanout=50)       1.026   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.921ns (1.873ns logic, 1.048ns route)
-                                                       (64.1% logic, 35.9% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[13].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<13>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    U21.PAD              Tiockp                3.257   L2P_DATA<13>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[13].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[13].U/OBUF1
-                                                       L2P_DATA<13>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-Fastest Paths: COMP "L2P_DATA<13>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKn" HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<13> (U21.PAD), 2 paths
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.166ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[13].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<13> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.482ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[13].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.733   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.738   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    U21.OTCLK2           net (fanout=2809)     0.877   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.482ns (1.588ns logic, 0.894ns route)
-                                                       (64.0% logic, 36.0% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[13].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<13>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    U21.PAD              Tiockp                2.684   L2P_DATA<13>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[13].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[13].U/OBUF1
-                                                       L2P_DATA<13>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.160ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[13].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<13> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.476ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[13].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.470   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    U21.OTCLK1           net (fanout=50)       0.872   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.476ns (1.587ns logic, 0.889ns route)
-                                                       (64.1% logic, 35.9% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[13].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<13>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    U21.PAD              Tiockp                2.684   L2P_DATA<13>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[13].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[13].U/OBUF1
-                                                       L2P_DATA<13>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "L2P_DATA<14>" OFFSET = OUT 6.5 ns AFTER COMP 
-"P2L_CLKp" HIGH;
-
- 2 paths analyzed, 1 endpoint analyzed, 0 failing endpoints
- 0 timing errors detected.
- Minimum allowable offset is   6.187ns.
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<14> (U20.PAD), 2 paths
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.313ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[14].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<14> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.930ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[14].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.661   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    U20.OTCLK2           net (fanout=2809)     1.035   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.930ns (1.873ns logic, 1.057ns route)
-                                                       (63.9% logic, 36.1% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[14].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<14>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    U20.PAD              Tiockp                3.257   L2P_DATA<14>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[14].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[14].U/OBUF1
-                                                       L2P_DATA<14>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.319ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[14].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<14> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.924ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[14].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.739   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.922   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    U20.OTCLK1           net (fanout=50)       1.029   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.924ns (1.873ns logic, 1.051ns route)
-                                                       (64.1% logic, 35.9% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[14].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<14>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    U20.PAD              Tiockp                3.257   L2P_DATA<14>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[14].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[14].U/OBUF1
-                                                       L2P_DATA<14>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-Fastest Paths: COMP "L2P_DATA<14>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKp" HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<14> (U20.PAD), 2 paths
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.168ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[14].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<14> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.484ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[14].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.470   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    U20.OTCLK2           net (fanout=2809)     0.880   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.484ns (1.587ns logic, 0.897ns route)
-                                                       (63.9% logic, 36.1% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[14].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<14>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    U20.PAD              Tiockp                2.684   L2P_DATA<14>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[14].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[14].U/OBUF1
-                                                       L2P_DATA<14>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.164ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[14].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<14> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.480ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[14].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.733   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.738   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    U20.OTCLK1           net (fanout=50)       0.875   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.480ns (1.588ns logic, 0.892ns route)
-                                                       (64.0% logic, 36.0% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[14].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<14>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    U20.PAD              Tiockp                2.684   L2P_DATA<14>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[14].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[14].U/OBUF1
-                                                       L2P_DATA<14>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "L2P_DATA<14>" OFFSET = OUT 6.5 ns AFTER COMP 
-"P2L_CLKn" HIGH;
-
- 2 paths analyzed, 1 endpoint analyzed, 0 failing endpoints
- 0 timing errors detected.
- Minimum allowable offset is   6.187ns.
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<14> (U20.PAD), 2 paths
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.313ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[14].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<14> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.930ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[14].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.739   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.922   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    U20.OTCLK2           net (fanout=2809)     1.035   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.930ns (1.873ns logic, 1.057ns route)
-                                                       (63.9% logic, 36.1% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[14].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<14>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    U20.PAD              Tiockp                3.257   L2P_DATA<14>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[14].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[14].U/OBUF1
-                                                       L2P_DATA<14>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.319ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[14].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<14> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.924ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[14].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.661   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    U20.OTCLK1           net (fanout=50)       1.029   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.924ns (1.873ns logic, 1.051ns route)
-                                                       (64.1% logic, 35.9% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[14].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<14>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    U20.PAD              Tiockp                3.257   L2P_DATA<14>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[14].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[14].U/OBUF1
-                                                       L2P_DATA<14>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-Fastest Paths: COMP "L2P_DATA<14>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKn" HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<14> (U20.PAD), 2 paths
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.169ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[14].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<14> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.485ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[14].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.733   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.738   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    U20.OTCLK2           net (fanout=2809)     0.880   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.485ns (1.588ns logic, 0.897ns route)
-                                                       (63.9% logic, 36.1% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[14].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<14>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    U20.PAD              Tiockp                2.684   L2P_DATA<14>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[14].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[14].U/OBUF1
-                                                       L2P_DATA<14>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.163ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[14].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<14> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.479ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[14].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.470   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    U20.OTCLK1           net (fanout=50)       0.875   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.479ns (1.587ns logic, 0.892ns route)
-                                                       (64.0% logic, 36.0% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[14].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<14>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    U20.PAD              Tiockp                2.684   L2P_DATA<14>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[14].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[14].U/OBUF1
-                                                       L2P_DATA<14>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "L2P_DATA<15>" OFFSET = OUT 6.5 ns AFTER COMP 
-"P2L_CLKp" HIGH;
-
- 2 paths analyzed, 1 endpoint analyzed, 0 failing endpoints
- 0 timing errors detected.
- Minimum allowable offset is   6.142ns.
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<15> (N19.PAD), 2 paths
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.358ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[15].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<15> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.885ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[15].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.661   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    N19.OTCLK2           net (fanout=2809)     0.990   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.885ns (1.873ns logic, 1.012ns route)
-                                                       (64.9% logic, 35.1% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[15].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<15>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    N19.PAD              Tiockp                3.257   L2P_DATA<15>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[15].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[15].U/OBUF1
-                                                       L2P_DATA<15>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.374ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[15].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<15> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.869ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[15].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.739   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.922   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    N19.OTCLK1           net (fanout=50)       0.974   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.869ns (1.873ns logic, 0.996ns route)
-                                                       (65.3% logic, 34.7% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[15].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<15>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    N19.PAD              Tiockp                3.257   L2P_DATA<15>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[15].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[15].U/OBUF1
-                                                       L2P_DATA<15>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-Fastest Paths: COMP "L2P_DATA<15>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKp" HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<15> (N19.PAD), 2 paths
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.130ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[15].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<15> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.446ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[15].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.470   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    N19.OTCLK2           net (fanout=2809)     0.842   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.446ns (1.587ns logic, 0.859ns route)
-                                                       (64.9% logic, 35.1% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[15].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<15>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    N19.PAD              Tiockp                2.684   L2P_DATA<15>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[15].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[15].U/OBUF1
-                                                       L2P_DATA<15>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.117ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[15].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<15> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.433ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[15].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.733   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.738   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    N19.OTCLK1           net (fanout=50)       0.828   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.433ns (1.588ns logic, 0.845ns route)
-                                                       (65.3% logic, 34.7% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[15].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<15>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    N19.PAD              Tiockp                2.684   L2P_DATA<15>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[15].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[15].U/OBUF1
-                                                       L2P_DATA<15>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "L2P_DATA<15>" OFFSET = OUT 6.5 ns AFTER COMP 
-"P2L_CLKn" HIGH;
-
- 2 paths analyzed, 1 endpoint analyzed, 0 failing endpoints
- 0 timing errors detected.
- Minimum allowable offset is   6.142ns.
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<15> (N19.PAD), 2 paths
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.358ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[15].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<15> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.885ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[15].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.739   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.922   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    N19.OTCLK2           net (fanout=2809)     0.990   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.885ns (1.873ns logic, 1.012ns route)
-                                                       (64.9% logic, 35.1% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[15].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<15>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    N19.PAD              Tiockp                3.257   L2P_DATA<15>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[15].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[15].U/OBUF1
-                                                       L2P_DATA<15>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.374ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[15].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<15> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.869ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[15].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.661   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    N19.OTCLK1           net (fanout=50)       0.974   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.869ns (1.873ns logic, 0.996ns route)
-                                                       (65.3% logic, 34.7% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[15].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<15>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    N19.PAD              Tiockp                3.257   L2P_DATA<15>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[15].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[15].U/OBUF1
-                                                       L2P_DATA<15>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-Fastest Paths: COMP "L2P_DATA<15>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKn" HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<15> (N19.PAD), 2 paths
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.131ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[15].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<15> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.447ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[15].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.733   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.738   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    N19.OTCLK2           net (fanout=2809)     0.842   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.447ns (1.588ns logic, 0.859ns route)
-                                                       (64.9% logic, 35.1% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[15].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<15>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    N19.PAD              Tiockp                2.684   L2P_DATA<15>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[15].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[15].U/OBUF1
-                                                       L2P_DATA<15>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.116ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[15].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<15> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.432ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[15].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.470   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    N19.OTCLK1           net (fanout=50)       0.828   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.432ns (1.587ns logic, 0.845ns route)
-                                                       (65.3% logic, 34.7% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[15].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<15>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    N19.PAD              Tiockp                2.684   L2P_DATA<15>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[15].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[15].U/OBUF1
-                                                       L2P_DATA<15>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "L2P_DATA<1>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKp" 
-HIGH;
-
- 2 paths analyzed, 1 endpoint analyzed, 0 failing endpoints
- 0 timing errors detected.
- Minimum allowable offset is   6.170ns.
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<1> (W22.PAD), 2 paths
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.330ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[1].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<1> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.913ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[1].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.661   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    W22.OTCLK2           net (fanout=2809)     1.018   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.913ns (1.873ns logic, 1.040ns route)
-                                                       (64.3% logic, 35.7% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[1].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<1>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    W22.PAD              Tiockp                3.257   L2P_DATA<1>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[1].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[1].U/OBUF1
-                                                       L2P_DATA<1>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.333ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[1].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<1> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.910ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[1].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.739   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.922   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    W22.OTCLK1           net (fanout=50)       1.015   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.910ns (1.873ns logic, 1.037ns route)
-                                                       (64.4% logic, 35.6% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[1].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<1>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    W22.PAD              Tiockp                3.257   L2P_DATA<1>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[1].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[1].U/OBUF1
-                                                       L2P_DATA<1>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-Fastest Paths: COMP "L2P_DATA<1>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKp" HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<1> (W22.PAD), 2 paths
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.154ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[1].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<1> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.470ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[1].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.470   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    W22.OTCLK2           net (fanout=2809)     0.866   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.470ns (1.587ns logic, 0.883ns route)
-                                                       (64.3% logic, 35.7% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[1].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<1>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    W22.PAD              Tiockp                2.684   L2P_DATA<1>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[1].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[1].U/OBUF1
-                                                       L2P_DATA<1>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.151ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[1].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<1> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.467ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[1].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.733   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.738   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    W22.OTCLK1           net (fanout=50)       0.862   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.467ns (1.588ns logic, 0.879ns route)
-                                                       (64.4% logic, 35.6% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[1].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<1>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    W22.PAD              Tiockp                2.684   L2P_DATA<1>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[1].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[1].U/OBUF1
-                                                       L2P_DATA<1>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "L2P_DATA<1>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKn" 
-HIGH;
-
- 2 paths analyzed, 1 endpoint analyzed, 0 failing endpoints
- 0 timing errors detected.
- Minimum allowable offset is   6.170ns.
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<1> (W22.PAD), 2 paths
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.330ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[1].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<1> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.913ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[1].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.739   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.922   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    W22.OTCLK2           net (fanout=2809)     1.018   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.913ns (1.873ns logic, 1.040ns route)
-                                                       (64.3% logic, 35.7% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[1].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<1>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    W22.PAD              Tiockp                3.257   L2P_DATA<1>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[1].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[1].U/OBUF1
-                                                       L2P_DATA<1>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.333ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[1].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<1> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.910ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[1].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.661   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    W22.OTCLK1           net (fanout=50)       1.015   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.910ns (1.873ns logic, 1.037ns route)
-                                                       (64.4% logic, 35.6% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[1].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<1>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    W22.PAD              Tiockp                3.257   L2P_DATA<1>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[1].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[1].U/OBUF1
-                                                       L2P_DATA<1>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-Fastest Paths: COMP "L2P_DATA<1>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKn" HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<1> (W22.PAD), 2 paths
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.155ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[1].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<1> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.471ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[1].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.733   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.738   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    W22.OTCLK2           net (fanout=2809)     0.866   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.471ns (1.588ns logic, 0.883ns route)
-                                                       (64.3% logic, 35.7% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[1].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<1>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    W22.PAD              Tiockp                2.684   L2P_DATA<1>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[1].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[1].U/OBUF1
-                                                       L2P_DATA<1>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.150ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[1].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<1> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.466ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[1].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.470   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    W22.OTCLK1           net (fanout=50)       0.862   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.466ns (1.587ns logic, 0.879ns route)
-                                                       (64.4% logic, 35.6% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[1].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<1>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    W22.PAD              Tiockp                2.684   L2P_DATA<1>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[1].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[1].U/OBUF1
-                                                       L2P_DATA<1>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "L2P_DATA<2>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKp" 
-HIGH;
-
- 2 paths analyzed, 1 endpoint analyzed, 0 failing endpoints
- 0 timing errors detected.
- Minimum allowable offset is   6.159ns.
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<2> (V20.PAD), 2 paths
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.341ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[2].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<2> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.902ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[2].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.661   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    V20.OTCLK2           net (fanout=2809)     1.007   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.902ns (1.873ns logic, 1.029ns route)
-                                                       (64.5% logic, 35.5% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[2].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<2>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    V20.PAD              Tiockp                3.257   L2P_DATA<2>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[2].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[2].U/OBUF1
-                                                       L2P_DATA<2>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.343ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[2].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<2> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.900ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[2].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.739   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.922   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    V20.OTCLK1           net (fanout=50)       1.005   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.900ns (1.873ns logic, 1.027ns route)
-                                                       (64.6% logic, 35.4% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[2].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<2>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    V20.PAD              Tiockp                3.257   L2P_DATA<2>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[2].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[2].U/OBUF1
-                                                       L2P_DATA<2>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-Fastest Paths: COMP "L2P_DATA<2>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKp" HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<2> (V20.PAD), 2 paths
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.144ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[2].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<2> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.460ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[2].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.470   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    V20.OTCLK2           net (fanout=2809)     0.856   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.460ns (1.587ns logic, 0.873ns route)
-                                                       (64.5% logic, 35.5% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[2].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<2>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    V20.PAD              Tiockp                2.684   L2P_DATA<2>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[2].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[2].U/OBUF1
-                                                       L2P_DATA<2>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.143ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[2].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<2> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.459ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[2].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.733   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.738   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    V20.OTCLK1           net (fanout=50)       0.854   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.459ns (1.588ns logic, 0.871ns route)
-                                                       (64.6% logic, 35.4% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[2].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<2>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    V20.PAD              Tiockp                2.684   L2P_DATA<2>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[2].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[2].U/OBUF1
-                                                       L2P_DATA<2>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "L2P_DATA<2>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKn" 
-HIGH;
-
- 2 paths analyzed, 1 endpoint analyzed, 0 failing endpoints
- 0 timing errors detected.
- Minimum allowable offset is   6.159ns.
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<2> (V20.PAD), 2 paths
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.341ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[2].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<2> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.902ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[2].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.739   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.922   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    V20.OTCLK2           net (fanout=2809)     1.007   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.902ns (1.873ns logic, 1.029ns route)
-                                                       (64.5% logic, 35.5% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[2].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<2>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    V20.PAD              Tiockp                3.257   L2P_DATA<2>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[2].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[2].U/OBUF1
-                                                       L2P_DATA<2>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.343ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[2].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<2> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.900ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[2].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.661   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    V20.OTCLK1           net (fanout=50)       1.005   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.900ns (1.873ns logic, 1.027ns route)
-                                                       (64.6% logic, 35.4% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[2].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<2>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    V20.PAD              Tiockp                3.257   L2P_DATA<2>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[2].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[2].U/OBUF1
-                                                       L2P_DATA<2>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-Fastest Paths: COMP "L2P_DATA<2>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKn" HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<2> (V20.PAD), 2 paths
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.145ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[2].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<2> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.461ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[2].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.733   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.738   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    V20.OTCLK2           net (fanout=2809)     0.856   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.461ns (1.588ns logic, 0.873ns route)
-                                                       (64.5% logic, 35.5% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[2].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<2>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    V20.PAD              Tiockp                2.684   L2P_DATA<2>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[2].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[2].U/OBUF1
-                                                       L2P_DATA<2>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.142ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[2].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<2> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.458ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[2].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.470   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    V20.OTCLK1           net (fanout=50)       0.854   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.458ns (1.587ns logic, 0.871ns route)
-                                                       (64.6% logic, 35.4% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[2].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<2>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    V20.PAD              Tiockp                2.684   L2P_DATA<2>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[2].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[2].U/OBUF1
-                                                       L2P_DATA<2>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "L2P_DATA<3>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKp" 
-HIGH;
-
- 2 paths analyzed, 1 endpoint analyzed, 0 failing endpoints
- 0 timing errors detected.
- Minimum allowable offset is   6.159ns.
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<3> (V19.PAD), 2 paths
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.341ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[3].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<3> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.902ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[3].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.661   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    V19.OTCLK2           net (fanout=2809)     1.007   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.902ns (1.873ns logic, 1.029ns route)
-                                                       (64.5% logic, 35.5% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[3].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<3>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    V19.PAD              Tiockp                3.257   L2P_DATA<3>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[3].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[3].U/OBUF1
-                                                       L2P_DATA<3>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.343ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[3].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<3> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.900ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[3].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.739   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.922   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    V19.OTCLK1           net (fanout=50)       1.005   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.900ns (1.873ns logic, 1.027ns route)
-                                                       (64.6% logic, 35.4% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[3].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<3>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    V19.PAD              Tiockp                3.257   L2P_DATA<3>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[3].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[3].U/OBUF1
-                                                       L2P_DATA<3>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-Fastest Paths: COMP "L2P_DATA<3>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKp" HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<3> (V19.PAD), 2 paths
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.144ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[3].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<3> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.460ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[3].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.470   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    V19.OTCLK2           net (fanout=2809)     0.856   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.460ns (1.587ns logic, 0.873ns route)
-                                                       (64.5% logic, 35.5% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[3].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<3>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    V19.PAD              Tiockp                2.684   L2P_DATA<3>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[3].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[3].U/OBUF1
-                                                       L2P_DATA<3>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.143ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[3].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<3> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.459ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[3].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.733   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.738   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    V19.OTCLK1           net (fanout=50)       0.854   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.459ns (1.588ns logic, 0.871ns route)
-                                                       (64.6% logic, 35.4% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[3].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<3>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    V19.PAD              Tiockp                2.684   L2P_DATA<3>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[3].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[3].U/OBUF1
-                                                       L2P_DATA<3>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "L2P_DATA<3>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKn" 
-HIGH;
-
- 2 paths analyzed, 1 endpoint analyzed, 0 failing endpoints
- 0 timing errors detected.
- Minimum allowable offset is   6.159ns.
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<3> (V19.PAD), 2 paths
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.341ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[3].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<3> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.902ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[3].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.739   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.922   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    V19.OTCLK2           net (fanout=2809)     1.007   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.902ns (1.873ns logic, 1.029ns route)
-                                                       (64.5% logic, 35.5% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[3].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<3>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    V19.PAD              Tiockp                3.257   L2P_DATA<3>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[3].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[3].U/OBUF1
-                                                       L2P_DATA<3>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.343ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[3].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<3> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.900ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[3].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.661   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    V19.OTCLK1           net (fanout=50)       1.005   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.900ns (1.873ns logic, 1.027ns route)
-                                                       (64.6% logic, 35.4% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[3].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<3>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    V19.PAD              Tiockp                3.257   L2P_DATA<3>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[3].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[3].U/OBUF1
-                                                       L2P_DATA<3>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-Fastest Paths: COMP "L2P_DATA<3>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKn" HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<3> (V19.PAD), 2 paths
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.145ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[3].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<3> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.461ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[3].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.733   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.738   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    V19.OTCLK2           net (fanout=2809)     0.856   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.461ns (1.588ns logic, 0.873ns route)
-                                                       (64.5% logic, 35.5% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[3].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<3>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    V19.PAD              Tiockp                2.684   L2P_DATA<3>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[3].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[3].U/OBUF1
-                                                       L2P_DATA<3>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.142ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[3].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<3> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.458ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[3].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.470   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    V19.OTCLK1           net (fanout=50)       0.854   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.458ns (1.587ns logic, 0.871ns route)
-                                                       (64.6% logic, 35.4% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[3].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<3>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    V19.PAD              Tiockp                2.684   L2P_DATA<3>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[3].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[3].U/OBUF1
-                                                       L2P_DATA<3>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "L2P_DATA<4>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKp" 
-HIGH;
-
- 2 paths analyzed, 1 endpoint analyzed, 0 failing endpoints
- 0 timing errors detected.
- Minimum allowable offset is   6.148ns.
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<4> (W21.PAD), 2 paths
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.352ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[4].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<4> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.891ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[4].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.661   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    W21.OTCLK2           net (fanout=2809)     0.996   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.891ns (1.873ns logic, 1.018ns route)
-                                                       (64.8% logic, 35.2% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[4].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<4>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    W21.PAD              Tiockp                3.257   L2P_DATA<4>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[4].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[4].U/OBUF1
-                                                       L2P_DATA<4>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.353ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[4].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<4> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.890ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[4].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.739   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.922   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    W21.OTCLK1           net (fanout=50)       0.995   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.890ns (1.873ns logic, 1.017ns route)
-                                                       (64.8% logic, 35.2% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[4].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<4>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    W21.PAD              Tiockp                3.257   L2P_DATA<4>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[4].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[4].U/OBUF1
-                                                       L2P_DATA<4>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-Fastest Paths: COMP "L2P_DATA<4>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKp" HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<4> (W21.PAD), 2 paths
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.135ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[4].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<4> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.451ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[4].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.470   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    W21.OTCLK2           net (fanout=2809)     0.847   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.451ns (1.587ns logic, 0.864ns route)
-                                                       (64.7% logic, 35.3% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[4].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<4>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    W21.PAD              Tiockp                2.684   L2P_DATA<4>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[4].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[4].U/OBUF1
-                                                       L2P_DATA<4>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.135ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[4].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<4> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.451ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[4].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.733   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.738   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    W21.OTCLK1           net (fanout=50)       0.846   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.451ns (1.588ns logic, 0.863ns route)
-                                                       (64.8% logic, 35.2% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[4].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<4>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    W21.PAD              Tiockp                2.684   L2P_DATA<4>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[4].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[4].U/OBUF1
-                                                       L2P_DATA<4>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "L2P_DATA<4>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKn" 
-HIGH;
-
- 2 paths analyzed, 1 endpoint analyzed, 0 failing endpoints
- 0 timing errors detected.
- Minimum allowable offset is   6.148ns.
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<4> (W21.PAD), 2 paths
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.352ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[4].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<4> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.891ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[4].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.739   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.922   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    W21.OTCLK2           net (fanout=2809)     0.996   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.891ns (1.873ns logic, 1.018ns route)
-                                                       (64.8% logic, 35.2% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[4].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<4>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    W21.PAD              Tiockp                3.257   L2P_DATA<4>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[4].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[4].U/OBUF1
-                                                       L2P_DATA<4>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.353ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[4].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<4> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.890ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[4].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.661   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    W21.OTCLK1           net (fanout=50)       0.995   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.890ns (1.873ns logic, 1.017ns route)
-                                                       (64.8% logic, 35.2% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[4].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<4>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    W21.PAD              Tiockp                3.257   L2P_DATA<4>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[4].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[4].U/OBUF1
-                                                       L2P_DATA<4>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-Fastest Paths: COMP "L2P_DATA<4>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKn" HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<4> (W21.PAD), 2 paths
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.136ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[4].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<4> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.452ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[4].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.733   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.738   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    W21.OTCLK2           net (fanout=2809)     0.847   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.452ns (1.588ns logic, 0.864ns route)
-                                                       (64.8% logic, 35.2% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[4].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<4>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    W21.PAD              Tiockp                2.684   L2P_DATA<4>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[4].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[4].U/OBUF1
-                                                       L2P_DATA<4>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.134ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[4].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<4> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.450ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[4].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.470   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    W21.OTCLK1           net (fanout=50)       0.846   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.450ns (1.587ns logic, 0.863ns route)
-                                                       (64.8% logic, 35.2% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[4].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<4>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    W21.PAD              Tiockp                2.684   L2P_DATA<4>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[4].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[4].U/OBUF1
-                                                       L2P_DATA<4>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "L2P_DATA<5>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKp" 
-HIGH;
-
- 2 paths analyzed, 1 endpoint analyzed, 0 failing endpoints
- 0 timing errors detected.
- Minimum allowable offset is   6.148ns.
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<5> (Y22.PAD), 2 paths
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.352ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[5].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<5> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.891ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[5].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.661   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    Y22.OTCLK2           net (fanout=2809)     0.996   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.891ns (1.873ns logic, 1.018ns route)
-                                                       (64.8% logic, 35.2% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[5].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<5>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    Y22.PAD              Tiockp                3.257   L2P_DATA<5>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[5].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[5].U/OBUF1
-                                                       L2P_DATA<5>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.353ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[5].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<5> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.890ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[5].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.739   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.922   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    Y22.OTCLK1           net (fanout=50)       0.995   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.890ns (1.873ns logic, 1.017ns route)
-                                                       (64.8% logic, 35.2% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[5].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<5>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    Y22.PAD              Tiockp                3.257   L2P_DATA<5>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[5].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[5].U/OBUF1
-                                                       L2P_DATA<5>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-Fastest Paths: COMP "L2P_DATA<5>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKp" HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<5> (Y22.PAD), 2 paths
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.135ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[5].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<5> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.451ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[5].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.470   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    Y22.OTCLK2           net (fanout=2809)     0.847   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.451ns (1.587ns logic, 0.864ns route)
-                                                       (64.7% logic, 35.3% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[5].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<5>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    Y22.PAD              Tiockp                2.684   L2P_DATA<5>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[5].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[5].U/OBUF1
-                                                       L2P_DATA<5>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.135ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[5].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<5> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.451ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[5].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.733   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.738   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    Y22.OTCLK1           net (fanout=50)       0.846   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.451ns (1.588ns logic, 0.863ns route)
-                                                       (64.8% logic, 35.2% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[5].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<5>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    Y22.PAD              Tiockp                2.684   L2P_DATA<5>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[5].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[5].U/OBUF1
-                                                       L2P_DATA<5>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "L2P_DATA<5>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKn" 
-HIGH;
-
- 2 paths analyzed, 1 endpoint analyzed, 0 failing endpoints
- 0 timing errors detected.
- Minimum allowable offset is   6.148ns.
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<5> (Y22.PAD), 2 paths
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.352ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[5].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<5> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.891ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[5].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.739   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.922   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    Y22.OTCLK2           net (fanout=2809)     0.996   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.891ns (1.873ns logic, 1.018ns route)
-                                                       (64.8% logic, 35.2% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[5].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<5>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    Y22.PAD              Tiockp                3.257   L2P_DATA<5>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[5].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[5].U/OBUF1
-                                                       L2P_DATA<5>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.353ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[5].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<5> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.890ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[5].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.661   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    Y22.OTCLK1           net (fanout=50)       0.995   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.890ns (1.873ns logic, 1.017ns route)
-                                                       (64.8% logic, 35.2% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[5].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<5>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    Y22.PAD              Tiockp                3.257   L2P_DATA<5>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[5].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[5].U/OBUF1
-                                                       L2P_DATA<5>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-Fastest Paths: COMP "L2P_DATA<5>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKn" HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<5> (Y22.PAD), 2 paths
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.136ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[5].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<5> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.452ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[5].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.733   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.738   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    Y22.OTCLK2           net (fanout=2809)     0.847   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.452ns (1.588ns logic, 0.864ns route)
-                                                       (64.8% logic, 35.2% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[5].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<5>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    Y22.PAD              Tiockp                2.684   L2P_DATA<5>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[5].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[5].U/OBUF1
-                                                       L2P_DATA<5>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.134ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[5].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<5> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.450ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[5].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.470   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    Y22.OTCLK1           net (fanout=50)       0.846   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.450ns (1.587ns logic, 0.863ns route)
-                                                       (64.8% logic, 35.2% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[5].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<5>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    Y22.PAD              Tiockp                2.684   L2P_DATA<5>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[5].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[5].U/OBUF1
-                                                       L2P_DATA<5>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "L2P_DATA<6>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKp" 
-HIGH;
-
- 2 paths analyzed, 1 endpoint analyzed, 0 failing endpoints
- 0 timing errors detected.
- Minimum allowable offset is   6.163ns.
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<6> (T18.PAD), 2 paths
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.337ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[6].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<6> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.906ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[6].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.661   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    T18.OTCLK2           net (fanout=2809)     1.011   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.906ns (1.873ns logic, 1.033ns route)
-                                                       (64.5% logic, 35.5% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[6].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<6>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    T18.PAD              Tiockp                3.257   L2P_DATA<6>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[6].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[6].U/OBUF1
-                                                       L2P_DATA<6>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.339ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[6].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<6> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.904ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[6].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.739   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.922   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    T18.OTCLK1           net (fanout=50)       1.009   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.904ns (1.873ns logic, 1.031ns route)
-                                                       (64.5% logic, 35.5% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[6].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<6>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    T18.PAD              Tiockp                3.257   L2P_DATA<6>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[6].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[6].U/OBUF1
-                                                       L2P_DATA<6>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-Fastest Paths: COMP "L2P_DATA<6>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKp" HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<6> (T18.PAD), 2 paths
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.147ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[6].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<6> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.463ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[6].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.470   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    T18.OTCLK2           net (fanout=2809)     0.859   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.463ns (1.587ns logic, 0.876ns route)
-                                                       (64.4% logic, 35.6% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[6].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<6>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    T18.PAD              Tiockp                2.684   L2P_DATA<6>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[6].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[6].U/OBUF1
-                                                       L2P_DATA<6>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.147ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[6].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<6> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.463ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[6].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.733   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.738   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    T18.OTCLK1           net (fanout=50)       0.858   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.463ns (1.588ns logic, 0.875ns route)
-                                                       (64.5% logic, 35.5% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[6].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<6>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    T18.PAD              Tiockp                2.684   L2P_DATA<6>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[6].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[6].U/OBUF1
-                                                       L2P_DATA<6>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "L2P_DATA<6>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKn" 
-HIGH;
-
- 2 paths analyzed, 1 endpoint analyzed, 0 failing endpoints
- 0 timing errors detected.
- Minimum allowable offset is   6.163ns.
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<6> (T18.PAD), 2 paths
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.337ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[6].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<6> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.906ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[6].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.739   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.922   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    T18.OTCLK2           net (fanout=2809)     1.011   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.906ns (1.873ns logic, 1.033ns route)
-                                                       (64.5% logic, 35.5% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[6].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<6>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    T18.PAD              Tiockp                3.257   L2P_DATA<6>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[6].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[6].U/OBUF1
-                                                       L2P_DATA<6>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.339ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[6].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<6> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.904ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[6].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.661   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    T18.OTCLK1           net (fanout=50)       1.009   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.904ns (1.873ns logic, 1.031ns route)
-                                                       (64.5% logic, 35.5% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[6].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<6>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    T18.PAD              Tiockp                3.257   L2P_DATA<6>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[6].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[6].U/OBUF1
-                                                       L2P_DATA<6>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-Fastest Paths: COMP "L2P_DATA<6>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKn" HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<6> (T18.PAD), 2 paths
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.148ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[6].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<6> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.464ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[6].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.733   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.738   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    T18.OTCLK2           net (fanout=2809)     0.859   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.464ns (1.588ns logic, 0.876ns route)
-                                                       (64.4% logic, 35.6% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[6].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<6>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    T18.PAD              Tiockp                2.684   L2P_DATA<6>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[6].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[6].U/OBUF1
-                                                       L2P_DATA<6>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.146ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[6].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<6> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.462ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[6].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.470   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    T18.OTCLK1           net (fanout=50)       0.858   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.462ns (1.587ns logic, 0.875ns route)
-                                                       (64.5% logic, 35.5% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[6].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<6>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    T18.PAD              Tiockp                2.684   L2P_DATA<6>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[6].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[6].U/OBUF1
-                                                       L2P_DATA<6>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "L2P_DATA<7>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKp" 
-HIGH;
-
- 2 paths analyzed, 1 endpoint analyzed, 0 failing endpoints
- 0 timing errors detected.
- Minimum allowable offset is   6.163ns.
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<7> (T17.PAD), 2 paths
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.337ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[7].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<7> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.906ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[7].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.661   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    T17.OTCLK2           net (fanout=2809)     1.011   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.906ns (1.873ns logic, 1.033ns route)
-                                                       (64.5% logic, 35.5% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[7].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<7>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    T17.PAD              Tiockp                3.257   L2P_DATA<7>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[7].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[7].U/OBUF1
-                                                       L2P_DATA<7>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.339ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[7].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<7> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.904ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[7].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.739   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.922   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    T17.OTCLK1           net (fanout=50)       1.009   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.904ns (1.873ns logic, 1.031ns route)
-                                                       (64.5% logic, 35.5% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[7].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<7>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    T17.PAD              Tiockp                3.257   L2P_DATA<7>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[7].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[7].U/OBUF1
-                                                       L2P_DATA<7>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-Fastest Paths: COMP "L2P_DATA<7>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKp" HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<7> (T17.PAD), 2 paths
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.147ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[7].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<7> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.463ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[7].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.470   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    T17.OTCLK2           net (fanout=2809)     0.859   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.463ns (1.587ns logic, 0.876ns route)
-                                                       (64.4% logic, 35.6% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[7].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<7>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    T17.PAD              Tiockp                2.684   L2P_DATA<7>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[7].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[7].U/OBUF1
-                                                       L2P_DATA<7>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.147ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[7].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<7> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.463ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[7].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.733   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.738   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    T17.OTCLK1           net (fanout=50)       0.858   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.463ns (1.588ns logic, 0.875ns route)
-                                                       (64.5% logic, 35.5% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[7].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<7>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    T17.PAD              Tiockp                2.684   L2P_DATA<7>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[7].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[7].U/OBUF1
-                                                       L2P_DATA<7>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "L2P_DATA<7>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKn" 
-HIGH;
-
- 2 paths analyzed, 1 endpoint analyzed, 0 failing endpoints
- 0 timing errors detected.
- Minimum allowable offset is   6.163ns.
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<7> (T17.PAD), 2 paths
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.337ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[7].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<7> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.906ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[7].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.739   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.922   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    T17.OTCLK2           net (fanout=2809)     1.011   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.906ns (1.873ns logic, 1.033ns route)
-                                                       (64.5% logic, 35.5% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[7].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<7>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    T17.PAD              Tiockp                3.257   L2P_DATA<7>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[7].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[7].U/OBUF1
-                                                       L2P_DATA<7>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.339ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[7].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<7> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.904ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[7].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.661   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    T17.OTCLK1           net (fanout=50)       1.009   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.904ns (1.873ns logic, 1.031ns route)
-                                                       (64.5% logic, 35.5% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[7].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<7>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    T17.PAD              Tiockp                3.257   L2P_DATA<7>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[7].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[7].U/OBUF1
-                                                       L2P_DATA<7>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-Fastest Paths: COMP "L2P_DATA<7>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKn" HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<7> (T17.PAD), 2 paths
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.148ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[7].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<7> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.464ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[7].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.733   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.738   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    T17.OTCLK2           net (fanout=2809)     0.859   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.464ns (1.588ns logic, 0.876ns route)
-                                                       (64.4% logic, 35.6% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[7].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<7>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    T17.PAD              Tiockp                2.684   L2P_DATA<7>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[7].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[7].U/OBUF1
-                                                       L2P_DATA<7>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.146ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[7].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<7> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.462ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[7].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.470   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    T17.OTCLK1           net (fanout=50)       0.858   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.462ns (1.587ns logic, 0.875ns route)
-                                                       (64.5% logic, 35.5% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[7].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<7>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    T17.PAD              Tiockp                2.684   L2P_DATA<7>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[7].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[7].U/OBUF1
-                                                       L2P_DATA<7>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "L2P_DATA<8>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKp" 
-HIGH;
-
- 2 paths analyzed, 1 endpoint analyzed, 0 failing endpoints
- 0 timing errors detected.
- Minimum allowable offset is   6.170ns.
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<8> (W20.PAD), 2 paths
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.330ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[8].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<8> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.913ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[8].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.661   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    W20.OTCLK2           net (fanout=2809)     1.018   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.913ns (1.873ns logic, 1.040ns route)
-                                                       (64.3% logic, 35.7% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[8].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<8>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    W20.PAD              Tiockp                3.257   L2P_DATA<8>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[8].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[8].U/OBUF1
-                                                       L2P_DATA<8>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.332ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[8].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<8> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.911ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[8].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.739   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.922   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    W20.OTCLK1           net (fanout=50)       1.016   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.911ns (1.873ns logic, 1.038ns route)
-                                                       (64.3% logic, 35.7% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[8].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<8>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    W20.PAD              Tiockp                3.257   L2P_DATA<8>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[8].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[8].U/OBUF1
-                                                       L2P_DATA<8>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-Fastest Paths: COMP "L2P_DATA<8>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKp" HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<8> (W20.PAD), 2 paths
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.153ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[8].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<8> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.469ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[8].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.470   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    W20.OTCLK2           net (fanout=2809)     0.865   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.469ns (1.587ns logic, 0.882ns route)
-                                                       (64.3% logic, 35.7% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[8].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<8>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    W20.PAD              Tiockp                2.684   L2P_DATA<8>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[8].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[8].U/OBUF1
-                                                       L2P_DATA<8>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.153ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[8].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<8> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.469ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[8].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.733   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.738   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    W20.OTCLK1           net (fanout=50)       0.864   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.469ns (1.588ns logic, 0.881ns route)
-                                                       (64.3% logic, 35.7% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[8].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<8>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    W20.PAD              Tiockp                2.684   L2P_DATA<8>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[8].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[8].U/OBUF1
-                                                       L2P_DATA<8>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "L2P_DATA<8>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKn" 
-HIGH;
-
- 2 paths analyzed, 1 endpoint analyzed, 0 failing endpoints
- 0 timing errors detected.
- Minimum allowable offset is   6.170ns.
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<8> (W20.PAD), 2 paths
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.330ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[8].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<8> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.913ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[8].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.739   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.922   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    W20.OTCLK2           net (fanout=2809)     1.018   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.913ns (1.873ns logic, 1.040ns route)
-                                                       (64.3% logic, 35.7% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[8].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<8>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    W20.PAD              Tiockp                3.257   L2P_DATA<8>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[8].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[8].U/OBUF1
-                                                       L2P_DATA<8>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.332ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[8].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<8> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.911ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[8].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.661   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    W20.OTCLK1           net (fanout=50)       1.016   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.911ns (1.873ns logic, 1.038ns route)
-                                                       (64.3% logic, 35.7% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[8].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<8>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    W20.PAD              Tiockp                3.257   L2P_DATA<8>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[8].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[8].U/OBUF1
-                                                       L2P_DATA<8>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-Fastest Paths: COMP "L2P_DATA<8>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKn" HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<8> (W20.PAD), 2 paths
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.154ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[8].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<8> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.470ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[8].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.733   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.738   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    W20.OTCLK2           net (fanout=2809)     0.865   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.470ns (1.588ns logic, 0.882ns route)
-                                                       (64.3% logic, 35.7% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[8].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<8>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    W20.PAD              Tiockp                2.684   L2P_DATA<8>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[8].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[8].U/OBUF1
-                                                       L2P_DATA<8>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.152ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[8].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<8> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.468ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[8].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.470   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    W20.OTCLK1           net (fanout=50)       0.864   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.468ns (1.587ns logic, 0.881ns route)
-                                                       (64.3% logic, 35.7% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[8].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<8>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    W20.PAD              Tiockp                2.684   L2P_DATA<8>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[8].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[8].U/OBUF1
-                                                       L2P_DATA<8>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "L2P_DATA<9>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKp" 
-HIGH;
-
- 2 paths analyzed, 1 endpoint analyzed, 0 failing endpoints
- 0 timing errors detected.
- Minimum allowable offset is   6.170ns.
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<9> (W19.PAD), 2 paths
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.330ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[9].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<9> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.913ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[9].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.661   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    W19.OTCLK2           net (fanout=2809)     1.018   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.913ns (1.873ns logic, 1.040ns route)
-                                                       (64.3% logic, 35.7% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[9].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<9>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    W19.PAD              Tiockp                3.257   L2P_DATA<9>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[9].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[9].U/OBUF1
-                                                       L2P_DATA<9>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.332ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[9].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<9> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.911ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[9].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.739   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.922   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    W19.OTCLK1           net (fanout=50)       1.016   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.911ns (1.873ns logic, 1.038ns route)
-                                                       (64.3% logic, 35.7% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[9].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<9>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    W19.PAD              Tiockp                3.257   L2P_DATA<9>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[9].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[9].U/OBUF1
-                                                       L2P_DATA<9>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-Fastest Paths: COMP "L2P_DATA<9>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKp" HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<9> (W19.PAD), 2 paths
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.153ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[9].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<9> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.469ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[9].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.470   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    W19.OTCLK2           net (fanout=2809)     0.865   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.469ns (1.587ns logic, 0.882ns route)
-                                                       (64.3% logic, 35.7% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[9].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<9>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    W19.PAD              Tiockp                2.684   L2P_DATA<9>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[9].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[9].U/OBUF1
-                                                       L2P_DATA<9>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.153ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[9].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<9> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.469ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[9].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.733   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.738   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    W19.OTCLK1           net (fanout=50)       0.864   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.469ns (1.588ns logic, 0.881ns route)
-                                                       (64.3% logic, 35.7% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[9].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<9>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    W19.PAD              Tiockp                2.684   L2P_DATA<9>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[9].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[9].U/OBUF1
-                                                       L2P_DATA<9>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "L2P_DATA<9>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKn" 
-HIGH;
-
- 2 paths analyzed, 1 endpoint analyzed, 0 failing endpoints
- 0 timing errors detected.
- Minimum allowable offset is   6.170ns.
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<9> (W19.PAD), 2 paths
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.330ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[9].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<9> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.913ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[9].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.739   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.922   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    W19.OTCLK2           net (fanout=2809)     1.018   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.913ns (1.873ns logic, 1.040ns route)
-                                                       (64.3% logic, 35.7% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[9].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<9>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    W19.PAD              Tiockp                3.257   L2P_DATA<9>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[9].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[9].U/OBUF1
-                                                       L2P_DATA<9>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.332ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[9].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<9> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.911ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[9].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.661   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    W19.OTCLK1           net (fanout=50)       1.016   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.911ns (1.873ns logic, 1.038ns route)
-                                                       (64.3% logic, 35.7% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[9].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<9>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    W19.PAD              Tiockp                3.257   L2P_DATA<9>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[9].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[9].U/OBUF1
-                                                       L2P_DATA<9>
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-Fastest Paths: COMP "L2P_DATA<9>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKn" HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DATA<9> (W19.PAD), 2 paths
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.154ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[9].U/FDDRRSE1/ODDR2/FF1 (FF)
-  Destination:          L2P_DATA<9> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_p rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.470ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[9].U/FDDRRSE1/ODDR2/FF1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.733   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.738   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    W19.OTCLK2           net (fanout=2809)     0.865   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.470ns (1.588ns logic, 0.882ns route)
-                                                       (64.3% logic, 35.7% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[9].U/FDDRRSE1/ODDR2/FF1 to L2P_DATA<9>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    W19.PAD              Tiockp                2.684   L2P_DATA<9>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[9].U/FDDRRSE1/ODDR2/FF1
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[9].U/OBUF1
-                                                       L2P_DATA<9>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.152ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[9].U/FDDRRSE1/ODDR2/FF0 (FF)
-  Destination:          L2P_DATA<9> (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.468ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[9].U/FDDRRSE1/ODDR2/FF0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.470   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    W19.OTCLK1           net (fanout=50)       0.864   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.468ns (1.587ns logic, 0.881ns route)
-                                                       (64.3% logic, 35.7% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[9].U/FDDRRSE1/ODDR2/FF0 to L2P_DATA<9>
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    W19.PAD              Tiockp                2.684   L2P_DATA<9>
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[9].U/FDDRRSE1/ODDR2/FF0
-                                                       cmp_gn4124_core/cmp_l2p_ser/gen_out_ddr_ff.DDROUT[9].U/OBUF1
-                                                       L2P_DATA<9>
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "L2P_DFRAME" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKn" 
-HIGH;
-
- 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints
- 0 timing errors detected.
- Minimum allowable offset is   6.174ns.
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DFRAME (J22.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.326ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/l2p_dframe_o (FF)
-  Destination:          L2P_DFRAME (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.917ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/l2p_dframe_o
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.661   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    J22.OTCLK1           net (fanout=50)       1.022   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.917ns (1.873ns logic, 1.044ns route)
-                                                       (64.2% logic, 35.8% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/l2p_dframe_o to L2P_DFRAME
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    J22.PAD              Tiockp                3.257   L2P_DFRAME
-                                                       cmp_gn4124_core/cmp_l2p_ser/l2p_dframe_o
-                                                       L2P_DFRAME_OBUF
-                                                       L2P_DFRAME
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-Fastest Paths: COMP "L2P_DFRAME" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKn" HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point L2P_DFRAME (J22.PAD), 1 path
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.157ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/l2p_dframe_o (FF)
-  Destination:          L2P_DFRAME (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.473ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/l2p_dframe_o
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.470   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    J22.OTCLK1           net (fanout=50)       0.869   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.473ns (1.587ns logic, 0.886ns route)
-                                                       (64.2% logic, 35.8% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/l2p_dframe_o to L2P_DFRAME
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    J22.PAD              Tiockp                2.684   L2P_DFRAME
-                                                       cmp_gn4124_core/cmp_l2p_ser/l2p_dframe_o
-                                                       L2P_DFRAME_OBUF
-                                                       L2P_DFRAME
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "L2P_VALID" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKn" 
-HIGH;
-
- 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints
- 0 timing errors detected.
- Minimum allowable offset is   6.122ns.
---------------------------------------------------------------------------------
-
-Paths for end point L2P_VALID (T19.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (slowest paths):  0.378ns (requirement - (clock arrival + clock path + data path + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_ser/l2p_valid_o (FF)
-  Destination:          L2P_VALID (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          6.500ns
-  Data Path Delay:      3.257ns (Levels of Logic = 0)
-  Clock Path Delay:     2.865ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/l2p_valid_o
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.661   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    T19.OTCLK1           net (fanout=50)       0.970   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.865ns (1.873ns logic, 0.992ns route)
-                                                       (65.4% logic, 34.6% route)
-
-  Maximum Data Path: cmp_gn4124_core/cmp_l2p_ser/l2p_valid_o to L2P_VALID
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    T19.PAD              Tiockp                3.257   L2P_VALID
-                                                       cmp_gn4124_core/cmp_l2p_ser/l2p_valid_o
-                                                       L2P_VALID_OBUF
-                                                       L2P_VALID
-    -------------------------------------------------  ---------------------------
-    Total                                      3.257ns (3.257ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-Fastest Paths: COMP "L2P_VALID" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKn" HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point L2P_VALID (T19.PAD), 1 path
---------------------------------------------------------------------------------
-Delay (fastest paths):  5.112ns (clock arrival + clock path + data path - uncertainty)
-  Source:               cmp_gn4124_core/cmp_l2p_ser/l2p_valid_o (FF)
-  Destination:          L2P_VALID (PAD)
-  Source Clock:         cmp_gn4124_core/clk_n rising at 0.000ns
-  Data Path Delay:      2.684ns (Levels of Logic = 0)
-  Clock Path Delay:     2.428ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_l2p_ser/l2p_valid_o
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.470   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    T19.OTCLK1           net (fanout=50)       0.824   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.428ns (1.587ns logic, 0.841ns route)
-                                                       (65.4% logic, 34.6% route)
-
-  Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/l2p_valid_o to L2P_VALID
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    T19.PAD              Tiockp                2.684   L2P_VALID
-                                                       cmp_gn4124_core/cmp_l2p_ser/l2p_valid_o
-                                                       L2P_VALID_OBUF
-                                                       L2P_VALID
-    -------------------------------------------------  ---------------------------
-    Total                                      2.684ns (2.684ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "P2L_DATA<0>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE 
-COMP "P2L_CLKp"         HIGH;
-
- 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors)
- Minimum allowable offset is   0.792ns.
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[0].U/FDRSE1 (E22.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.408ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<0> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[0].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.458ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<0> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[0].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E22.ICLK2            Tiopickd              3.250   P2L_DATA<0>
-                                                       P2L_DATA<0>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[0].U/IBUF1
-                                                       P2L_DATA<0>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[0].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[0].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.470   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    E22.ICLK2            net (fanout=2809)     0.854   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.458ns (1.587ns logic, 0.871ns route)
-                                                       (64.6% logic, 35.4% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[0].U/FDRSE0 (E22.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.409ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<0> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[0].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.459ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<0> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[0].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E22.ICLK1            Tiopickd              3.250   P2L_DATA<0>
-                                                       P2L_DATA<0>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[0].U/IBUF1
-                                                       P2L_DATA<0>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[0].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[0].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.733   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.738   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    E22.ICLK1            net (fanout=50)       0.854   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.459ns (1.588ns logic, 0.871ns route)
-                                                       (64.6% logic, 35.4% route)
-
---------------------------------------------------------------------------------
-
-Hold Paths: COMP "P2L_DATA<0>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKp"
-        HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[0].U/FDRSE0 (E22.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.271ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<0> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[0].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.899ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<0> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[0].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E22.ICLK1            Tioickpd    (-Th)    -2.770   P2L_DATA<0>
-                                                       P2L_DATA<0>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[0].U/IBUF1
-                                                       P2L_DATA<0>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[0].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[0].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.739   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.922   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    E22.ICLK1            net (fanout=50)       1.004   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.899ns (1.873ns logic, 1.026ns route)
-                                                       (64.6% logic, 35.4% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[0].U/FDRSE1 (E22.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.271ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<0> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[0].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.899ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<0> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[0].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E22.ICLK2            Tioickpd    (-Th)    -2.770   P2L_DATA<0>
-                                                       P2L_DATA<0>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[0].U/IBUF1
-                                                       P2L_DATA<0>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[0].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[0].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.661   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    E22.ICLK2            net (fanout=2809)     1.004   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.899ns (1.873ns logic, 1.026ns route)
-                                                       (64.6% logic, 35.4% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "P2L_DATA<0>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE 
-COMP "P2L_CLKn"         HIGH;
-
- 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors)
- Minimum allowable offset is   0.792ns.
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[0].U/FDRSE0 (E22.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.408ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<0> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[0].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.458ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<0> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[0].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E22.ICLK1            Tiopickd              3.250   P2L_DATA<0>
-                                                       P2L_DATA<0>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[0].U/IBUF1
-                                                       P2L_DATA<0>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[0].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[0].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.470   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    E22.ICLK1            net (fanout=50)       0.854   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.458ns (1.587ns logic, 0.871ns route)
-                                                       (64.6% logic, 35.4% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[0].U/FDRSE1 (E22.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.409ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<0> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[0].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.459ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<0> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[0].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E22.ICLK2            Tiopickd              3.250   P2L_DATA<0>
-                                                       P2L_DATA<0>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[0].U/IBUF1
-                                                       P2L_DATA<0>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[0].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[0].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.733   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.738   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    E22.ICLK2            net (fanout=2809)     0.854   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.459ns (1.588ns logic, 0.871ns route)
-                                                       (64.6% logic, 35.4% route)
-
---------------------------------------------------------------------------------
-
-Hold Paths: COMP "P2L_DATA<0>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKn"
-        HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[0].U/FDRSE0 (E22.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.271ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<0> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[0].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.899ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<0> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[0].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E22.ICLK1            Tioickpd    (-Th)    -2.770   P2L_DATA<0>
-                                                       P2L_DATA<0>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[0].U/IBUF1
-                                                       P2L_DATA<0>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[0].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[0].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.661   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    E22.ICLK1            net (fanout=50)       1.004   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.899ns (1.873ns logic, 1.026ns route)
-                                                       (64.6% logic, 35.4% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[0].U/FDRSE1 (E22.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.271ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<0> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[0].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.899ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<0> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[0].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E22.ICLK2            Tioickpd    (-Th)    -2.770   P2L_DATA<0>
-                                                       P2L_DATA<0>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[0].U/IBUF1
-                                                       P2L_DATA<0>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[0].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[0].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.739   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.922   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    E22.ICLK2            net (fanout=2809)     1.004   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.899ns (1.873ns logic, 1.026ns route)
-                                                       (64.6% logic, 35.4% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "P2L_DATA<10>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE 
-COMP "P2L_CLKp"         HIGH;
-
- 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors)
- Minimum allowable offset is   0.779ns.
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[10].U/FDRSE1 (K19.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.421ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<10> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[10].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.471ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<10> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[10].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    K19.ICLK2            Tiopickd              3.250   P2L_DATA<10>
-                                                       P2L_DATA<10>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[10].U/IBUF1
-                                                       P2L_DATA<10>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[10].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[10].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.470   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    K19.ICLK2            net (fanout=2809)     0.867   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.471ns (1.587ns logic, 0.884ns route)
-                                                       (64.2% logic, 35.8% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[10].U/FDRSE0 (K19.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.430ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<10> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[10].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.480ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<10> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[10].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    K19.ICLK1            Tiopickd              3.250   P2L_DATA<10>
-                                                       P2L_DATA<10>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[10].U/IBUF1
-                                                       P2L_DATA<10>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[10].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[10].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.733   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.738   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    K19.ICLK1            net (fanout=50)       0.875   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.480ns (1.588ns logic, 0.892ns route)
-                                                       (64.0% logic, 36.0% route)
-
---------------------------------------------------------------------------------
-
-Hold Paths: COMP "P2L_DATA<10>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKp"
-        HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[10].U/FDRSE0 (K19.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.246ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<10> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[10].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.924ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<10> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[10].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    K19.ICLK1            Tioickpd    (-Th)    -2.770   P2L_DATA<10>
-                                                       P2L_DATA<10>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[10].U/IBUF1
-                                                       P2L_DATA<10>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[10].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[10].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.739   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.922   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    K19.ICLK1            net (fanout=50)       1.029   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.924ns (1.873ns logic, 1.051ns route)
-                                                       (64.1% logic, 35.9% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[10].U/FDRSE1 (K19.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.254ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<10> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[10].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.916ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<10> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[10].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    K19.ICLK2            Tioickpd    (-Th)    -2.770   P2L_DATA<10>
-                                                       P2L_DATA<10>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[10].U/IBUF1
-                                                       P2L_DATA<10>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[10].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[10].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.661   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    K19.ICLK2            net (fanout=2809)     1.021   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.916ns (1.873ns logic, 1.043ns route)
-                                                       (64.2% logic, 35.8% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "P2L_DATA<10>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE 
-COMP "P2L_CLKn"         HIGH;
-
- 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors)
- Minimum allowable offset is   0.778ns.
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[10].U/FDRSE1 (K19.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.422ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<10> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[10].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.472ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<10> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[10].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    K19.ICLK2            Tiopickd              3.250   P2L_DATA<10>
-                                                       P2L_DATA<10>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[10].U/IBUF1
-                                                       P2L_DATA<10>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[10].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[10].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.733   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.738   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    K19.ICLK2            net (fanout=2809)     0.867   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.472ns (1.588ns logic, 0.884ns route)
-                                                       (64.2% logic, 35.8% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[10].U/FDRSE0 (K19.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.429ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<10> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[10].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.479ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<10> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[10].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    K19.ICLK1            Tiopickd              3.250   P2L_DATA<10>
-                                                       P2L_DATA<10>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[10].U/IBUF1
-                                                       P2L_DATA<10>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[10].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[10].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.470   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    K19.ICLK1            net (fanout=50)       0.875   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.479ns (1.587ns logic, 0.892ns route)
-                                                       (64.0% logic, 36.0% route)
-
---------------------------------------------------------------------------------
-
-Hold Paths: COMP "P2L_DATA<10>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKn"
-        HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[10].U/FDRSE0 (K19.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.246ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<10> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[10].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.924ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<10> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[10].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    K19.ICLK1            Tioickpd    (-Th)    -2.770   P2L_DATA<10>
-                                                       P2L_DATA<10>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[10].U/IBUF1
-                                                       P2L_DATA<10>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[10].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[10].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.661   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    K19.ICLK1            net (fanout=50)       1.029   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.924ns (1.873ns logic, 1.051ns route)
-                                                       (64.1% logic, 35.9% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[10].U/FDRSE1 (K19.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.254ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<10> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[10].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.916ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<10> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[10].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    K19.ICLK2            Tioickpd    (-Th)    -2.770   P2L_DATA<10>
-                                                       P2L_DATA<10>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[10].U/IBUF1
-                                                       P2L_DATA<10>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[10].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[10].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.739   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.922   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    K19.ICLK2            net (fanout=2809)     1.021   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.916ns (1.873ns logic, 1.043ns route)
-                                                       (64.2% logic, 35.8% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "P2L_DATA<11>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE 
-COMP "P2L_CLKp"         HIGH;
-
- 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors)
- Minimum allowable offset is   0.775ns.
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[11].U/FDRSE1 (M20.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.425ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<11> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[11].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.475ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<11> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[11].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    M20.ICLK2            Tiopickd              3.250   P2L_DATA<11>
-                                                       P2L_DATA<11>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[11].U/IBUF1
-                                                       P2L_DATA<11>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[11].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[11].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.470   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    M20.ICLK2            net (fanout=2809)     0.871   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.475ns (1.587ns logic, 0.888ns route)
-                                                       (64.1% logic, 35.9% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[11].U/FDRSE0 (M20.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.433ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<11> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[11].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.483ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<11> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[11].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    M20.ICLK1            Tiopickd              3.250   P2L_DATA<11>
-                                                       P2L_DATA<11>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[11].U/IBUF1
-                                                       P2L_DATA<11>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[11].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[11].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.733   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.738   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    M20.ICLK1            net (fanout=50)       0.878   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.483ns (1.588ns logic, 0.895ns route)
-                                                       (64.0% logic, 36.0% route)
-
---------------------------------------------------------------------------------
-
-Hold Paths: COMP "P2L_DATA<11>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKp"
-        HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[11].U/FDRSE0 (M20.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.242ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<11> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[11].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.928ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<11> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[11].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    M20.ICLK1            Tioickpd    (-Th)    -2.770   P2L_DATA<11>
-                                                       P2L_DATA<11>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[11].U/IBUF1
-                                                       P2L_DATA<11>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[11].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[11].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.739   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.922   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    M20.ICLK1            net (fanout=50)       1.033   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.928ns (1.873ns logic, 1.055ns route)
-                                                       (64.0% logic, 36.0% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[11].U/FDRSE1 (M20.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.250ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<11> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[11].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.920ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<11> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[11].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    M20.ICLK2            Tioickpd    (-Th)    -2.770   P2L_DATA<11>
-                                                       P2L_DATA<11>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[11].U/IBUF1
-                                                       P2L_DATA<11>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[11].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[11].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.661   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    M20.ICLK2            net (fanout=2809)     1.025   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.920ns (1.873ns logic, 1.047ns route)
-                                                       (64.1% logic, 35.9% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "P2L_DATA<11>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE 
-COMP "P2L_CLKn"         HIGH;
-
- 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors)
- Minimum allowable offset is   0.774ns.
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[11].U/FDRSE1 (M20.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.426ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<11> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[11].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.476ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<11> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[11].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    M20.ICLK2            Tiopickd              3.250   P2L_DATA<11>
-                                                       P2L_DATA<11>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[11].U/IBUF1
-                                                       P2L_DATA<11>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[11].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[11].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.733   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.738   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    M20.ICLK2            net (fanout=2809)     0.871   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.476ns (1.588ns logic, 0.888ns route)
-                                                       (64.1% logic, 35.9% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[11].U/FDRSE0 (M20.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.432ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<11> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[11].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.482ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<11> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[11].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    M20.ICLK1            Tiopickd              3.250   P2L_DATA<11>
-                                                       P2L_DATA<11>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[11].U/IBUF1
-                                                       P2L_DATA<11>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[11].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[11].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.470   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    M20.ICLK1            net (fanout=50)       0.878   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.482ns (1.587ns logic, 0.895ns route)
-                                                       (63.9% logic, 36.1% route)
-
---------------------------------------------------------------------------------
-
-Hold Paths: COMP "P2L_DATA<11>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKn"
-        HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[11].U/FDRSE0 (M20.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.242ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<11> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[11].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.928ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<11> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[11].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    M20.ICLK1            Tioickpd    (-Th)    -2.770   P2L_DATA<11>
-                                                       P2L_DATA<11>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[11].U/IBUF1
-                                                       P2L_DATA<11>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[11].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[11].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.661   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    M20.ICLK1            net (fanout=50)       1.033   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.928ns (1.873ns logic, 1.055ns route)
-                                                       (64.0% logic, 36.0% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[11].U/FDRSE1 (M20.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.250ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<11> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[11].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.920ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<11> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[11].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    M20.ICLK2            Tioickpd    (-Th)    -2.770   P2L_DATA<11>
-                                                       P2L_DATA<11>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[11].U/IBUF1
-                                                       P2L_DATA<11>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[11].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[11].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.739   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.922   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    M20.ICLK2            net (fanout=2809)     1.025   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.920ns (1.873ns logic, 1.047ns route)
-                                                       (64.1% logic, 35.9% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "P2L_DATA<12>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE 
-COMP "P2L_CLKp"         HIGH;
-
- 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors)
- Minimum allowable offset is   0.815ns.
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[12].U/FDRSE1 (G22.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.385ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<12> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[12].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.435ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<12> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[12].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    G22.ICLK2            Tiopickd              3.250   P2L_DATA<12>
-                                                       P2L_DATA<12>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[12].U/IBUF1
-                                                       P2L_DATA<12>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[12].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[12].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.470   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    G22.ICLK2            net (fanout=2809)     0.831   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.435ns (1.587ns logic, 0.848ns route)
-                                                       (65.2% logic, 34.8% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[12].U/FDRSE0 (G22.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.388ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<12> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[12].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.438ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<12> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[12].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    G22.ICLK1            Tiopickd              3.250   P2L_DATA<12>
-                                                       P2L_DATA<12>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[12].U/IBUF1
-                                                       P2L_DATA<12>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[12].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[12].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.733   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.738   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    G22.ICLK1            net (fanout=50)       0.833   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.438ns (1.588ns logic, 0.850ns route)
-                                                       (65.1% logic, 34.9% route)
-
---------------------------------------------------------------------------------
-
-Hold Paths: COMP "P2L_DATA<12>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKp"
-        HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[12].U/FDRSE0 (G22.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.295ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<12> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[12].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.875ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<12> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[12].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    G22.ICLK1            Tioickpd    (-Th)    -2.770   P2L_DATA<12>
-                                                       P2L_DATA<12>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[12].U/IBUF1
-                                                       P2L_DATA<12>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[12].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[12].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.739   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.922   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    G22.ICLK1            net (fanout=50)       0.980   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.875ns (1.873ns logic, 1.002ns route)
-                                                       (65.1% logic, 34.9% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[12].U/FDRSE1 (G22.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.297ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<12> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[12].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.873ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<12> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[12].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    G22.ICLK2            Tioickpd    (-Th)    -2.770   P2L_DATA<12>
-                                                       P2L_DATA<12>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[12].U/IBUF1
-                                                       P2L_DATA<12>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[12].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[12].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.661   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    G22.ICLK2            net (fanout=2809)     0.978   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.873ns (1.873ns logic, 1.000ns route)
-                                                       (65.2% logic, 34.8% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "P2L_DATA<12>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE 
-COMP "P2L_CLKn"         HIGH;
-
- 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors)
- Minimum allowable offset is   0.814ns.
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[12].U/FDRSE1 (G22.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.386ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<12> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[12].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.436ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<12> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[12].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    G22.ICLK2            Tiopickd              3.250   P2L_DATA<12>
-                                                       P2L_DATA<12>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[12].U/IBUF1
-                                                       P2L_DATA<12>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[12].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[12].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.733   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.738   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    G22.ICLK2            net (fanout=2809)     0.831   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.436ns (1.588ns logic, 0.848ns route)
-                                                       (65.2% logic, 34.8% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[12].U/FDRSE0 (G22.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.387ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<12> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[12].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.437ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<12> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[12].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    G22.ICLK1            Tiopickd              3.250   P2L_DATA<12>
-                                                       P2L_DATA<12>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[12].U/IBUF1
-                                                       P2L_DATA<12>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[12].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[12].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.470   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    G22.ICLK1            net (fanout=50)       0.833   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.437ns (1.587ns logic, 0.850ns route)
-                                                       (65.1% logic, 34.9% route)
-
---------------------------------------------------------------------------------
-
-Hold Paths: COMP "P2L_DATA<12>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKn"
-        HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[12].U/FDRSE0 (G22.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.295ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<12> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[12].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.875ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<12> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[12].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    G22.ICLK1            Tioickpd    (-Th)    -2.770   P2L_DATA<12>
-                                                       P2L_DATA<12>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[12].U/IBUF1
-                                                       P2L_DATA<12>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[12].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[12].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.661   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    G22.ICLK1            net (fanout=50)       0.980   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.875ns (1.873ns logic, 1.002ns route)
-                                                       (65.1% logic, 34.9% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[12].U/FDRSE1 (G22.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.297ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<12> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[12].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.873ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<12> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[12].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    G22.ICLK2            Tioickpd    (-Th)    -2.770   P2L_DATA<12>
-                                                       P2L_DATA<12>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[12].U/IBUF1
-                                                       P2L_DATA<12>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[12].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[12].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.739   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.922   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    G22.ICLK2            net (fanout=2809)     0.978   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.873ns (1.873ns logic, 1.000ns route)
-                                                       (65.2% logic, 34.8% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "P2L_DATA<13>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE 
-COMP "P2L_CLKp"         HIGH;
-
- 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors)
- Minimum allowable offset is   0.800ns.
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[13].U/FDRSE1 (L18.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.400ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<13> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[13].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.450ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<13> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[13].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    L18.ICLK2            Tiopickd              3.250   P2L_DATA<13>
-                                                       P2L_DATA<13>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[13].U/IBUF1
-                                                       P2L_DATA<13>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[13].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[13].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.470   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    L18.ICLK2            net (fanout=2809)     0.846   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.450ns (1.587ns logic, 0.863ns route)
-                                                       (64.8% logic, 35.2% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[13].U/FDRSE0 (L18.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.405ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<13> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[13].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.455ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<13> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[13].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    L18.ICLK1            Tiopickd              3.250   P2L_DATA<13>
-                                                       P2L_DATA<13>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[13].U/IBUF1
-                                                       P2L_DATA<13>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[13].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[13].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.733   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.738   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    L18.ICLK1            net (fanout=50)       0.850   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.455ns (1.588ns logic, 0.867ns route)
-                                                       (64.7% logic, 35.3% route)
-
---------------------------------------------------------------------------------
-
-Hold Paths: COMP "P2L_DATA<13>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKp"
-        HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[13].U/FDRSE0 (L18.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.275ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<13> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[13].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.895ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<13> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[13].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    L18.ICLK1            Tioickpd    (-Th)    -2.770   P2L_DATA<13>
-                                                       P2L_DATA<13>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[13].U/IBUF1
-                                                       P2L_DATA<13>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[13].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[13].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.739   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.922   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    L18.ICLK1            net (fanout=50)       1.000   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.895ns (1.873ns logic, 1.022ns route)
-                                                       (64.7% logic, 35.3% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[13].U/FDRSE1 (L18.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.280ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<13> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[13].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.890ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<13> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[13].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    L18.ICLK2            Tioickpd    (-Th)    -2.770   P2L_DATA<13>
-                                                       P2L_DATA<13>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[13].U/IBUF1
-                                                       P2L_DATA<13>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[13].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[13].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.661   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    L18.ICLK2            net (fanout=2809)     0.995   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.890ns (1.873ns logic, 1.017ns route)
-                                                       (64.8% logic, 35.2% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "P2L_DATA<13>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE 
-COMP "P2L_CLKn"         HIGH;
-
- 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors)
- Minimum allowable offset is   0.799ns.
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[13].U/FDRSE1 (L18.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.401ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<13> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[13].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.451ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<13> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[13].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    L18.ICLK2            Tiopickd              3.250   P2L_DATA<13>
-                                                       P2L_DATA<13>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[13].U/IBUF1
-                                                       P2L_DATA<13>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[13].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[13].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.733   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.738   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    L18.ICLK2            net (fanout=2809)     0.846   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.451ns (1.588ns logic, 0.863ns route)
-                                                       (64.8% logic, 35.2% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[13].U/FDRSE0 (L18.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.404ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<13> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[13].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.454ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<13> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[13].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    L18.ICLK1            Tiopickd              3.250   P2L_DATA<13>
-                                                       P2L_DATA<13>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[13].U/IBUF1
-                                                       P2L_DATA<13>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[13].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[13].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.470   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    L18.ICLK1            net (fanout=50)       0.850   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.454ns (1.587ns logic, 0.867ns route)
-                                                       (64.7% logic, 35.3% route)
-
---------------------------------------------------------------------------------
-
-Hold Paths: COMP "P2L_DATA<13>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKn"
-        HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[13].U/FDRSE0 (L18.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.275ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<13> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[13].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.895ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<13> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[13].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    L18.ICLK1            Tioickpd    (-Th)    -2.770   P2L_DATA<13>
-                                                       P2L_DATA<13>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[13].U/IBUF1
-                                                       P2L_DATA<13>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[13].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[13].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.661   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    L18.ICLK1            net (fanout=50)       1.000   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.895ns (1.873ns logic, 1.022ns route)
-                                                       (64.7% logic, 35.3% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[13].U/FDRSE1 (L18.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.280ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<13> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[13].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.890ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<13> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[13].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    L18.ICLK2            Tioickpd    (-Th)    -2.770   P2L_DATA<13>
-                                                       P2L_DATA<13>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[13].U/IBUF1
-                                                       P2L_DATA<13>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[13].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[13].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.739   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.922   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    L18.ICLK2            net (fanout=2809)     0.995   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.890ns (1.873ns logic, 1.017ns route)
-                                                       (64.8% logic, 35.2% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "P2L_DATA<14>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE 
-COMP "P2L_CLKp"         HIGH;
-
- 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors)
- Minimum allowable offset is   0.775ns.
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[14].U/FDRSE1 (M18.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.425ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<14> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[14].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.475ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<14> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[14].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    M18.ICLK2            Tiopickd              3.250   P2L_DATA<14>
-                                                       P2L_DATA<14>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[14].U/IBUF1
-                                                       P2L_DATA<14>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[14].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[14].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.470   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    M18.ICLK2            net (fanout=2809)     0.871   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.475ns (1.587ns logic, 0.888ns route)
-                                                       (64.1% logic, 35.9% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[14].U/FDRSE0 (M18.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.433ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<14> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[14].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.483ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<14> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[14].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    M18.ICLK1            Tiopickd              3.250   P2L_DATA<14>
-                                                       P2L_DATA<14>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[14].U/IBUF1
-                                                       P2L_DATA<14>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[14].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[14].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.733   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.738   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    M18.ICLK1            net (fanout=50)       0.878   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.483ns (1.588ns logic, 0.895ns route)
-                                                       (64.0% logic, 36.0% route)
-
---------------------------------------------------------------------------------
-
-Hold Paths: COMP "P2L_DATA<14>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKp"
-        HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[14].U/FDRSE0 (M18.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.242ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<14> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[14].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.928ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<14> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[14].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    M18.ICLK1            Tioickpd    (-Th)    -2.770   P2L_DATA<14>
-                                                       P2L_DATA<14>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[14].U/IBUF1
-                                                       P2L_DATA<14>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[14].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[14].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.739   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.922   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    M18.ICLK1            net (fanout=50)       1.033   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.928ns (1.873ns logic, 1.055ns route)
-                                                       (64.0% logic, 36.0% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[14].U/FDRSE1 (M18.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.250ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<14> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[14].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.920ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<14> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[14].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    M18.ICLK2            Tioickpd    (-Th)    -2.770   P2L_DATA<14>
-                                                       P2L_DATA<14>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[14].U/IBUF1
-                                                       P2L_DATA<14>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[14].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[14].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.661   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    M18.ICLK2            net (fanout=2809)     1.025   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.920ns (1.873ns logic, 1.047ns route)
-                                                       (64.1% logic, 35.9% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "P2L_DATA<14>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE 
-COMP "P2L_CLKn"         HIGH;
-
- 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors)
- Minimum allowable offset is   0.774ns.
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[14].U/FDRSE1 (M18.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.426ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<14> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[14].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.476ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<14> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[14].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    M18.ICLK2            Tiopickd              3.250   P2L_DATA<14>
-                                                       P2L_DATA<14>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[14].U/IBUF1
-                                                       P2L_DATA<14>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[14].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[14].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.733   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.738   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    M18.ICLK2            net (fanout=2809)     0.871   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.476ns (1.588ns logic, 0.888ns route)
-                                                       (64.1% logic, 35.9% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[14].U/FDRSE0 (M18.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.432ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<14> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[14].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.482ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<14> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[14].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    M18.ICLK1            Tiopickd              3.250   P2L_DATA<14>
-                                                       P2L_DATA<14>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[14].U/IBUF1
-                                                       P2L_DATA<14>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[14].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[14].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.470   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    M18.ICLK1            net (fanout=50)       0.878   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.482ns (1.587ns logic, 0.895ns route)
-                                                       (63.9% logic, 36.1% route)
-
---------------------------------------------------------------------------------
-
-Hold Paths: COMP "P2L_DATA<14>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKn"
-        HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[14].U/FDRSE0 (M18.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.242ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<14> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[14].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.928ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<14> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[14].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    M18.ICLK1            Tioickpd    (-Th)    -2.770   P2L_DATA<14>
-                                                       P2L_DATA<14>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[14].U/IBUF1
-                                                       P2L_DATA<14>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[14].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[14].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.661   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    M18.ICLK1            net (fanout=50)       1.033   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.928ns (1.873ns logic, 1.055ns route)
-                                                       (64.0% logic, 36.0% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[14].U/FDRSE1 (M18.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.250ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<14> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[14].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.920ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<14> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[14].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    M18.ICLK2            Tioickpd    (-Th)    -2.770   P2L_DATA<14>
-                                                       P2L_DATA<14>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[14].U/IBUF1
-                                                       P2L_DATA<14>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[14].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[14].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.739   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.922   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    M18.ICLK2            net (fanout=2809)     1.025   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.920ns (1.873ns logic, 1.047ns route)
-                                                       (64.1% logic, 35.9% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "P2L_DATA<15>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE 
-COMP "P2L_CLKp"         HIGH;
-
- 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors)
- Minimum allowable offset is   0.779ns.
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[15].U/FDRSE1 (K20.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.421ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<15> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[15].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.471ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<15> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[15].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    K20.ICLK2            Tiopickd              3.250   P2L_DATA<15>
-                                                       P2L_DATA<15>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[15].U/IBUF1
-                                                       P2L_DATA<15>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[15].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[15].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.470   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    K20.ICLK2            net (fanout=2809)     0.867   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.471ns (1.587ns logic, 0.884ns route)
-                                                       (64.2% logic, 35.8% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[15].U/FDRSE0 (K20.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.430ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<15> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[15].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.480ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<15> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[15].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    K20.ICLK1            Tiopickd              3.250   P2L_DATA<15>
-                                                       P2L_DATA<15>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[15].U/IBUF1
-                                                       P2L_DATA<15>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[15].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[15].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.733   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.738   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    K20.ICLK1            net (fanout=50)       0.875   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.480ns (1.588ns logic, 0.892ns route)
-                                                       (64.0% logic, 36.0% route)
-
---------------------------------------------------------------------------------
-
-Hold Paths: COMP "P2L_DATA<15>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKp"
-        HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[15].U/FDRSE0 (K20.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.246ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<15> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[15].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.924ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<15> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[15].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    K20.ICLK1            Tioickpd    (-Th)    -2.770   P2L_DATA<15>
-                                                       P2L_DATA<15>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[15].U/IBUF1
-                                                       P2L_DATA<15>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[15].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[15].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.739   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.922   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    K20.ICLK1            net (fanout=50)       1.029   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.924ns (1.873ns logic, 1.051ns route)
-                                                       (64.1% logic, 35.9% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[15].U/FDRSE1 (K20.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.254ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<15> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[15].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.916ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<15> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[15].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    K20.ICLK2            Tioickpd    (-Th)    -2.770   P2L_DATA<15>
-                                                       P2L_DATA<15>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[15].U/IBUF1
-                                                       P2L_DATA<15>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[15].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[15].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.661   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    K20.ICLK2            net (fanout=2809)     1.021   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.916ns (1.873ns logic, 1.043ns route)
-                                                       (64.2% logic, 35.8% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "P2L_DATA<15>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE 
-COMP "P2L_CLKn"         HIGH;
-
- 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors)
- Minimum allowable offset is   0.778ns.
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[15].U/FDRSE1 (K20.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.422ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<15> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[15].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.472ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<15> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[15].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    K20.ICLK2            Tiopickd              3.250   P2L_DATA<15>
-                                                       P2L_DATA<15>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[15].U/IBUF1
-                                                       P2L_DATA<15>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[15].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[15].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.733   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.738   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    K20.ICLK2            net (fanout=2809)     0.867   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.472ns (1.588ns logic, 0.884ns route)
-                                                       (64.2% logic, 35.8% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[15].U/FDRSE0 (K20.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.429ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<15> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[15].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.479ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<15> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[15].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    K20.ICLK1            Tiopickd              3.250   P2L_DATA<15>
-                                                       P2L_DATA<15>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[15].U/IBUF1
-                                                       P2L_DATA<15>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[15].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[15].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.470   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    K20.ICLK1            net (fanout=50)       0.875   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.479ns (1.587ns logic, 0.892ns route)
-                                                       (64.0% logic, 36.0% route)
-
---------------------------------------------------------------------------------
-
-Hold Paths: COMP "P2L_DATA<15>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKn"
-        HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[15].U/FDRSE0 (K20.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.246ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<15> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[15].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.924ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<15> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[15].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    K20.ICLK1            Tioickpd    (-Th)    -2.770   P2L_DATA<15>
-                                                       P2L_DATA<15>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[15].U/IBUF1
-                                                       P2L_DATA<15>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[15].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[15].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.661   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    K20.ICLK1            net (fanout=50)       1.029   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.924ns (1.873ns logic, 1.051ns route)
-                                                       (64.1% logic, 35.9% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[15].U/FDRSE1 (K20.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.254ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<15> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[15].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.916ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<15> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[15].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    K20.ICLK2            Tioickpd    (-Th)    -2.770   P2L_DATA<15>
-                                                       P2L_DATA<15>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[15].U/IBUF1
-                                                       P2L_DATA<15>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[15].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[15].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.739   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.922   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    K20.ICLK2            net (fanout=2809)     1.021   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.916ns (1.873ns logic, 1.043ns route)
-                                                       (64.2% logic, 35.8% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "P2L_DATA<1>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE 
-COMP "P2L_CLKp"         HIGH;
-
- 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors)
- Minimum allowable offset is   0.765ns.
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[1].U/FDRSE1 (J18.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.435ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<1> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[1].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.485ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<1> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[1].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    J18.ICLK2            Tiopickd              3.250   P2L_DATA<1>
-                                                       P2L_DATA<1>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[1].U/IBUF1
-                                                       P2L_DATA<1>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[1].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[1].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.470   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    J18.ICLK2            net (fanout=2809)     0.881   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.485ns (1.587ns logic, 0.898ns route)
-                                                       (63.9% logic, 36.1% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[1].U/FDRSE0 (J18.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.436ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<1> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[1].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.486ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<1> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[1].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    J18.ICLK1            Tiopickd              3.250   P2L_DATA<1>
-                                                       P2L_DATA<1>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[1].U/IBUF1
-                                                       P2L_DATA<1>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[1].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[1].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.733   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.738   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    J18.ICLK1            net (fanout=50)       0.881   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.486ns (1.588ns logic, 0.898ns route)
-                                                       (63.9% logic, 36.1% route)
-
---------------------------------------------------------------------------------
-
-Hold Paths: COMP "P2L_DATA<1>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKp"
-        HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[1].U/FDRSE0 (J18.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.238ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<1> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[1].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.932ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<1> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[1].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    J18.ICLK1            Tioickpd    (-Th)    -2.770   P2L_DATA<1>
-                                                       P2L_DATA<1>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[1].U/IBUF1
-                                                       P2L_DATA<1>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[1].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[1].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.739   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.922   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    J18.ICLK1            net (fanout=50)       1.037   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.932ns (1.873ns logic, 1.059ns route)
-                                                       (63.9% logic, 36.1% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[1].U/FDRSE1 (J18.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.238ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<1> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[1].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.932ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<1> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[1].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    J18.ICLK2            Tioickpd    (-Th)    -2.770   P2L_DATA<1>
-                                                       P2L_DATA<1>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[1].U/IBUF1
-                                                       P2L_DATA<1>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[1].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[1].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.661   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    J18.ICLK2            net (fanout=2809)     1.037   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.932ns (1.873ns logic, 1.059ns route)
-                                                       (63.9% logic, 36.1% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "P2L_DATA<1>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE 
-COMP "P2L_CLKn"         HIGH;
-
- 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors)
- Minimum allowable offset is   0.765ns.
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[1].U/FDRSE0 (J18.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.435ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<1> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[1].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.485ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<1> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[1].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    J18.ICLK1            Tiopickd              3.250   P2L_DATA<1>
-                                                       P2L_DATA<1>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[1].U/IBUF1
-                                                       P2L_DATA<1>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[1].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[1].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.470   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    J18.ICLK1            net (fanout=50)       0.881   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.485ns (1.587ns logic, 0.898ns route)
-                                                       (63.9% logic, 36.1% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[1].U/FDRSE1 (J18.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.436ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<1> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[1].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.486ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<1> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[1].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    J18.ICLK2            Tiopickd              3.250   P2L_DATA<1>
-                                                       P2L_DATA<1>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[1].U/IBUF1
-                                                       P2L_DATA<1>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[1].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[1].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.733   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.738   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    J18.ICLK2            net (fanout=2809)     0.881   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.486ns (1.588ns logic, 0.898ns route)
-                                                       (63.9% logic, 36.1% route)
-
---------------------------------------------------------------------------------
-
-Hold Paths: COMP "P2L_DATA<1>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKn"
-        HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[1].U/FDRSE0 (J18.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.238ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<1> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[1].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.932ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<1> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[1].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    J18.ICLK1            Tioickpd    (-Th)    -2.770   P2L_DATA<1>
-                                                       P2L_DATA<1>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[1].U/IBUF1
-                                                       P2L_DATA<1>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[1].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[1].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.661   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    J18.ICLK1            net (fanout=50)       1.037   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.932ns (1.873ns logic, 1.059ns route)
-                                                       (63.9% logic, 36.1% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[1].U/FDRSE1 (J18.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.238ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<1> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[1].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.932ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<1> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[1].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    J18.ICLK2            Tioickpd    (-Th)    -2.770   P2L_DATA<1>
-                                                       P2L_DATA<1>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[1].U/IBUF1
-                                                       P2L_DATA<1>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[1].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[1].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.739   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.922   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    J18.ICLK2            net (fanout=2809)     1.037   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.932ns (1.873ns logic, 1.059ns route)
-                                                       (63.9% logic, 36.1% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "P2L_DATA<2>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE 
-COMP "P2L_CLKp"         HIGH;
-
- 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors)
- Minimum allowable offset is   0.761ns.
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[2].U/FDRSE1 (G19.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.439ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<2> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[2].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.489ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<2> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[2].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    G19.ICLK2            Tiopickd              3.250   P2L_DATA<2>
-                                                       P2L_DATA<2>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[2].U/IBUF1
-                                                       P2L_DATA<2>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[2].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[2].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.470   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    G19.ICLK2            net (fanout=2809)     0.885   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.489ns (1.587ns logic, 0.902ns route)
-                                                       (63.8% logic, 36.2% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[2].U/FDRSE0 (G19.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.440ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<2> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[2].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.490ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<2> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[2].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    G19.ICLK1            Tiopickd              3.250   P2L_DATA<2>
-                                                       P2L_DATA<2>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[2].U/IBUF1
-                                                       P2L_DATA<2>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[2].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[2].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.733   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.738   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    G19.ICLK1            net (fanout=50)       0.885   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.490ns (1.588ns logic, 0.902ns route)
-                                                       (63.8% logic, 36.2% route)
-
---------------------------------------------------------------------------------
-
-Hold Paths: COMP "P2L_DATA<2>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKp"
-        HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[2].U/FDRSE0 (G19.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.234ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<2> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[2].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.936ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<2> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[2].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    G19.ICLK1            Tioickpd    (-Th)    -2.770   P2L_DATA<2>
-                                                       P2L_DATA<2>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[2].U/IBUF1
-                                                       P2L_DATA<2>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[2].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[2].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.739   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.922   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    G19.ICLK1            net (fanout=50)       1.041   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.936ns (1.873ns logic, 1.063ns route)
-                                                       (63.8% logic, 36.2% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[2].U/FDRSE1 (G19.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.234ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<2> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[2].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.936ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<2> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[2].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    G19.ICLK2            Tioickpd    (-Th)    -2.770   P2L_DATA<2>
-                                                       P2L_DATA<2>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[2].U/IBUF1
-                                                       P2L_DATA<2>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[2].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[2].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.661   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    G19.ICLK2            net (fanout=2809)     1.041   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.936ns (1.873ns logic, 1.063ns route)
-                                                       (63.8% logic, 36.2% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "P2L_DATA<2>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE 
-COMP "P2L_CLKn"         HIGH;
-
- 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors)
- Minimum allowable offset is   0.761ns.
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[2].U/FDRSE0 (G19.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.439ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<2> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[2].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.489ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<2> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[2].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    G19.ICLK1            Tiopickd              3.250   P2L_DATA<2>
-                                                       P2L_DATA<2>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[2].U/IBUF1
-                                                       P2L_DATA<2>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[2].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[2].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.470   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    G19.ICLK1            net (fanout=50)       0.885   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.489ns (1.587ns logic, 0.902ns route)
-                                                       (63.8% logic, 36.2% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[2].U/FDRSE1 (G19.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.440ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<2> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[2].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.490ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<2> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[2].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    G19.ICLK2            Tiopickd              3.250   P2L_DATA<2>
-                                                       P2L_DATA<2>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[2].U/IBUF1
-                                                       P2L_DATA<2>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[2].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[2].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.733   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.738   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    G19.ICLK2            net (fanout=2809)     0.885   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.490ns (1.588ns logic, 0.902ns route)
-                                                       (63.8% logic, 36.2% route)
-
---------------------------------------------------------------------------------
-
-Hold Paths: COMP "P2L_DATA<2>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKn"
-        HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[2].U/FDRSE0 (G19.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.234ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<2> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[2].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.936ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<2> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[2].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    G19.ICLK1            Tioickpd    (-Th)    -2.770   P2L_DATA<2>
-                                                       P2L_DATA<2>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[2].U/IBUF1
-                                                       P2L_DATA<2>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[2].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[2].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.661   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    G19.ICLK1            net (fanout=50)       1.041   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.936ns (1.873ns logic, 1.063ns route)
-                                                       (63.8% logic, 36.2% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[2].U/FDRSE1 (G19.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.234ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<2> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[2].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.936ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<2> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[2].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    G19.ICLK2            Tioickpd    (-Th)    -2.770   P2L_DATA<2>
-                                                       P2L_DATA<2>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[2].U/IBUF1
-                                                       P2L_DATA<2>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[2].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[2].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.739   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.922   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    G19.ICLK2            net (fanout=2809)     1.041   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.936ns (1.873ns logic, 1.063ns route)
-                                                       (63.8% logic, 36.2% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "P2L_DATA<3>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE 
-COMP "P2L_CLKp"         HIGH;
-
- 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors)
- Minimum allowable offset is   0.817ns.
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[3].U/FDRSE1 (K15.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.383ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<3> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[3].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.433ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<3> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[3].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    K15.ICLK2            Tiopickd              3.250   P2L_DATA<3>
-                                                       P2L_DATA<3>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[3].U/IBUF1
-                                                       P2L_DATA<3>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[3].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[3].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.470   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    K15.ICLK2            net (fanout=2809)     0.829   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.433ns (1.587ns logic, 0.846ns route)
-                                                       (65.2% logic, 34.8% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[3].U/FDRSE0 (K15.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.384ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<3> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[3].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.434ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<3> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[3].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    K15.ICLK1            Tiopickd              3.250   P2L_DATA<3>
-                                                       P2L_DATA<3>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[3].U/IBUF1
-                                                       P2L_DATA<3>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[3].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[3].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.733   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.738   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    K15.ICLK1            net (fanout=50)       0.829   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.434ns (1.588ns logic, 0.846ns route)
-                                                       (65.2% logic, 34.8% route)
-
---------------------------------------------------------------------------------
-
-Hold Paths: COMP "P2L_DATA<3>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKp"
-        HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[3].U/FDRSE0 (K15.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.299ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<3> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[3].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.871ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<3> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[3].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    K15.ICLK1            Tioickpd    (-Th)    -2.770   P2L_DATA<3>
-                                                       P2L_DATA<3>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[3].U/IBUF1
-                                                       P2L_DATA<3>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[3].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[3].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.739   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.922   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    K15.ICLK1            net (fanout=50)       0.976   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.871ns (1.873ns logic, 0.998ns route)
-                                                       (65.2% logic, 34.8% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[3].U/FDRSE1 (K15.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.299ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<3> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[3].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.871ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<3> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[3].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    K15.ICLK2            Tioickpd    (-Th)    -2.770   P2L_DATA<3>
-                                                       P2L_DATA<3>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[3].U/IBUF1
-                                                       P2L_DATA<3>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[3].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[3].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.661   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    K15.ICLK2            net (fanout=2809)     0.976   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.871ns (1.873ns logic, 0.998ns route)
-                                                       (65.2% logic, 34.8% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "P2L_DATA<3>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE 
-COMP "P2L_CLKn"         HIGH;
-
- 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors)
- Minimum allowable offset is   0.817ns.
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[3].U/FDRSE0 (K15.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.383ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<3> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[3].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.433ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<3> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[3].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    K15.ICLK1            Tiopickd              3.250   P2L_DATA<3>
-                                                       P2L_DATA<3>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[3].U/IBUF1
-                                                       P2L_DATA<3>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[3].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[3].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.470   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    K15.ICLK1            net (fanout=50)       0.829   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.433ns (1.587ns logic, 0.846ns route)
-                                                       (65.2% logic, 34.8% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[3].U/FDRSE1 (K15.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.384ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<3> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[3].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.434ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<3> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[3].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    K15.ICLK2            Tiopickd              3.250   P2L_DATA<3>
-                                                       P2L_DATA<3>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[3].U/IBUF1
-                                                       P2L_DATA<3>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[3].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[3].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.733   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.738   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    K15.ICLK2            net (fanout=2809)     0.829   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.434ns (1.588ns logic, 0.846ns route)
-                                                       (65.2% logic, 34.8% route)
-
---------------------------------------------------------------------------------
-
-Hold Paths: COMP "P2L_DATA<3>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKn"
-        HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[3].U/FDRSE0 (K15.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.299ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<3> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[3].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.871ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<3> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[3].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    K15.ICLK1            Tioickpd    (-Th)    -2.770   P2L_DATA<3>
-                                                       P2L_DATA<3>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[3].U/IBUF1
-                                                       P2L_DATA<3>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[3].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[3].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.661   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    K15.ICLK1            net (fanout=50)       0.976   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.871ns (1.873ns logic, 0.998ns route)
-                                                       (65.2% logic, 34.8% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[3].U/FDRSE1 (K15.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.299ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<3> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[3].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.871ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<3> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[3].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    K15.ICLK2            Tioickpd    (-Th)    -2.770   P2L_DATA<3>
-                                                       P2L_DATA<3>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[3].U/IBUF1
-                                                       P2L_DATA<3>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[3].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[3].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.739   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.922   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    K15.ICLK2            net (fanout=2809)     0.976   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.871ns (1.873ns logic, 0.998ns route)
-                                                       (65.2% logic, 34.8% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "P2L_DATA<4>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE 
-COMP "P2L_CLKp"         HIGH;
-
- 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors)
- Minimum allowable offset is   0.777ns.
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[4].U/FDRSE1 (H17.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.423ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<4> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[4].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.473ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<4> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[4].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    H17.ICLK2            Tiopickd              3.250   P2L_DATA<4>
-                                                       P2L_DATA<4>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[4].U/IBUF1
-                                                       P2L_DATA<4>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[4].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[4].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.470   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    H17.ICLK2            net (fanout=2809)     0.869   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.473ns (1.587ns logic, 0.886ns route)
-                                                       (64.2% logic, 35.8% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[4].U/FDRSE0 (H17.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.424ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<4> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[4].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.474ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<4> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[4].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    H17.ICLK1            Tiopickd              3.250   P2L_DATA<4>
-                                                       P2L_DATA<4>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[4].U/IBUF1
-                                                       P2L_DATA<4>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[4].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[4].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.733   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.738   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    H17.ICLK1            net (fanout=50)       0.869   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.474ns (1.588ns logic, 0.886ns route)
-                                                       (64.2% logic, 35.8% route)
-
---------------------------------------------------------------------------------
-
-Hold Paths: COMP "P2L_DATA<4>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKp"
-        HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[4].U/FDRSE0 (H17.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.252ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<4> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[4].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.918ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<4> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[4].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    H17.ICLK1            Tioickpd    (-Th)    -2.770   P2L_DATA<4>
-                                                       P2L_DATA<4>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[4].U/IBUF1
-                                                       P2L_DATA<4>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[4].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[4].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.739   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.922   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    H17.ICLK1            net (fanout=50)       1.023   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.918ns (1.873ns logic, 1.045ns route)
-                                                       (64.2% logic, 35.8% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[4].U/FDRSE1 (H17.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.252ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<4> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[4].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.918ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<4> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[4].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    H17.ICLK2            Tioickpd    (-Th)    -2.770   P2L_DATA<4>
-                                                       P2L_DATA<4>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[4].U/IBUF1
-                                                       P2L_DATA<4>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[4].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[4].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.661   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    H17.ICLK2            net (fanout=2809)     1.023   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.918ns (1.873ns logic, 1.045ns route)
-                                                       (64.2% logic, 35.8% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "P2L_DATA<4>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE 
-COMP "P2L_CLKn"         HIGH;
-
- 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors)
- Minimum allowable offset is   0.777ns.
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[4].U/FDRSE0 (H17.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.423ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<4> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[4].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.473ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<4> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[4].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    H17.ICLK1            Tiopickd              3.250   P2L_DATA<4>
-                                                       P2L_DATA<4>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[4].U/IBUF1
-                                                       P2L_DATA<4>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[4].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[4].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.470   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    H17.ICLK1            net (fanout=50)       0.869   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.473ns (1.587ns logic, 0.886ns route)
-                                                       (64.2% logic, 35.8% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[4].U/FDRSE1 (H17.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.424ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<4> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[4].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.474ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<4> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[4].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    H17.ICLK2            Tiopickd              3.250   P2L_DATA<4>
-                                                       P2L_DATA<4>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[4].U/IBUF1
-                                                       P2L_DATA<4>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[4].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[4].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.733   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.738   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    H17.ICLK2            net (fanout=2809)     0.869   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.474ns (1.588ns logic, 0.886ns route)
-                                                       (64.2% logic, 35.8% route)
-
---------------------------------------------------------------------------------
-
-Hold Paths: COMP "P2L_DATA<4>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKn"
-        HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[4].U/FDRSE0 (H17.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.252ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<4> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[4].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.918ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<4> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[4].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    H17.ICLK1            Tioickpd    (-Th)    -2.770   P2L_DATA<4>
-                                                       P2L_DATA<4>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[4].U/IBUF1
-                                                       P2L_DATA<4>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[4].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[4].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.661   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    H17.ICLK1            net (fanout=50)       1.023   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.918ns (1.873ns logic, 1.045ns route)
-                                                       (64.2% logic, 35.8% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[4].U/FDRSE1 (H17.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.252ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<4> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[4].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.918ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<4> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[4].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    H17.ICLK2            Tioickpd    (-Th)    -2.770   P2L_DATA<4>
-                                                       P2L_DATA<4>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[4].U/IBUF1
-                                                       P2L_DATA<4>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[4].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[4].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.739   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.922   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    H17.ICLK2            net (fanout=2809)     1.023   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.918ns (1.873ns logic, 1.045ns route)
-                                                       (64.2% logic, 35.8% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "P2L_DATA<5>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE 
-COMP "P2L_CLKp"         HIGH;
-
- 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors)
- Minimum allowable offset is   0.761ns.
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[5].U/FDRSE1 (G20.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.439ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<5> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[5].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.489ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<5> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[5].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    G20.ICLK2            Tiopickd              3.250   P2L_DATA<5>
-                                                       P2L_DATA<5>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[5].U/IBUF1
-                                                       P2L_DATA<5>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[5].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[5].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.470   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    G20.ICLK2            net (fanout=2809)     0.885   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.489ns (1.587ns logic, 0.902ns route)
-                                                       (63.8% logic, 36.2% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[5].U/FDRSE0 (G20.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.440ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<5> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[5].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.490ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<5> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[5].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    G20.ICLK1            Tiopickd              3.250   P2L_DATA<5>
-                                                       P2L_DATA<5>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[5].U/IBUF1
-                                                       P2L_DATA<5>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[5].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[5].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.733   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.738   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    G20.ICLK1            net (fanout=50)       0.885   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.490ns (1.588ns logic, 0.902ns route)
-                                                       (63.8% logic, 36.2% route)
-
---------------------------------------------------------------------------------
-
-Hold Paths: COMP "P2L_DATA<5>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKp"
-        HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[5].U/FDRSE0 (G20.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.234ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<5> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[5].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.936ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<5> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[5].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    G20.ICLK1            Tioickpd    (-Th)    -2.770   P2L_DATA<5>
-                                                       P2L_DATA<5>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[5].U/IBUF1
-                                                       P2L_DATA<5>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[5].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[5].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.739   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.922   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    G20.ICLK1            net (fanout=50)       1.041   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.936ns (1.873ns logic, 1.063ns route)
-                                                       (63.8% logic, 36.2% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[5].U/FDRSE1 (G20.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.234ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<5> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[5].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.936ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<5> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[5].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    G20.ICLK2            Tioickpd    (-Th)    -2.770   P2L_DATA<5>
-                                                       P2L_DATA<5>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[5].U/IBUF1
-                                                       P2L_DATA<5>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[5].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[5].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.661   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    G20.ICLK2            net (fanout=2809)     1.041   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.936ns (1.873ns logic, 1.063ns route)
-                                                       (63.8% logic, 36.2% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "P2L_DATA<5>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE 
-COMP "P2L_CLKn"         HIGH;
-
- 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors)
- Minimum allowable offset is   0.761ns.
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[5].U/FDRSE0 (G20.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.439ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<5> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[5].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.489ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<5> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[5].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    G20.ICLK1            Tiopickd              3.250   P2L_DATA<5>
-                                                       P2L_DATA<5>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[5].U/IBUF1
-                                                       P2L_DATA<5>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[5].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[5].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.470   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    G20.ICLK1            net (fanout=50)       0.885   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.489ns (1.587ns logic, 0.902ns route)
-                                                       (63.8% logic, 36.2% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[5].U/FDRSE1 (G20.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.440ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<5> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[5].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.490ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<5> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[5].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    G20.ICLK2            Tiopickd              3.250   P2L_DATA<5>
-                                                       P2L_DATA<5>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[5].U/IBUF1
-                                                       P2L_DATA<5>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[5].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[5].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.733   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.738   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    G20.ICLK2            net (fanout=2809)     0.885   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.490ns (1.588ns logic, 0.902ns route)
-                                                       (63.8% logic, 36.2% route)
-
---------------------------------------------------------------------------------
-
-Hold Paths: COMP "P2L_DATA<5>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKn"
-        HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[5].U/FDRSE0 (G20.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.234ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<5> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[5].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.936ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<5> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[5].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    G20.ICLK1            Tioickpd    (-Th)    -2.770   P2L_DATA<5>
-                                                       P2L_DATA<5>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[5].U/IBUF1
-                                                       P2L_DATA<5>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[5].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[5].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.661   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    G20.ICLK1            net (fanout=50)       1.041   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.936ns (1.873ns logic, 1.063ns route)
-                                                       (63.8% logic, 36.2% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[5].U/FDRSE1 (G20.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.234ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<5> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[5].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.936ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<5> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[5].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    G20.ICLK2            Tioickpd    (-Th)    -2.770   P2L_DATA<5>
-                                                       P2L_DATA<5>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[5].U/IBUF1
-                                                       P2L_DATA<5>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[5].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[5].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.739   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.922   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    G20.ICLK2            net (fanout=2809)     1.041   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.936ns (1.873ns logic, 1.063ns route)
-                                                       (63.8% logic, 36.2% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "P2L_DATA<6>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE 
-COMP "P2L_CLKp"         HIGH;
-
- 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors)
- Minimum allowable offset is   0.818ns.
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[6].U/FDRSE1 (F22.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.382ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<6> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[6].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.432ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<6> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[6].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    F22.ICLK2            Tiopickd              3.250   P2L_DATA<6>
-                                                       P2L_DATA<6>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[6].U/IBUF1
-                                                       P2L_DATA<6>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[6].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[6].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.470   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    F22.ICLK2            net (fanout=2809)     0.828   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.432ns (1.587ns logic, 0.845ns route)
-                                                       (65.3% logic, 34.7% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[6].U/FDRSE0 (F22.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.383ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<6> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[6].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.433ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<6> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[6].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    F22.ICLK1            Tiopickd              3.250   P2L_DATA<6>
-                                                       P2L_DATA<6>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[6].U/IBUF1
-                                                       P2L_DATA<6>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[6].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[6].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.733   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.738   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    F22.ICLK1            net (fanout=50)       0.828   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.433ns (1.588ns logic, 0.845ns route)
-                                                       (65.3% logic, 34.7% route)
-
---------------------------------------------------------------------------------
-
-Hold Paths: COMP "P2L_DATA<6>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKp"
-        HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[6].U/FDRSE0 (F22.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.301ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<6> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[6].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.869ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<6> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[6].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    F22.ICLK1            Tioickpd    (-Th)    -2.770   P2L_DATA<6>
-                                                       P2L_DATA<6>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[6].U/IBUF1
-                                                       P2L_DATA<6>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[6].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[6].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.739   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.922   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    F22.ICLK1            net (fanout=50)       0.974   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.869ns (1.873ns logic, 0.996ns route)
-                                                       (65.3% logic, 34.7% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[6].U/FDRSE1 (F22.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.301ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<6> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[6].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.869ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<6> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[6].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    F22.ICLK2            Tioickpd    (-Th)    -2.770   P2L_DATA<6>
-                                                       P2L_DATA<6>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[6].U/IBUF1
-                                                       P2L_DATA<6>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[6].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[6].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.661   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    F22.ICLK2            net (fanout=2809)     0.974   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.869ns (1.873ns logic, 0.996ns route)
-                                                       (65.3% logic, 34.7% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "P2L_DATA<6>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE 
-COMP "P2L_CLKn"         HIGH;
-
- 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors)
- Minimum allowable offset is   0.818ns.
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[6].U/FDRSE0 (F22.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.382ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<6> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[6].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.432ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<6> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[6].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    F22.ICLK1            Tiopickd              3.250   P2L_DATA<6>
-                                                       P2L_DATA<6>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[6].U/IBUF1
-                                                       P2L_DATA<6>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[6].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[6].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.470   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    F22.ICLK1            net (fanout=50)       0.828   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.432ns (1.587ns logic, 0.845ns route)
-                                                       (65.3% logic, 34.7% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[6].U/FDRSE1 (F22.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.383ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<6> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[6].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.433ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<6> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[6].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    F22.ICLK2            Tiopickd              3.250   P2L_DATA<6>
-                                                       P2L_DATA<6>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[6].U/IBUF1
-                                                       P2L_DATA<6>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[6].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[6].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.733   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.738   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    F22.ICLK2            net (fanout=2809)     0.828   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.433ns (1.588ns logic, 0.845ns route)
-                                                       (65.3% logic, 34.7% route)
-
---------------------------------------------------------------------------------
-
-Hold Paths: COMP "P2L_DATA<6>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKn"
-        HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[6].U/FDRSE0 (F22.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.301ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<6> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[6].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.869ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<6> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[6].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    F22.ICLK1            Tioickpd    (-Th)    -2.770   P2L_DATA<6>
-                                                       P2L_DATA<6>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[6].U/IBUF1
-                                                       P2L_DATA<6>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[6].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[6].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.661   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    F22.ICLK1            net (fanout=50)       0.974   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.869ns (1.873ns logic, 0.996ns route)
-                                                       (65.3% logic, 34.7% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[6].U/FDRSE1 (F22.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.301ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<6> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[6].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.869ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<6> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[6].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    F22.ICLK2            Tioickpd    (-Th)    -2.770   P2L_DATA<6>
-                                                       P2L_DATA<6>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[6].U/IBUF1
-                                                       P2L_DATA<6>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[6].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[6].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.739   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.922   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    F22.ICLK2            net (fanout=2809)     0.974   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.869ns (1.873ns logic, 0.996ns route)
-                                                       (65.3% logic, 34.7% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "P2L_DATA<7>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE 
-COMP "P2L_CLKp"         HIGH;
-
- 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors)
- Minimum allowable offset is   0.765ns.
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[7].U/FDRSE1 (H19.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.435ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<7> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[7].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.485ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<7> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[7].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    H19.ICLK2            Tiopickd              3.250   P2L_DATA<7>
-                                                       P2L_DATA<7>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[7].U/IBUF1
-                                                       P2L_DATA<7>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[7].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[7].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.470   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    H19.ICLK2            net (fanout=2809)     0.881   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.485ns (1.587ns logic, 0.898ns route)
-                                                       (63.9% logic, 36.1% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[7].U/FDRSE0 (H19.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.436ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<7> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[7].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.486ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<7> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[7].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    H19.ICLK1            Tiopickd              3.250   P2L_DATA<7>
-                                                       P2L_DATA<7>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[7].U/IBUF1
-                                                       P2L_DATA<7>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[7].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[7].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.733   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.738   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    H19.ICLK1            net (fanout=50)       0.881   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.486ns (1.588ns logic, 0.898ns route)
-                                                       (63.9% logic, 36.1% route)
-
---------------------------------------------------------------------------------
-
-Hold Paths: COMP "P2L_DATA<7>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKp"
-        HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[7].U/FDRSE0 (H19.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.238ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<7> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[7].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.932ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<7> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[7].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    H19.ICLK1            Tioickpd    (-Th)    -2.770   P2L_DATA<7>
-                                                       P2L_DATA<7>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[7].U/IBUF1
-                                                       P2L_DATA<7>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[7].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[7].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.739   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.922   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    H19.ICLK1            net (fanout=50)       1.037   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.932ns (1.873ns logic, 1.059ns route)
-                                                       (63.9% logic, 36.1% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[7].U/FDRSE1 (H19.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.238ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<7> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[7].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.932ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<7> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[7].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    H19.ICLK2            Tioickpd    (-Th)    -2.770   P2L_DATA<7>
-                                                       P2L_DATA<7>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[7].U/IBUF1
-                                                       P2L_DATA<7>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[7].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[7].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.661   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    H19.ICLK2            net (fanout=2809)     1.037   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.932ns (1.873ns logic, 1.059ns route)
-                                                       (63.9% logic, 36.1% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "P2L_DATA<7>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE 
-COMP "P2L_CLKn"         HIGH;
-
- 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors)
- Minimum allowable offset is   0.765ns.
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[7].U/FDRSE0 (H19.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.435ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<7> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[7].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.485ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<7> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[7].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    H19.ICLK1            Tiopickd              3.250   P2L_DATA<7>
-                                                       P2L_DATA<7>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[7].U/IBUF1
-                                                       P2L_DATA<7>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[7].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[7].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.470   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    H19.ICLK1            net (fanout=50)       0.881   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.485ns (1.587ns logic, 0.898ns route)
-                                                       (63.9% logic, 36.1% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[7].U/FDRSE1 (H19.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.436ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<7> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[7].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.486ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<7> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[7].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    H19.ICLK2            Tiopickd              3.250   P2L_DATA<7>
-                                                       P2L_DATA<7>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[7].U/IBUF1
-                                                       P2L_DATA<7>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[7].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[7].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.733   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.738   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    H19.ICLK2            net (fanout=2809)     0.881   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.486ns (1.588ns logic, 0.898ns route)
-                                                       (63.9% logic, 36.1% route)
-
---------------------------------------------------------------------------------
-
-Hold Paths: COMP "P2L_DATA<7>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKn"
-        HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[7].U/FDRSE0 (H19.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.238ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<7> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[7].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.932ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<7> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[7].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    H19.ICLK1            Tioickpd    (-Th)    -2.770   P2L_DATA<7>
-                                                       P2L_DATA<7>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[7].U/IBUF1
-                                                       P2L_DATA<7>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[7].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[7].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.661   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    H19.ICLK1            net (fanout=50)       1.037   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.932ns (1.873ns logic, 1.059ns route)
-                                                       (63.9% logic, 36.1% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[7].U/FDRSE1 (H19.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.238ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<7> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[7].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.932ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<7> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[7].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    H19.ICLK2            Tioickpd    (-Th)    -2.770   P2L_DATA<7>
-                                                       P2L_DATA<7>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[7].U/IBUF1
-                                                       P2L_DATA<7>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[7].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[7].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.739   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.922   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    H19.ICLK2            net (fanout=2809)     1.037   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.932ns (1.873ns logic, 1.059ns route)
-                                                       (63.9% logic, 36.1% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "P2L_DATA<8>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE 
-COMP "P2L_CLKp"         HIGH;
-
- 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors)
- Minimum allowable offset is   0.785ns.
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[8].U/FDRSE1 (K22.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.415ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<8> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[8].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.465ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<8> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[8].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    K22.ICLK2            Tiopickd              3.250   P2L_DATA<8>
-                                                       P2L_DATA<8>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[8].U/IBUF1
-                                                       P2L_DATA<8>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[8].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[8].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.470   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    K22.ICLK2            net (fanout=2809)     0.861   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.465ns (1.587ns logic, 0.878ns route)
-                                                       (64.4% logic, 35.6% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[8].U/FDRSE0 (K22.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.424ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<8> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[8].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.474ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<8> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[8].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    K22.ICLK1            Tiopickd              3.250   P2L_DATA<8>
-                                                       P2L_DATA<8>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[8].U/IBUF1
-                                                       P2L_DATA<8>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[8].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[8].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.733   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.738   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    K22.ICLK1            net (fanout=50)       0.869   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.474ns (1.588ns logic, 0.886ns route)
-                                                       (64.2% logic, 35.8% route)
-
---------------------------------------------------------------------------------
-
-Hold Paths: COMP "P2L_DATA<8>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKp"
-        HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[8].U/FDRSE0 (K22.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.253ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<8> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[8].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.917ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<8> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[8].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    K22.ICLK1            Tioickpd    (-Th)    -2.770   P2L_DATA<8>
-                                                       P2L_DATA<8>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[8].U/IBUF1
-                                                       P2L_DATA<8>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[8].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[8].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.739   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.922   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    K22.ICLK1            net (fanout=50)       1.022   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.917ns (1.873ns logic, 1.044ns route)
-                                                       (64.2% logic, 35.8% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[8].U/FDRSE1 (K22.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.261ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<8> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[8].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.909ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<8> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[8].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    K22.ICLK2            Tioickpd    (-Th)    -2.770   P2L_DATA<8>
-                                                       P2L_DATA<8>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[8].U/IBUF1
-                                                       P2L_DATA<8>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[8].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[8].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.661   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    K22.ICLK2            net (fanout=2809)     1.014   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.909ns (1.873ns logic, 1.036ns route)
-                                                       (64.4% logic, 35.6% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "P2L_DATA<8>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE 
-COMP "P2L_CLKn"         HIGH;
-
- 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors)
- Minimum allowable offset is   0.784ns.
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[8].U/FDRSE1 (K22.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.416ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<8> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[8].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.466ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<8> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[8].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    K22.ICLK2            Tiopickd              3.250   P2L_DATA<8>
-                                                       P2L_DATA<8>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[8].U/IBUF1
-                                                       P2L_DATA<8>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[8].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[8].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.733   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.738   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    K22.ICLK2            net (fanout=2809)     0.861   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.466ns (1.588ns logic, 0.878ns route)
-                                                       (64.4% logic, 35.6% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[8].U/FDRSE0 (K22.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.423ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<8> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[8].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.473ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<8> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[8].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    K22.ICLK1            Tiopickd              3.250   P2L_DATA<8>
-                                                       P2L_DATA<8>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[8].U/IBUF1
-                                                       P2L_DATA<8>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[8].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[8].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.470   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    K22.ICLK1            net (fanout=50)       0.869   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.473ns (1.587ns logic, 0.886ns route)
-                                                       (64.2% logic, 35.8% route)
-
---------------------------------------------------------------------------------
-
-Hold Paths: COMP "P2L_DATA<8>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKn"
-        HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[8].U/FDRSE0 (K22.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.253ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<8> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[8].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.917ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<8> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[8].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    K22.ICLK1            Tioickpd    (-Th)    -2.770   P2L_DATA<8>
-                                                       P2L_DATA<8>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[8].U/IBUF1
-                                                       P2L_DATA<8>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[8].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[8].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.661   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    K22.ICLK1            net (fanout=50)       1.022   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.917ns (1.873ns logic, 1.044ns route)
-                                                       (64.2% logic, 35.8% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[8].U/FDRSE1 (K22.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.261ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<8> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[8].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.909ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<8> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[8].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    K22.ICLK2            Tioickpd    (-Th)    -2.770   P2L_DATA<8>
-                                                       P2L_DATA<8>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[8].U/IBUF1
-                                                       P2L_DATA<8>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[8].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[8].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.739   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.922   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    K22.ICLK2            net (fanout=2809)     1.014   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.909ns (1.873ns logic, 1.036ns route)
-                                                       (64.4% logic, 35.6% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "P2L_DATA<9>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE 
-COMP "P2L_CLKp"         HIGH;
-
- 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors)
- Minimum allowable offset is   0.824ns.
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[9].U/FDRSE1 (K17.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.376ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<9> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[9].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.426ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<9> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[9].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    K17.ICLK2            Tiopickd              3.250   P2L_DATA<9>
-                                                       P2L_DATA<9>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[9].U/IBUF1
-                                                       P2L_DATA<9>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[9].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[9].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.470   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    K17.ICLK2            net (fanout=2809)     0.822   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.426ns (1.587ns logic, 0.839ns route)
-                                                       (65.4% logic, 34.6% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[9].U/FDRSE0 (K17.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.377ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<9> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[9].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.427ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<9> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[9].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    K17.ICLK1            Tiopickd              3.250   P2L_DATA<9>
-                                                       P2L_DATA<9>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[9].U/IBUF1
-                                                       P2L_DATA<9>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[9].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[9].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.733   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.738   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    K17.ICLK1            net (fanout=50)       0.822   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.427ns (1.588ns logic, 0.839ns route)
-                                                       (65.4% logic, 34.6% route)
-
---------------------------------------------------------------------------------
-
-Hold Paths: COMP "P2L_DATA<9>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKp"
-        HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[9].U/FDRSE0 (K17.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.308ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<9> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[9].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.862ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<9> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[9].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    K17.ICLK1            Tioickpd    (-Th)    -2.770   P2L_DATA<9>
-                                                       P2L_DATA<9>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[9].U/IBUF1
-                                                       P2L_DATA<9>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[9].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[9].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.PADOUT           Tiopp                 0.739   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLKn_ibuf/SLAVEBUF.DIFFIN
-    E12.I                Tdiffin               0.922   P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    K17.ICLK1            net (fanout=50)       0.967   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.862ns (1.873ns logic, 0.989ns route)
-                                                       (65.4% logic, 34.6% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[9].U/FDRSE1 (K17.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.308ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<9> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[9].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.862ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<9> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[9].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    K17.ICLK2            Tioickpd    (-Th)    -2.770   P2L_DATA<9>
-                                                       P2L_DATA<9>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[9].U/IBUF1
-                                                       P2L_DATA<9>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[9].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[9].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.661   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    K17.ICLK2            net (fanout=2809)     0.967   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.862ns (1.873ns logic, 0.989ns route)
-                                                       (65.4% logic, 34.6% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "P2L_DATA<9>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE 
-COMP "P2L_CLKn"         HIGH;
-
- 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors)
- Minimum allowable offset is   0.824ns.
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[9].U/FDRSE0 (K17.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.376ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<9> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[9].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.426ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<9> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[9].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    K17.ICLK1            Tiopickd              3.250   P2L_DATA<9>
-                                                       P2L_DATA<9>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[9].U/IBUF1
-                                                       P2L_DATA<9>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[9].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[9].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.470   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.117   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    K17.ICLK1            net (fanout=50)       0.822   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.426ns (1.587ns logic, 0.839ns route)
-                                                       (65.4% logic, 34.6% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[9].U/FDRSE1 (K17.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.377ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DATA<9> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[9].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      3.250ns (Levels of Logic = 0)
-  Clock Path Delay:     2.427ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DATA<9> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[9].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    K17.ICLK2            Tiopickd              3.250   P2L_DATA<9>
-                                                       P2L_DATA<9>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[9].U/IBUF1
-                                                       P2L_DATA<9>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[9].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      3.250ns (3.250ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[9].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.733   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.738   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    K17.ICLK2            net (fanout=2809)     0.822   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.427ns (1.588ns logic, 0.839ns route)
-                                                       (65.4% logic, 34.6% route)
-
---------------------------------------------------------------------------------
-
-Hold Paths: COMP "P2L_DATA<9>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKn"
-        HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[9].U/FDRSE0 (K17.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.308ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<9> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[9].U/FDRSE0 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_n rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.862ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<9> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[9].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    K17.ICLK1            Tioickpd    (-Th)    -2.770   P2L_DATA<9>
-                                                       P2L_DATA<9>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[9].U/IBUF1
-                                                       P2L_DATA<9>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[9].U/FDRSE0
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[9].U/FDRSE0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.I                Tiopi                 1.661   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLKn_ibuf/IBUFDS
-                                                       P2L_CLKn.DELAY_ADJ
-    BUFGMUX_X2Y11.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_n_buf
-    BUFGMUX_X2Y11.O      Tgi0o                 0.212   cmp_gn4124_core/CLKn_bufg
-                                                       cmp_gn4124_core/CLKn_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLKn_bufg
-    K17.ICLK1            net (fanout=50)       0.967   cmp_gn4124_core/clk_n
-    -------------------------------------------------  ---------------------------
-    Total                                      2.862ns (1.873ns logic, 0.989ns route)
-                                                       (65.4% logic, 34.6% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[9].U/FDRSE1 (K17.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.308ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DATA<9> (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[9].U/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          0.400ns
-  Data Path Delay:      2.770ns (Levels of Logic = 0)
-  Clock Path Delay:     2.862ns (Levels of Logic = 3)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DATA<9> to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[9].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    K17.ICLK2            Tioickpd    (-Th)    -2.770   P2L_DATA<9>
-                                                       P2L_DATA<9>
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[9].U/IBUF1
-                                                       P2L_DATA<9>.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[9].U/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      2.770ns (2.770ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKn to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_D[9].U/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    E12.PADOUT           Tiopp                 0.739   P2L_CLKn
-                                                       P2L_CLKn
-                                                       cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.DIFFI_IN         net (fanout=1)        0.000   cmp_gn4124_core/CLK_ibuf/SLAVEBUF.DIFFIN
-    C12.I                Tdiffin               0.922   P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    K17.ICLK2            net (fanout=2809)     0.967   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.862ns (1.873ns logic, 0.989ns route)
-                                                       (65.4% logic, 34.6% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "P2L_DFRAME" OFFSET = IN 1.2 ns VALID 3 ns BEFORE COMP 
-"P2L_CLKp" HIGH;
-
- 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors)
- Minimum allowable offset is   0.024ns.
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_F/FDRSE1 (L22.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     1.176ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_DFRAME (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_F/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      2.494ns (Levels of Logic = 0)
-  Clock Path Delay:     2.470ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_DFRAME to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_F/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    L22.ICLK1            Tiopickd              2.494   P2L_DFRAME
-                                                       P2L_DFRAME
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_F/IBUF1
-                                                       P2L_DFRAME.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_F/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      2.494ns (2.494ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_F/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.470   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    L22.ICLK1            net (fanout=2809)     0.866   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.470ns (1.587ns logic, 0.883ns route)
-                                                       (64.3% logic, 35.7% route)
-
---------------------------------------------------------------------------------
-
-Hold Paths: COMP "P2L_DFRAME" OFFSET = IN 1.2 ns VALID 3 ns BEFORE COMP "P2L_CLKp" HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_F/FDRSE1 (L22.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      1.198ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_DFRAME (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_F/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          1.800ns
-  Data Path Delay:      2.312ns (Levels of Logic = 0)
-  Clock Path Delay:     2.914ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_DFRAME to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_F/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    L22.ICLK1            Tioickpd    (-Th)    -2.312   P2L_DFRAME
-                                                       P2L_DFRAME
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_F/IBUF1
-                                                       P2L_DFRAME.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_F/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      2.312ns (2.312ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_F/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.661   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    L22.ICLK1            net (fanout=2809)     1.019   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.914ns (1.873ns logic, 1.041ns route)
-                                                       (64.3% logic, 35.7% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: COMP "P2L_VALID" OFFSET = IN 1.2 ns VALID 3 ns BEFORE COMP 
-"P2L_CLKp" HIGH;
-
- 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors)
- Minimum allowable offset is   0.024ns.
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_V/FDRSE1 (M22.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     1.176ns (requirement - (data path - clock path - clock arrival + uncertainty))
-  Source:               P2L_VALID (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_V/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          1.200ns
-  Data Path Delay:      2.494ns (Levels of Logic = 0)
-  Clock Path Delay:     2.470ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: P2L_VALID to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_V/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    M22.ICLK1            Tiopickd              2.494   P2L_VALID
-                                                       P2L_VALID
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_V/IBUF1
-                                                       P2L_VALID.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_V/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      2.494ns (2.494ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Minimum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_V/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.470   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.017   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.117   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    M22.ICLK1            net (fanout=2809)     0.866   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.470ns (1.587ns logic, 0.883ns route)
-                                                       (64.3% logic, 35.7% route)
-
---------------------------------------------------------------------------------
-
-Hold Paths: COMP "P2L_VALID" OFFSET = IN 1.2 ns VALID 3 ns BEFORE COMP "P2L_CLKp" HIGH;
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_V/FDRSE1 (M22.PAD), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      1.198ns (requirement - (clock path + clock arrival + uncertainty - data path))
-  Source:               P2L_VALID (PAD)
-  Destination:          cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_V/FDRSE1 (FF)
-  Destination Clock:    cmp_gn4124_core/clk_p rising at 0.000ns
-  Requirement:          1.800ns
-  Data Path Delay:      2.312ns (Levels of Logic = 0)
-  Clock Path Delay:     2.914ns (Levels of Logic = 2)
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path: P2L_VALID to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_V/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    M22.ICLK1            Tioickpd    (-Th)    -2.312   P2L_VALID
-                                                       P2L_VALID
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_V/IBUF1
-                                                       P2L_VALID.DELAY_ADJ
-                                                       cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_V/FDRSE1
-    -------------------------------------------------  ---------------------------
-    Total                                      2.312ns (2.312ns logic, 0.000ns route)
-                                                       (100.0% logic, 0.0% route)
-
-  Maximum Clock Path: P2L_CLKp to cmp_gn4124_core/cmp_p2l_des/gen_in_ddr_ff.DDRFF_V/FDRSE1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    C12.I                Tiopi                 1.661   P2L_CLKp
-                                                       P2L_CLKp
-                                                       cmp_gn4124_core/CLK_ibuf/IBUFDS
-                                                       P2L_CLKp.DELAY_ADJ
-    BUFGMUX_X2Y10.I0     net (fanout=1)        0.022   cmp_gn4124_core/clk_p_buf
-    BUFGMUX_X2Y10.O      Tgi0o                 0.212   cmp_gn4124_core/CLK_bufg
-                                                       cmp_gn4124_core/CLK_bufg.GCLKMUX
-                                                       cmp_gn4124_core/CLK_bufg
-    M22.ICLK1            net (fanout=2809)     1.019   cmp_gn4124_core/clk_p
-    -------------------------------------------------  ---------------------------
-    Total                                      2.914ns (1.873ns logic, 1.041ns route)
-                                                       (64.3% logic, 35.7% route)
-
---------------------------------------------------------------------------------
-
-
-1 constraint not met.
-
-
-Data Sheet report:
------------------
-All values displayed in nanoseconds (ns)
-
-Setup/Hold to clock P2L_CLKn
-------------+------------+------------+---------------------+--------+
-            |Max Setup to|Max Hold to |                     | Clock  |
-Source      | clk (edge) | clk (edge) |Internal Clock(s)    | Phase  |
-------------+------------+------------+---------------------+--------+
-P2L_DATA<0> |    0.792(R)|    0.129(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    0.791(R)|    0.129(R)|cmp_gn4124_core/clk_p|   0.000|
-P2L_DATA<1> |    0.765(R)|    0.162(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    0.764(R)|    0.162(R)|cmp_gn4124_core/clk_p|   0.000|
-P2L_DATA<2> |    0.761(R)|    0.166(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    0.760(R)|    0.166(R)|cmp_gn4124_core/clk_p|   0.000|
-P2L_DATA<3> |    0.817(R)|    0.101(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    0.816(R)|    0.101(R)|cmp_gn4124_core/clk_p|   0.000|
-P2L_DATA<4> |    0.777(R)|    0.148(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    0.776(R)|    0.148(R)|cmp_gn4124_core/clk_p|   0.000|
-P2L_DATA<5> |    0.761(R)|    0.166(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    0.760(R)|    0.166(R)|cmp_gn4124_core/clk_p|   0.000|
-P2L_DATA<6> |    0.818(R)|    0.099(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    0.817(R)|    0.099(R)|cmp_gn4124_core/clk_p|   0.000|
-P2L_DATA<7> |    0.765(R)|    0.162(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    0.764(R)|    0.162(R)|cmp_gn4124_core/clk_p|   0.000|
-P2L_DATA<8> |    0.777(R)|    0.147(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    0.784(R)|    0.139(R)|cmp_gn4124_core/clk_p|   0.000|
-P2L_DATA<9> |    0.824(R)|    0.092(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    0.823(R)|    0.092(R)|cmp_gn4124_core/clk_p|   0.000|
-P2L_DATA<10>|    0.771(R)|    0.154(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    0.778(R)|    0.146(R)|cmp_gn4124_core/clk_p|   0.000|
-P2L_DATA<11>|    0.768(R)|    0.158(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    0.774(R)|    0.150(R)|cmp_gn4124_core/clk_p|   0.000|
-P2L_DATA<12>|    0.813(R)|    0.105(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    0.814(R)|    0.103(R)|cmp_gn4124_core/clk_p|   0.000|
-P2L_DATA<13>|    0.796(R)|    0.125(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    0.799(R)|    0.120(R)|cmp_gn4124_core/clk_p|   0.000|
-P2L_DATA<14>|    0.768(R)|    0.158(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    0.774(R)|    0.150(R)|cmp_gn4124_core/clk_p|   0.000|
-P2L_DATA<15>|    0.771(R)|    0.154(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    0.778(R)|    0.146(R)|cmp_gn4124_core/clk_p|   0.000|
-------------+------------+------------+---------------------+--------+
-
-Setup/Hold to clock P2L_CLKp
-------------+------------+------------+---------------------+--------+
-            |Max Setup to|Max Hold to |                     | Clock  |
-Source      | clk (edge) | clk (edge) |Internal Clock(s)    | Phase  |
-------------+------------+------------+---------------------+--------+
-P2L_DATA<0> |    0.791(R)|    0.129(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    0.792(R)|    0.129(R)|cmp_gn4124_core/clk_p|   0.000|
-P2L_DATA<1> |    0.764(R)|    0.162(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    0.765(R)|    0.162(R)|cmp_gn4124_core/clk_p|   0.000|
-P2L_DATA<2> |    0.760(R)|    0.166(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    0.761(R)|    0.166(R)|cmp_gn4124_core/clk_p|   0.000|
-P2L_DATA<3> |    0.816(R)|    0.101(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    0.817(R)|    0.101(R)|cmp_gn4124_core/clk_p|   0.000|
-P2L_DATA<4> |    0.776(R)|    0.148(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    0.777(R)|    0.148(R)|cmp_gn4124_core/clk_p|   0.000|
-P2L_DATA<5> |    0.760(R)|    0.166(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    0.761(R)|    0.166(R)|cmp_gn4124_core/clk_p|   0.000|
-P2L_DATA<6> |    0.817(R)|    0.099(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    0.818(R)|    0.099(R)|cmp_gn4124_core/clk_p|   0.000|
-P2L_DATA<7> |    0.764(R)|    0.162(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    0.765(R)|    0.162(R)|cmp_gn4124_core/clk_p|   0.000|
-P2L_DATA<8> |    0.776(R)|    0.147(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    0.785(R)|    0.139(R)|cmp_gn4124_core/clk_p|   0.000|
-P2L_DATA<9> |    0.823(R)|    0.092(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    0.824(R)|    0.092(R)|cmp_gn4124_core/clk_p|   0.000|
-P2L_DATA<10>|    0.770(R)|    0.154(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    0.779(R)|    0.146(R)|cmp_gn4124_core/clk_p|   0.000|
-P2L_DATA<11>|    0.767(R)|    0.158(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    0.775(R)|    0.150(R)|cmp_gn4124_core/clk_p|   0.000|
-P2L_DATA<12>|    0.812(R)|    0.105(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    0.815(R)|    0.103(R)|cmp_gn4124_core/clk_p|   0.000|
-P2L_DATA<13>|    0.795(R)|    0.125(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    0.800(R)|    0.120(R)|cmp_gn4124_core/clk_p|   0.000|
-P2L_DATA<14>|    0.767(R)|    0.158(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    0.775(R)|    0.150(R)|cmp_gn4124_core/clk_p|   0.000|
-P2L_DATA<15>|    0.770(R)|    0.154(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    0.779(R)|    0.146(R)|cmp_gn4124_core/clk_p|   0.000|
-P2L_DFRAME  |    0.024(R)|    0.602(R)|cmp_gn4124_core/clk_p|   0.000|
-P2L_VALID   |    0.024(R)|    0.602(R)|cmp_gn4124_core/clk_p|   0.000|
-------------+------------+------------+---------------------+--------+
-
-Clock P2L_CLKn to Pad
-------------+------------+---------------------+--------+
-            | clk (edge) |                     | Clock  |
-Destination |   to PAD   |Internal Clock(s)    | Phase  |
-------------+------------+---------------------+--------+
-L2P_CLKn    |    6.261(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    6.263(R)|cmp_gn4124_core/clk_p|   0.000|
-L2P_DATA<0> |    6.167(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    6.170(R)|cmp_gn4124_core/clk_p|   0.000|
-L2P_DATA<1> |    6.167(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    6.170(R)|cmp_gn4124_core/clk_p|   0.000|
-L2P_DATA<2> |    6.157(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    6.159(R)|cmp_gn4124_core/clk_p|   0.000|
-L2P_DATA<3> |    6.157(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    6.159(R)|cmp_gn4124_core/clk_p|   0.000|
-L2P_DATA<4> |    6.147(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    6.148(R)|cmp_gn4124_core/clk_p|   0.000|
-L2P_DATA<5> |    6.147(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    6.148(R)|cmp_gn4124_core/clk_p|   0.000|
-L2P_DATA<6> |    6.161(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    6.163(R)|cmp_gn4124_core/clk_p|   0.000|
-L2P_DATA<7> |    6.161(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    6.163(R)|cmp_gn4124_core/clk_p|   0.000|
-L2P_DATA<8> |    6.168(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    6.170(R)|cmp_gn4124_core/clk_p|   0.000|
-L2P_DATA<9> |    6.168(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    6.170(R)|cmp_gn4124_core/clk_p|   0.000|
-L2P_DATA<10>|    6.119(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    6.125(R)|cmp_gn4124_core/clk_p|   0.000|
-L2P_DATA<11>|    6.129(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    6.164(R)|cmp_gn4124_core/clk_p|   0.000|
-L2P_DATA<12>|    6.181(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    6.187(R)|cmp_gn4124_core/clk_p|   0.000|
-L2P_DATA<13>|    6.178(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    6.183(R)|cmp_gn4124_core/clk_p|   0.000|
-L2P_DATA<14>|    6.181(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    6.187(R)|cmp_gn4124_core/clk_p|   0.000|
-L2P_DATA<15>|    6.126(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    6.142(R)|cmp_gn4124_core/clk_p|   0.000|
-L2P_DFRAME  |    6.174(R)|cmp_gn4124_core/clk_n|   0.000|
-L2P_VALID   |    6.122(R)|cmp_gn4124_core/clk_n|   0.000|
-------------+------------+---------------------+--------+
-
-Clock P2L_CLKp to Pad
-------------+------------+---------------------+--------+
-            | clk (edge) |                     | Clock  |
-Destination |   to PAD   |Internal Clock(s)    | Phase  |
-------------+------------+---------------------+--------+
-L2P_CLKp    |    6.261(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    6.263(R)|cmp_gn4124_core/clk_p|   0.000|
-L2P_DATA<0> |    6.167(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    6.170(R)|cmp_gn4124_core/clk_p|   0.000|
-L2P_DATA<1> |    6.167(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    6.170(R)|cmp_gn4124_core/clk_p|   0.000|
-L2P_DATA<2> |    6.157(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    6.159(R)|cmp_gn4124_core/clk_p|   0.000|
-L2P_DATA<3> |    6.157(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    6.159(R)|cmp_gn4124_core/clk_p|   0.000|
-L2P_DATA<4> |    6.147(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    6.148(R)|cmp_gn4124_core/clk_p|   0.000|
-L2P_DATA<5> |    6.147(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    6.148(R)|cmp_gn4124_core/clk_p|   0.000|
-L2P_DATA<6> |    6.161(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    6.163(R)|cmp_gn4124_core/clk_p|   0.000|
-L2P_DATA<7> |    6.161(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    6.163(R)|cmp_gn4124_core/clk_p|   0.000|
-L2P_DATA<8> |    6.168(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    6.170(R)|cmp_gn4124_core/clk_p|   0.000|
-L2P_DATA<9> |    6.168(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    6.170(R)|cmp_gn4124_core/clk_p|   0.000|
-L2P_DATA<10>|    6.119(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    6.125(R)|cmp_gn4124_core/clk_p|   0.000|
-L2P_DATA<11>|    6.129(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    6.164(R)|cmp_gn4124_core/clk_p|   0.000|
-L2P_DATA<12>|    6.181(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    6.187(R)|cmp_gn4124_core/clk_p|   0.000|
-L2P_DATA<13>|    6.178(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    6.183(R)|cmp_gn4124_core/clk_p|   0.000|
-L2P_DATA<14>|    6.181(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    6.187(R)|cmp_gn4124_core/clk_p|   0.000|
-L2P_DATA<15>|    6.126(R)|cmp_gn4124_core/clk_n|   0.000|
-            |    6.142(R)|cmp_gn4124_core/clk_p|   0.000|
-------------+------------+---------------------+--------+
-
-Clock to Setup on destination clock P2L_CLKn
----------------+---------+---------+---------+---------+
-               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
-Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
----------------+---------+---------+---------+---------+
-P2L_CLKn       |    5.820|         |         |         |
-P2L_CLKp       |    5.820|         |         |         |
----------------+---------+---------+---------+---------+
-
-Clock to Setup on destination clock P2L_CLKp
----------------+---------+---------+---------+---------+
-               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
-Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
----------------+---------+---------+---------+---------+
-P2L_CLKn       |    5.820|         |         |         |
-P2L_CLKp       |    5.820|         |         |         |
----------------+---------+---------+---------+---------+
-
-COMP "P2L_DATA<0>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKp"         HIGH;
-Worst Case Data Window 0.921; Ideal Clock Offset To Actual Clock -0.068; 
-------------------+------------+------------+---------+---------+-------------+
-                  |            |            |  Setup  |  Hold   |Source Offset|
-Source            |   Setup    |    Hold    |  Slack  |  Slack  |  To Center  |
-------------------+------------+------------+---------+---------+-------------+
-P2L_DATA<0>       |    0.791(R)|    0.129(R)|    0.409|    0.271|        0.069|
-                  |    0.792(R)|    0.129(R)|    0.408|    0.271|        0.068|
-------------------+------------+------------+---------+---------+-------------+
-Worst Case Summary|       0.792|       0.129|    0.408|    0.271|             |
-------------------+------------+------------+---------+---------+-------------+
-
-COMP "P2L_DATA<0>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKn"         HIGH;
-Worst Case Data Window 0.921; Ideal Clock Offset To Actual Clock -0.068; 
-------------------+------------+------------+---------+---------+-------------+
-                  |            |            |  Setup  |  Hold   |Source Offset|
-Source            |   Setup    |    Hold    |  Slack  |  Slack  |  To Center  |
-------------------+------------+------------+---------+---------+-------------+
-P2L_DATA<0>       |    0.792(R)|    0.129(R)|    0.408|    0.271|        0.068|
-                  |    0.791(R)|    0.129(R)|    0.409|    0.271|        0.069|
-------------------+------------+------------+---------+---------+-------------+
-Worst Case Summary|       0.792|       0.129|    0.408|    0.271|             |
-------------------+------------+------------+---------+---------+-------------+
-
-COMP "P2L_DATA<10>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKp"         HIGH;
-Worst Case Data Window 0.933; Ideal Clock Offset To Actual Clock -0.088; 
-------------------+------------+------------+---------+---------+-------------+
-                  |            |            |  Setup  |  Hold   |Source Offset|
-Source            |   Setup    |    Hold    |  Slack  |  Slack  |  To Center  |
-------------------+------------+------------+---------+---------+-------------+
-P2L_DATA<10>      |    0.770(R)|    0.154(R)|    0.430|    0.246|        0.092|
-                  |    0.779(R)|    0.146(R)|    0.421|    0.254|        0.083|
-------------------+------------+------------+---------+---------+-------------+
-Worst Case Summary|       0.779|       0.154|    0.421|    0.246|             |
-------------------+------------+------------+---------+---------+-------------+
-
-COMP "P2L_DATA<10>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKn"         HIGH;
-Worst Case Data Window 0.932; Ideal Clock Offset To Actual Clock -0.088; 
-------------------+------------+------------+---------+---------+-------------+
-                  |            |            |  Setup  |  Hold   |Source Offset|
-Source            |   Setup    |    Hold    |  Slack  |  Slack  |  To Center  |
-------------------+------------+------------+---------+---------+-------------+
-P2L_DATA<10>      |    0.771(R)|    0.154(R)|    0.429|    0.246|        0.092|
-                  |    0.778(R)|    0.146(R)|    0.422|    0.254|        0.084|
-------------------+------------+------------+---------+---------+-------------+
-Worst Case Summary|       0.778|       0.154|    0.422|    0.246|             |
-------------------+------------+------------+---------+---------+-------------+
-
-COMP "P2L_DATA<11>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKp"         HIGH;
-Worst Case Data Window 0.933; Ideal Clock Offset To Actual Clock -0.092; 
-------------------+------------+------------+---------+---------+-------------+
-                  |            |            |  Setup  |  Hold   |Source Offset|
-Source            |   Setup    |    Hold    |  Slack  |  Slack  |  To Center  |
-------------------+------------+------------+---------+---------+-------------+
-P2L_DATA<11>      |    0.767(R)|    0.158(R)|    0.433|    0.242|        0.096|
-                  |    0.775(R)|    0.150(R)|    0.425|    0.250|        0.088|
-------------------+------------+------------+---------+---------+-------------+
-Worst Case Summary|       0.775|       0.158|    0.425|    0.242|             |
-------------------+------------+------------+---------+---------+-------------+
-
-COMP "P2L_DATA<11>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKn"         HIGH;
-Worst Case Data Window 0.932; Ideal Clock Offset To Actual Clock -0.092; 
-------------------+------------+------------+---------+---------+-------------+
-                  |            |            |  Setup  |  Hold   |Source Offset|
-Source            |   Setup    |    Hold    |  Slack  |  Slack  |  To Center  |
-------------------+------------+------------+---------+---------+-------------+
-P2L_DATA<11>      |    0.768(R)|    0.158(R)|    0.432|    0.242|        0.095|
-                  |    0.774(R)|    0.150(R)|    0.426|    0.250|        0.088|
-------------------+------------+------------+---------+---------+-------------+
-Worst Case Summary|       0.774|       0.158|    0.426|    0.242|             |
-------------------+------------+------------+---------+---------+-------------+
-
-COMP "P2L_DATA<12>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKp"         HIGH;
-Worst Case Data Window 0.920; Ideal Clock Offset To Actual Clock -0.045; 
-------------------+------------+------------+---------+---------+-------------+
-                  |            |            |  Setup  |  Hold   |Source Offset|
-Source            |   Setup    |    Hold    |  Slack  |  Slack  |  To Center  |
-------------------+------------+------------+---------+---------+-------------+
-P2L_DATA<12>      |    0.812(R)|    0.105(R)|    0.388|    0.295|        0.047|
-                  |    0.815(R)|    0.103(R)|    0.385|    0.297|        0.044|
-------------------+------------+------------+---------+---------+-------------+
-Worst Case Summary|       0.815|       0.105|    0.385|    0.295|             |
-------------------+------------+------------+---------+---------+-------------+
-
-COMP "P2L_DATA<12>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKn"         HIGH;
-Worst Case Data Window 0.919; Ideal Clock Offset To Actual Clock -0.046; 
-------------------+------------+------------+---------+---------+-------------+
-                  |            |            |  Setup  |  Hold   |Source Offset|
-Source            |   Setup    |    Hold    |  Slack  |  Slack  |  To Center  |
-------------------+------------+------------+---------+---------+-------------+
-P2L_DATA<12>      |    0.813(R)|    0.105(R)|    0.387|    0.295|        0.046|
-                  |    0.814(R)|    0.103(R)|    0.386|    0.297|        0.045|
-------------------+------------+------------+---------+---------+-------------+
-Worst Case Summary|       0.814|       0.105|    0.386|    0.295|             |
-------------------+------------+------------+---------+---------+-------------+
-
-COMP "P2L_DATA<13>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKp"         HIGH;
-Worst Case Data Window 0.925; Ideal Clock Offset To Actual Clock -0.063; 
-------------------+------------+------------+---------+---------+-------------+
-                  |            |            |  Setup  |  Hold   |Source Offset|
-Source            |   Setup    |    Hold    |  Slack  |  Slack  |  To Center  |
-------------------+------------+------------+---------+---------+-------------+
-P2L_DATA<13>      |    0.795(R)|    0.125(R)|    0.405|    0.275|        0.065|
-                  |    0.800(R)|    0.120(R)|    0.400|    0.280|        0.060|
-------------------+------------+------------+---------+---------+-------------+
-Worst Case Summary|       0.800|       0.125|    0.400|    0.275|             |
-------------------+------------+------------+---------+---------+-------------+
-
-COMP "P2L_DATA<13>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKn"         HIGH;
-Worst Case Data Window 0.924; Ideal Clock Offset To Actual Clock -0.063; 
-------------------+------------+------------+---------+---------+-------------+
-                  |            |            |  Setup  |  Hold   |Source Offset|
-Source            |   Setup    |    Hold    |  Slack  |  Slack  |  To Center  |
-------------------+------------+------------+---------+---------+-------------+
-P2L_DATA<13>      |    0.796(R)|    0.125(R)|    0.404|    0.275|        0.065|
-                  |    0.799(R)|    0.120(R)|    0.401|    0.280|        0.061|
-------------------+------------+------------+---------+---------+-------------+
-Worst Case Summary|       0.799|       0.125|    0.401|    0.275|             |
-------------------+------------+------------+---------+---------+-------------+
-
-COMP "P2L_DATA<14>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKp"         HIGH;
-Worst Case Data Window 0.933; Ideal Clock Offset To Actual Clock -0.092; 
-------------------+------------+------------+---------+---------+-------------+
-                  |            |            |  Setup  |  Hold   |Source Offset|
-Source            |   Setup    |    Hold    |  Slack  |  Slack  |  To Center  |
-------------------+------------+------------+---------+---------+-------------+
-P2L_DATA<14>      |    0.767(R)|    0.158(R)|    0.433|    0.242|        0.096|
-                  |    0.775(R)|    0.150(R)|    0.425|    0.250|        0.088|
-------------------+------------+------------+---------+---------+-------------+
-Worst Case Summary|       0.775|       0.158|    0.425|    0.242|             |
-------------------+------------+------------+---------+---------+-------------+
-
-COMP "P2L_DATA<14>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKn"         HIGH;
-Worst Case Data Window 0.932; Ideal Clock Offset To Actual Clock -0.092; 
-------------------+------------+------------+---------+---------+-------------+
-                  |            |            |  Setup  |  Hold   |Source Offset|
-Source            |   Setup    |    Hold    |  Slack  |  Slack  |  To Center  |
-------------------+------------+------------+---------+---------+-------------+
-P2L_DATA<14>      |    0.768(R)|    0.158(R)|    0.432|    0.242|        0.095|
-                  |    0.774(R)|    0.150(R)|    0.426|    0.250|        0.088|
-------------------+------------+------------+---------+---------+-------------+
-Worst Case Summary|       0.774|       0.158|    0.426|    0.242|             |
-------------------+------------+------------+---------+---------+-------------+
-
-COMP "P2L_DATA<15>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKp"         HIGH;
-Worst Case Data Window 0.933; Ideal Clock Offset To Actual Clock -0.088; 
-------------------+------------+------------+---------+---------+-------------+
-                  |            |            |  Setup  |  Hold   |Source Offset|
-Source            |   Setup    |    Hold    |  Slack  |  Slack  |  To Center  |
-------------------+------------+------------+---------+---------+-------------+
-P2L_DATA<15>      |    0.770(R)|    0.154(R)|    0.430|    0.246|        0.092|
-                  |    0.779(R)|    0.146(R)|    0.421|    0.254|        0.083|
-------------------+------------+------------+---------+---------+-------------+
-Worst Case Summary|       0.779|       0.154|    0.421|    0.246|             |
-------------------+------------+------------+---------+---------+-------------+
-
-COMP "P2L_DATA<15>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKn"         HIGH;
-Worst Case Data Window 0.932; Ideal Clock Offset To Actual Clock -0.088; 
-------------------+------------+------------+---------+---------+-------------+
-                  |            |            |  Setup  |  Hold   |Source Offset|
-Source            |   Setup    |    Hold    |  Slack  |  Slack  |  To Center  |
-------------------+------------+------------+---------+---------+-------------+
-P2L_DATA<15>      |    0.771(R)|    0.154(R)|    0.429|    0.246|        0.092|
-                  |    0.778(R)|    0.146(R)|    0.422|    0.254|        0.084|
-------------------+------------+------------+---------+---------+-------------+
-Worst Case Summary|       0.778|       0.154|    0.422|    0.246|             |
-------------------+------------+------------+---------+---------+-------------+
-
-COMP "P2L_DATA<1>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKp"         HIGH;
-Worst Case Data Window 0.927; Ideal Clock Offset To Actual Clock -0.099; 
-------------------+------------+------------+---------+---------+-------------+
-                  |            |            |  Setup  |  Hold   |Source Offset|
-Source            |   Setup    |    Hold    |  Slack  |  Slack  |  To Center  |
-------------------+------------+------------+---------+---------+-------------+
-P2L_DATA<1>       |    0.764(R)|    0.162(R)|    0.436|    0.238|        0.099|
-                  |    0.765(R)|    0.162(R)|    0.435|    0.238|        0.099|
-------------------+------------+------------+---------+---------+-------------+
-Worst Case Summary|       0.765|       0.162|    0.435|    0.238|             |
-------------------+------------+------------+---------+---------+-------------+
-
-COMP "P2L_DATA<1>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKn"         HIGH;
-Worst Case Data Window 0.927; Ideal Clock Offset To Actual Clock -0.099; 
-------------------+------------+------------+---------+---------+-------------+
-                  |            |            |  Setup  |  Hold   |Source Offset|
-Source            |   Setup    |    Hold    |  Slack  |  Slack  |  To Center  |
-------------------+------------+------------+---------+---------+-------------+
-P2L_DATA<1>       |    0.765(R)|    0.162(R)|    0.435|    0.238|        0.099|
-                  |    0.764(R)|    0.162(R)|    0.436|    0.238|        0.099|
-------------------+------------+------------+---------+---------+-------------+
-Worst Case Summary|       0.765|       0.162|    0.435|    0.238|             |
-------------------+------------+------------+---------+---------+-------------+
-
-COMP "P2L_DATA<2>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKp"         HIGH;
-Worst Case Data Window 0.927; Ideal Clock Offset To Actual Clock -0.103; 
-------------------+------------+------------+---------+---------+-------------+
-                  |            |            |  Setup  |  Hold   |Source Offset|
-Source            |   Setup    |    Hold    |  Slack  |  Slack  |  To Center  |
-------------------+------------+------------+---------+---------+-------------+
-P2L_DATA<2>       |    0.760(R)|    0.166(R)|    0.440|    0.234|        0.103|
-                  |    0.761(R)|    0.166(R)|    0.439|    0.234|        0.103|
-------------------+------------+------------+---------+---------+-------------+
-Worst Case Summary|       0.761|       0.166|    0.439|    0.234|             |
-------------------+------------+------------+---------+---------+-------------+
-
-COMP "P2L_DATA<2>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKn"         HIGH;
-Worst Case Data Window 0.927; Ideal Clock Offset To Actual Clock -0.103; 
-------------------+------------+------------+---------+---------+-------------+
-                  |            |            |  Setup  |  Hold   |Source Offset|
-Source            |   Setup    |    Hold    |  Slack  |  Slack  |  To Center  |
-------------------+------------+------------+---------+---------+-------------+
-P2L_DATA<2>       |    0.761(R)|    0.166(R)|    0.439|    0.234|        0.103|
-                  |    0.760(R)|    0.166(R)|    0.440|    0.234|        0.103|
-------------------+------------+------------+---------+---------+-------------+
-Worst Case Summary|       0.761|       0.166|    0.439|    0.234|             |
-------------------+------------+------------+---------+---------+-------------+
-
-COMP "P2L_DATA<3>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKp"         HIGH;
-Worst Case Data Window 0.918; Ideal Clock Offset To Actual Clock -0.042; 
-------------------+------------+------------+---------+---------+-------------+
-                  |            |            |  Setup  |  Hold   |Source Offset|
-Source            |   Setup    |    Hold    |  Slack  |  Slack  |  To Center  |
-------------------+------------+------------+---------+---------+-------------+
-P2L_DATA<3>       |    0.816(R)|    0.101(R)|    0.384|    0.299|        0.043|
-                  |    0.817(R)|    0.101(R)|    0.383|    0.299|        0.042|
-------------------+------------+------------+---------+---------+-------------+
-Worst Case Summary|       0.817|       0.101|    0.383|    0.299|             |
-------------------+------------+------------+---------+---------+-------------+
-
-COMP "P2L_DATA<3>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKn"         HIGH;
-Worst Case Data Window 0.918; Ideal Clock Offset To Actual Clock -0.042; 
-------------------+------------+------------+---------+---------+-------------+
-                  |            |            |  Setup  |  Hold   |Source Offset|
-Source            |   Setup    |    Hold    |  Slack  |  Slack  |  To Center  |
-------------------+------------+------------+---------+---------+-------------+
-P2L_DATA<3>       |    0.817(R)|    0.101(R)|    0.383|    0.299|        0.042|
-                  |    0.816(R)|    0.101(R)|    0.384|    0.299|        0.043|
-------------------+------------+------------+---------+---------+-------------+
-Worst Case Summary|       0.817|       0.101|    0.383|    0.299|             |
-------------------+------------+------------+---------+---------+-------------+
-
-COMP "P2L_DATA<4>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKp"         HIGH;
-Worst Case Data Window 0.925; Ideal Clock Offset To Actual Clock -0.085; 
-------------------+------------+------------+---------+---------+-------------+
-                  |            |            |  Setup  |  Hold   |Source Offset|
-Source            |   Setup    |    Hold    |  Slack  |  Slack  |  To Center  |
-------------------+------------+------------+---------+---------+-------------+
-P2L_DATA<4>       |    0.776(R)|    0.148(R)|    0.424|    0.252|        0.086|
-                  |    0.777(R)|    0.148(R)|    0.423|    0.252|        0.085|
-------------------+------------+------------+---------+---------+-------------+
-Worst Case Summary|       0.777|       0.148|    0.423|    0.252|             |
-------------------+------------+------------+---------+---------+-------------+
-
-COMP "P2L_DATA<4>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKn"         HIGH;
-Worst Case Data Window 0.925; Ideal Clock Offset To Actual Clock -0.085; 
-------------------+------------+------------+---------+---------+-------------+
-                  |            |            |  Setup  |  Hold   |Source Offset|
-Source            |   Setup    |    Hold    |  Slack  |  Slack  |  To Center  |
-------------------+------------+------------+---------+---------+-------------+
-P2L_DATA<4>       |    0.777(R)|    0.148(R)|    0.423|    0.252|        0.085|
-                  |    0.776(R)|    0.148(R)|    0.424|    0.252|        0.086|
-------------------+------------+------------+---------+---------+-------------+
-Worst Case Summary|       0.777|       0.148|    0.423|    0.252|             |
-------------------+------------+------------+---------+---------+-------------+
-
-COMP "P2L_DATA<5>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKp"         HIGH;
-Worst Case Data Window 0.927; Ideal Clock Offset To Actual Clock -0.103; 
-------------------+------------+------------+---------+---------+-------------+
-                  |            |            |  Setup  |  Hold   |Source Offset|
-Source            |   Setup    |    Hold    |  Slack  |  Slack  |  To Center  |
-------------------+------------+------------+---------+---------+-------------+
-P2L_DATA<5>       |    0.760(R)|    0.166(R)|    0.440|    0.234|        0.103|
-                  |    0.761(R)|    0.166(R)|    0.439|    0.234|        0.103|
-------------------+------------+------------+---------+---------+-------------+
-Worst Case Summary|       0.761|       0.166|    0.439|    0.234|             |
-------------------+------------+------------+---------+---------+-------------+
-
-COMP "P2L_DATA<5>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKn"         HIGH;
-Worst Case Data Window 0.927; Ideal Clock Offset To Actual Clock -0.103; 
-------------------+------------+------------+---------+---------+-------------+
-                  |            |            |  Setup  |  Hold   |Source Offset|
-Source            |   Setup    |    Hold    |  Slack  |  Slack  |  To Center  |
-------------------+------------+------------+---------+---------+-------------+
-P2L_DATA<5>       |    0.761(R)|    0.166(R)|    0.439|    0.234|        0.103|
-                  |    0.760(R)|    0.166(R)|    0.440|    0.234|        0.103|
-------------------+------------+------------+---------+---------+-------------+
-Worst Case Summary|       0.761|       0.166|    0.439|    0.234|             |
-------------------+------------+------------+---------+---------+-------------+
-
-COMP "P2L_DATA<6>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKp"         HIGH;
-Worst Case Data Window 0.917; Ideal Clock Offset To Actual Clock -0.041; 
-------------------+------------+------------+---------+---------+-------------+
-                  |            |            |  Setup  |  Hold   |Source Offset|
-Source            |   Setup    |    Hold    |  Slack  |  Slack  |  To Center  |
-------------------+------------+------------+---------+---------+-------------+
-P2L_DATA<6>       |    0.817(R)|    0.099(R)|    0.383|    0.301|        0.041|
-                  |    0.818(R)|    0.099(R)|    0.382|    0.301|        0.041|
-------------------+------------+------------+---------+---------+-------------+
-Worst Case Summary|       0.818|       0.099|    0.382|    0.301|             |
-------------------+------------+------------+---------+---------+-------------+
-
-COMP "P2L_DATA<6>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKn"         HIGH;
-Worst Case Data Window 0.917; Ideal Clock Offset To Actual Clock -0.041; 
-------------------+------------+------------+---------+---------+-------------+
-                  |            |            |  Setup  |  Hold   |Source Offset|
-Source            |   Setup    |    Hold    |  Slack  |  Slack  |  To Center  |
-------------------+------------+------------+---------+---------+-------------+
-P2L_DATA<6>       |    0.818(R)|    0.099(R)|    0.382|    0.301|        0.041|
-                  |    0.817(R)|    0.099(R)|    0.383|    0.301|        0.041|
-------------------+------------+------------+---------+---------+-------------+
-Worst Case Summary|       0.818|       0.099|    0.382|    0.301|             |
-------------------+------------+------------+---------+---------+-------------+
-
-COMP "P2L_DATA<7>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKp"         HIGH;
-Worst Case Data Window 0.927; Ideal Clock Offset To Actual Clock -0.099; 
-------------------+------------+------------+---------+---------+-------------+
-                  |            |            |  Setup  |  Hold   |Source Offset|
-Source            |   Setup    |    Hold    |  Slack  |  Slack  |  To Center  |
-------------------+------------+------------+---------+---------+-------------+
-P2L_DATA<7>       |    0.764(R)|    0.162(R)|    0.436|    0.238|        0.099|
-                  |    0.765(R)|    0.162(R)|    0.435|    0.238|        0.099|
-------------------+------------+------------+---------+---------+-------------+
-Worst Case Summary|       0.765|       0.162|    0.435|    0.238|             |
-------------------+------------+------------+---------+---------+-------------+
-
-COMP "P2L_DATA<7>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKn"         HIGH;
-Worst Case Data Window 0.927; Ideal Clock Offset To Actual Clock -0.099; 
-------------------+------------+------------+---------+---------+-------------+
-                  |            |            |  Setup  |  Hold   |Source Offset|
-Source            |   Setup    |    Hold    |  Slack  |  Slack  |  To Center  |
-------------------+------------+------------+---------+---------+-------------+
-P2L_DATA<7>       |    0.765(R)|    0.162(R)|    0.435|    0.238|        0.099|
-                  |    0.764(R)|    0.162(R)|    0.436|    0.238|        0.099|
-------------------+------------+------------+---------+---------+-------------+
-Worst Case Summary|       0.765|       0.162|    0.435|    0.238|             |
-------------------+------------+------------+---------+---------+-------------+
-
-COMP "P2L_DATA<8>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKp"         HIGH;
-Worst Case Data Window 0.932; Ideal Clock Offset To Actual Clock -0.081; 
-------------------+------------+------------+---------+---------+-------------+
-                  |            |            |  Setup  |  Hold   |Source Offset|
-Source            |   Setup    |    Hold    |  Slack  |  Slack  |  To Center  |
-------------------+------------+------------+---------+---------+-------------+
-P2L_DATA<8>       |    0.776(R)|    0.147(R)|    0.424|    0.253|        0.085|
-                  |    0.785(R)|    0.139(R)|    0.415|    0.261|        0.077|
-------------------+------------+------------+---------+---------+-------------+
-Worst Case Summary|       0.785|       0.147|    0.415|    0.253|             |
-------------------+------------+------------+---------+---------+-------------+
-
-COMP "P2L_DATA<8>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKn"         HIGH;
-Worst Case Data Window 0.931; Ideal Clock Offset To Actual Clock -0.081; 
-------------------+------------+------------+---------+---------+-------------+
-                  |            |            |  Setup  |  Hold   |Source Offset|
-Source            |   Setup    |    Hold    |  Slack  |  Slack  |  To Center  |
-------------------+------------+------------+---------+---------+-------------+
-P2L_DATA<8>       |    0.777(R)|    0.147(R)|    0.423|    0.253|        0.085|
-                  |    0.784(R)|    0.139(R)|    0.416|    0.261|        0.077|
-------------------+------------+------------+---------+---------+-------------+
-Worst Case Summary|       0.784|       0.147|    0.416|    0.253|             |
-------------------+------------+------------+---------+---------+-------------+
-
-COMP "P2L_DATA<9>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKp"         HIGH;
-Worst Case Data Window 0.916; Ideal Clock Offset To Actual Clock -0.034; 
-------------------+------------+------------+---------+---------+-------------+
-                  |            |            |  Setup  |  Hold   |Source Offset|
-Source            |   Setup    |    Hold    |  Slack  |  Slack  |  To Center  |
-------------------+------------+------------+---------+---------+-------------+
-P2L_DATA<9>       |    0.823(R)|    0.092(R)|    0.377|    0.308|        0.035|
-                  |    0.824(R)|    0.092(R)|    0.376|    0.308|        0.034|
-------------------+------------+------------+---------+---------+-------------+
-Worst Case Summary|       0.824|       0.092|    0.376|    0.308|             |
-------------------+------------+------------+---------+---------+-------------+
-
-COMP "P2L_DATA<9>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKn"         HIGH;
-Worst Case Data Window 0.916; Ideal Clock Offset To Actual Clock -0.034; 
-------------------+------------+------------+---------+---------+-------------+
-                  |            |            |  Setup  |  Hold   |Source Offset|
-Source            |   Setup    |    Hold    |  Slack  |  Slack  |  To Center  |
-------------------+------------+------------+---------+---------+-------------+
-P2L_DATA<9>       |    0.824(R)|    0.092(R)|    0.376|    0.308|        0.034|
-                  |    0.823(R)|    0.092(R)|    0.377|    0.308|        0.035|
-------------------+------------+------------+---------+---------+-------------+
-Worst Case Summary|       0.824|       0.092|    0.376|    0.308|             |
-------------------+------------+------------+---------+---------+-------------+
-
-COMP "P2L_DFRAME" OFFSET = IN 1.2 ns VALID 3 ns BEFORE COMP "P2L_CLKp" HIGH;
-Worst Case Data Window 0.626; Ideal Clock Offset To Actual Clock 0.011; 
-------------------+------------+------------+---------+---------+-------------+
-                  |            |            |  Setup  |  Hold   |Source Offset|
-Source            |   Setup    |    Hold    |  Slack  |  Slack  |  To Center  |
-------------------+------------+------------+---------+---------+-------------+
-P2L_DFRAME        |    0.024(R)|    0.602(R)|    1.176|    1.198|       -0.011|
-------------------+------------+------------+---------+---------+-------------+
-Worst Case Summary|       0.024|       0.602|    1.176|    1.198|             |
-------------------+------------+------------+---------+---------+-------------+
-
-COMP "P2L_VALID" OFFSET = IN 1.2 ns VALID 3 ns BEFORE COMP "P2L_CLKp" HIGH;
-Worst Case Data Window 0.626; Ideal Clock Offset To Actual Clock 0.011; 
-------------------+------------+------------+---------+---------+-------------+
-                  |            |            |  Setup  |  Hold   |Source Offset|
-Source            |   Setup    |    Hold    |  Slack  |  Slack  |  To Center  |
-------------------+------------+------------+---------+---------+-------------+
-P2L_VALID         |    0.024(R)|    0.602(R)|    1.176|    1.198|       -0.011|
-------------------+------------+------------+---------+---------+-------------+
-Worst Case Summary|       0.024|       0.602|    1.176|    1.198|             |
-------------------+------------+------------+---------+---------+-------------+
-
-COMP "L2P_CLKn" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKn" HIGH;
-Bus Skew: 0.000 ns; 
------------------------------------------------+-------------+--------------+
-PAD                                            | Delay (ns)  |Edge Skew (ns)|
------------------------------------------------+-------------+--------------+
-L2P_CLKn                                       |        6.263|         0.000|
------------------------------------------------+-------------+--------------+
-
-COMP "L2P_CLKp" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKp" HIGH;
-Bus Skew: 0.000 ns; 
------------------------------------------------+-------------+--------------+
-PAD                                            | Delay (ns)  |Edge Skew (ns)|
------------------------------------------------+-------------+--------------+
-L2P_CLKp                                       |        6.263|         0.000|
------------------------------------------------+-------------+--------------+
-
-COMP "L2P_DATA<0>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKp" HIGH;
-Bus Skew: 0.000 ns; 
------------------------------------------------+-------------+--------------+
-PAD                                            | Delay (ns)  |Edge Skew (ns)|
------------------------------------------------+-------------+--------------+
-L2P_DATA<0>                                    |        6.170|         0.000|
------------------------------------------------+-------------+--------------+
-
-COMP "L2P_DATA<0>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKn" HIGH;
-Bus Skew: 0.000 ns; 
------------------------------------------------+-------------+--------------+
-PAD                                            | Delay (ns)  |Edge Skew (ns)|
------------------------------------------------+-------------+--------------+
-L2P_DATA<0>                                    |        6.170|         0.000|
------------------------------------------------+-------------+--------------+
-
-COMP "L2P_DATA<10>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKp" HIGH;
-Bus Skew: 0.000 ns; 
------------------------------------------------+-------------+--------------+
-PAD                                            | Delay (ns)  |Edge Skew (ns)|
------------------------------------------------+-------------+--------------+
-L2P_DATA<10>                                   |        6.125|         0.000|
------------------------------------------------+-------------+--------------+
-
-COMP "L2P_DATA<10>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKn" HIGH;
-Bus Skew: 0.000 ns; 
------------------------------------------------+-------------+--------------+
-PAD                                            | Delay (ns)  |Edge Skew (ns)|
------------------------------------------------+-------------+--------------+
-L2P_DATA<10>                                   |        6.125|         0.000|
------------------------------------------------+-------------+--------------+
-
-COMP "L2P_DATA<11>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKp" HIGH;
-Bus Skew: 0.000 ns; 
------------------------------------------------+-------------+--------------+
-PAD                                            | Delay (ns)  |Edge Skew (ns)|
------------------------------------------------+-------------+--------------+
-L2P_DATA<11>                                   |        6.164|         0.000|
------------------------------------------------+-------------+--------------+
-
-COMP "L2P_DATA<11>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKn" HIGH;
-Bus Skew: 0.000 ns; 
------------------------------------------------+-------------+--------------+
-PAD                                            | Delay (ns)  |Edge Skew (ns)|
------------------------------------------------+-------------+--------------+
-L2P_DATA<11>                                   |        6.164|         0.000|
------------------------------------------------+-------------+--------------+
-
-COMP "L2P_DATA<12>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKp" HIGH;
-Bus Skew: 0.000 ns; 
------------------------------------------------+-------------+--------------+
-PAD                                            | Delay (ns)  |Edge Skew (ns)|
------------------------------------------------+-------------+--------------+
-L2P_DATA<12>                                   |        6.187|         0.000|
------------------------------------------------+-------------+--------------+
-
-COMP "L2P_DATA<12>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKn" HIGH;
-Bus Skew: 0.000 ns; 
------------------------------------------------+-------------+--------------+
-PAD                                            | Delay (ns)  |Edge Skew (ns)|
------------------------------------------------+-------------+--------------+
-L2P_DATA<12>                                   |        6.187|         0.000|
------------------------------------------------+-------------+--------------+
-
-COMP "L2P_DATA<13>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKp" HIGH;
-Bus Skew: 0.000 ns; 
------------------------------------------------+-------------+--------------+
-PAD                                            | Delay (ns)  |Edge Skew (ns)|
------------------------------------------------+-------------+--------------+
-L2P_DATA<13>                                   |        6.183|         0.000|
------------------------------------------------+-------------+--------------+
-
-COMP "L2P_DATA<13>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKn" HIGH;
-Bus Skew: 0.000 ns; 
------------------------------------------------+-------------+--------------+
-PAD                                            | Delay (ns)  |Edge Skew (ns)|
------------------------------------------------+-------------+--------------+
-L2P_DATA<13>                                   |        6.183|         0.000|
------------------------------------------------+-------------+--------------+
-
-COMP "L2P_DATA<14>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKp" HIGH;
-Bus Skew: 0.000 ns; 
------------------------------------------------+-------------+--------------+
-PAD                                            | Delay (ns)  |Edge Skew (ns)|
------------------------------------------------+-------------+--------------+
-L2P_DATA<14>                                   |        6.187|         0.000|
------------------------------------------------+-------------+--------------+
-
-COMP "L2P_DATA<14>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKn" HIGH;
-Bus Skew: 0.000 ns; 
------------------------------------------------+-------------+--------------+
-PAD                                            | Delay (ns)  |Edge Skew (ns)|
------------------------------------------------+-------------+--------------+
-L2P_DATA<14>                                   |        6.187|         0.000|
------------------------------------------------+-------------+--------------+
-
-COMP "L2P_DATA<15>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKp" HIGH;
-Bus Skew: 0.000 ns; 
------------------------------------------------+-------------+--------------+
-PAD                                            | Delay (ns)  |Edge Skew (ns)|
------------------------------------------------+-------------+--------------+
-L2P_DATA<15>                                   |        6.142|         0.000|
------------------------------------------------+-------------+--------------+
-
-COMP "L2P_DATA<15>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKn" HIGH;
-Bus Skew: 0.000 ns; 
------------------------------------------------+-------------+--------------+
-PAD                                            | Delay (ns)  |Edge Skew (ns)|
------------------------------------------------+-------------+--------------+
-L2P_DATA<15>                                   |        6.142|         0.000|
------------------------------------------------+-------------+--------------+
-
-COMP "L2P_DATA<1>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKp" HIGH;
-Bus Skew: 0.000 ns; 
------------------------------------------------+-------------+--------------+
-PAD                                            | Delay (ns)  |Edge Skew (ns)|
------------------------------------------------+-------------+--------------+
-L2P_DATA<1>                                    |        6.170|         0.000|
------------------------------------------------+-------------+--------------+
-
-COMP "L2P_DATA<1>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKn" HIGH;
-Bus Skew: 0.000 ns; 
------------------------------------------------+-------------+--------------+
-PAD                                            | Delay (ns)  |Edge Skew (ns)|
------------------------------------------------+-------------+--------------+
-L2P_DATA<1>                                    |        6.170|         0.000|
------------------------------------------------+-------------+--------------+
-
-COMP "L2P_DATA<2>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKp" HIGH;
-Bus Skew: 0.000 ns; 
------------------------------------------------+-------------+--------------+
-PAD                                            | Delay (ns)  |Edge Skew (ns)|
------------------------------------------------+-------------+--------------+
-L2P_DATA<2>                                    |        6.159|         0.000|
------------------------------------------------+-------------+--------------+
-
-COMP "L2P_DATA<2>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKn" HIGH;
-Bus Skew: 0.000 ns; 
------------------------------------------------+-------------+--------------+
-PAD                                            | Delay (ns)  |Edge Skew (ns)|
------------------------------------------------+-------------+--------------+
-L2P_DATA<2>                                    |        6.159|         0.000|
------------------------------------------------+-------------+--------------+
-
-COMP "L2P_DATA<3>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKp" HIGH;
-Bus Skew: 0.000 ns; 
------------------------------------------------+-------------+--------------+
-PAD                                            | Delay (ns)  |Edge Skew (ns)|
------------------------------------------------+-------------+--------------+
-L2P_DATA<3>                                    |        6.159|         0.000|
------------------------------------------------+-------------+--------------+
-
-COMP "L2P_DATA<3>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKn" HIGH;
-Bus Skew: 0.000 ns; 
------------------------------------------------+-------------+--------------+
-PAD                                            | Delay (ns)  |Edge Skew (ns)|
------------------------------------------------+-------------+--------------+
-L2P_DATA<3>                                    |        6.159|         0.000|
------------------------------------------------+-------------+--------------+
-
-COMP "L2P_DATA<4>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKp" HIGH;
-Bus Skew: 0.000 ns; 
------------------------------------------------+-------------+--------------+
-PAD                                            | Delay (ns)  |Edge Skew (ns)|
------------------------------------------------+-------------+--------------+
-L2P_DATA<4>                                    |        6.148|         0.000|
------------------------------------------------+-------------+--------------+
-
-COMP "L2P_DATA<4>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKn" HIGH;
-Bus Skew: 0.000 ns; 
------------------------------------------------+-------------+--------------+
-PAD                                            | Delay (ns)  |Edge Skew (ns)|
------------------------------------------------+-------------+--------------+
-L2P_DATA<4>                                    |        6.148|         0.000|
------------------------------------------------+-------------+--------------+
-
-COMP "L2P_DATA<5>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKp" HIGH;
-Bus Skew: 0.000 ns; 
------------------------------------------------+-------------+--------------+
-PAD                                            | Delay (ns)  |Edge Skew (ns)|
------------------------------------------------+-------------+--------------+
-L2P_DATA<5>                                    |        6.148|         0.000|
------------------------------------------------+-------------+--------------+
-
-COMP "L2P_DATA<5>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKn" HIGH;
-Bus Skew: 0.000 ns; 
------------------------------------------------+-------------+--------------+
-PAD                                            | Delay (ns)  |Edge Skew (ns)|
------------------------------------------------+-------------+--------------+
-L2P_DATA<5>                                    |        6.148|         0.000|
------------------------------------------------+-------------+--------------+
-
-COMP "L2P_DATA<6>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKp" HIGH;
-Bus Skew: 0.000 ns; 
------------------------------------------------+-------------+--------------+
-PAD                                            | Delay (ns)  |Edge Skew (ns)|
------------------------------------------------+-------------+--------------+
-L2P_DATA<6>                                    |        6.163|         0.000|
------------------------------------------------+-------------+--------------+
-
-COMP "L2P_DATA<6>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKn" HIGH;
-Bus Skew: 0.000 ns; 
------------------------------------------------+-------------+--------------+
-PAD                                            | Delay (ns)  |Edge Skew (ns)|
------------------------------------------------+-------------+--------------+
-L2P_DATA<6>                                    |        6.163|         0.000|
------------------------------------------------+-------------+--------------+
-
-COMP "L2P_DATA<7>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKp" HIGH;
-Bus Skew: 0.000 ns; 
------------------------------------------------+-------------+--------------+
-PAD                                            | Delay (ns)  |Edge Skew (ns)|
------------------------------------------------+-------------+--------------+
-L2P_DATA<7>                                    |        6.163|         0.000|
------------------------------------------------+-------------+--------------+
-
-COMP "L2P_DATA<7>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKn" HIGH;
-Bus Skew: 0.000 ns; 
------------------------------------------------+-------------+--------------+
-PAD                                            | Delay (ns)  |Edge Skew (ns)|
------------------------------------------------+-------------+--------------+
-L2P_DATA<7>                                    |        6.163|         0.000|
------------------------------------------------+-------------+--------------+
-
-COMP "L2P_DATA<8>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKp" HIGH;
-Bus Skew: 0.000 ns; 
------------------------------------------------+-------------+--------------+
-PAD                                            | Delay (ns)  |Edge Skew (ns)|
------------------------------------------------+-------------+--------------+
-L2P_DATA<8>                                    |        6.170|         0.000|
------------------------------------------------+-------------+--------------+
-
-COMP "L2P_DATA<8>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKn" HIGH;
-Bus Skew: 0.000 ns; 
------------------------------------------------+-------------+--------------+
-PAD                                            | Delay (ns)  |Edge Skew (ns)|
------------------------------------------------+-------------+--------------+
-L2P_DATA<8>                                    |        6.170|         0.000|
------------------------------------------------+-------------+--------------+
-
-COMP "L2P_DATA<9>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKp" HIGH;
-Bus Skew: 0.000 ns; 
------------------------------------------------+-------------+--------------+
-PAD                                            | Delay (ns)  |Edge Skew (ns)|
------------------------------------------------+-------------+--------------+
-L2P_DATA<9>                                    |        6.170|         0.000|
------------------------------------------------+-------------+--------------+
-
-COMP "L2P_DATA<9>" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKn" HIGH;
-Bus Skew: 0.000 ns; 
------------------------------------------------+-------------+--------------+
-PAD                                            | Delay (ns)  |Edge Skew (ns)|
------------------------------------------------+-------------+--------------+
-L2P_DATA<9>                                    |        6.170|         0.000|
------------------------------------------------+-------------+--------------+
-
-COMP "L2P_DFRAME" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKn" HIGH;
-Bus Skew: 0.000 ns; 
------------------------------------------------+-------------+--------------+
-PAD                                            | Delay (ns)  |Edge Skew (ns)|
------------------------------------------------+-------------+--------------+
-L2P_DFRAME                                     |        6.174|         0.000|
------------------------------------------------+-------------+--------------+
-
-COMP "L2P_VALID" OFFSET = OUT 6.5 ns AFTER COMP "P2L_CLKn" HIGH;
-Bus Skew: 0.000 ns; 
------------------------------------------------+-------------+--------------+
-PAD                                            | Delay (ns)  |Edge Skew (ns)|
------------------------------------------------+-------------+--------------+
-L2P_VALID                                      |        6.122|         0.000|
------------------------------------------------+-------------+--------------+
-
-
-Timing summary:
----------------
-
-Timing errors: 132  Score: 37208  (Setup/Max: 37208, Hold: 0)
-
-Constraints cover 34955 paths, 4 nets, and 14790 connections
-
-Design statistics:
-   Minimum period:  13.619ns{1}   (Maximum frequency:  73.427MHz)
-   Maximum path delay from/to any node:   4.946ns
-   Maximum net delay:   0.022ns
-   Minimum input required time before clock:   0.824ns
-   Minimum output required time after clock:   6.263ns
-
-
-------------------------------------Footnotes-----------------------------------
-1)  The minimum period statistic assumes all single cycle delays.
-
-Analysis completed Fri May 13 11:49:15 2011 
---------------------------------------------------------------------------------
-
-Trace Settings:
--------------------------
-Trace Settings 
-
-Peak Memory Usage: 195 MB
-
-
-
diff --git a/hdl/gullwing/rtl/gullwing_wrapper.txt b/hdl/gullwing/rtl/gullwing_wrapper.txt
deleted file mode 100644
index 2a9f96c2c218818fbb78a9dc2584baaabb602018..0000000000000000000000000000000000000000
--- a/hdl/gullwing/rtl/gullwing_wrapper.txt
+++ /dev/null
@@ -1,15 +0,0 @@
--------------------------------
-gullwing_wrapper.vhd memory map
--------------------------------
-
-BAR0:
-
-0x00040000, Read only, Status register 1, Value = 0xDEADBABE
-0x00040004, Read only, Status register 2, Value = 0xBEEFFACE
-0x00040008, Read only, Status register 3, Value = 0x12345678
-0x0004000C, Read only, On-board DEBUG switch status (bit0 to bit 7)
-
-0x00080000, Read/write, Control register 1
-0x00080004, Read/write, Control register 2
-0x00080008, Read/write, Control register 3
-0x0008000C, Read/write, On-board LED control register (bit0 to bit7)
diff --git a/hdl/gullwing/rtl/gullwing_wrapper.vhd b/hdl/gullwing/rtl/gullwing_wrapper.vhd
deleted file mode 100644
index 54e9fa875be14b806d42c5759e90e51dd34d7ac5..0000000000000000000000000000000000000000
--- a/hdl/gullwing/rtl/gullwing_wrapper.vhd
+++ /dev/null
@@ -1,541 +0,0 @@
---------------------------------------------------------------------------------
---                                                                            --
--- CERN BE-CO-HT         GN4124 core for PCIe FMC carrier                     --
---                       http://www.ohwr.org/projects/gn4124-core             --
---------------------------------------------------------------------------------
---
--- unit name: gw_wrapper (gullwing_wrapper.vhd)
---
--- author: Matthieu Cattin (matthieu.cattin@cern.ch)
---
--- date: 20-10-2010
---
--- version: 0.1
---
--- description: Wrapper for the GN4124 core to drop into the FPGA on the
---              Gullwing board
---
--- dependencies:
---
---------------------------------------------------------------------------------
--- last changes: 21-10-2010 (mcattin) Add a RAM block to perform  bi-directional
---                                    DMA tests.
---------------------------------------------------------------------------------
--- TODO: - 
---------------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.NUMERIC_STD.all;
-use work.gn4124_core_pkg.all;
-
-library UNISIM;
-use UNISIM.vcomponents.all;
-
-
-entity gw_wrapper is
-  generic
-    (
-      TAR_ADDR_WDTH : integer := 13     -- not used for this project
-      );
-  port
-    (
-      -- From ASIC Local bus
-      L_CLKp : in std_logic;            -- Running at 100 or 200 Mhz
-      L_CLKn : in std_logic;            -- Running at 100 or 200 Mhz
-
-      L_RST_N   : in std_logic;
-      L_RST33_N : in std_logic;
-
-      SYS_CLKB   : in std_logic;        -- Running at 161 Mhz (for the SDRAM)
-      SYS_CLK    : in std_logic;        -- Running at 161 Mhz (for the SDRAM)
-      RESET_IN_N : in std_logic;
-
-      -- General Purpose Interface
-      GPIO : inout std_logic_vector(15 downto 0);  -- General Purpose Input/Output
-
-      -- PCIe to Local [Inbound Data] - RX
-      P2L_RDY    : out std_logic;                      -- Rx Buffer Full Flag
-      P2L_CLKn   : in  std_logic;                      -- Receiver Source Synchronous Clock-
-      P2L_CLKp   : in  std_logic;                      -- Receiver Source Synchronous Clock+
-      P2L_DATA   : in  std_logic_vector(15 downto 0);  -- Parallel receive data
-      P2L_DFRAME : in  std_logic;                      -- Receive Frame
-      P2L_VALID  : in  std_logic;                      -- Receive Data Valid
-
-      -- Inbound Buffer Request/Status
-      P_WR_REQ : in  std_logic_vector(1 downto 0);  -- PCIe Write Request
-      P_WR_RDY : out std_logic_vector(1 downto 0);  -- PCIe Write Ready
-      RX_ERROR : out std_logic;                     -- Receive Error
-
-      -- Local to Parallel [Outbound Data] - TX
-      L2P_DATA   : out std_logic_vector(15 downto 0);  -- Parallel transmit data
-      L2P_DFRAME : out std_logic;                      -- Transmit Data Frame
-      L2P_VALID  : out std_logic;                      -- Transmit Data Valid
-      L2P_CLKn   : out std_logic;                      -- Transmitter Source Synchronous Clock-
-      L2P_CLKp   : out std_logic;                      -- Transmitter Source Synchronous Clock+
-      L2P_EDB    : out std_logic;                      -- Packet termination and discard
-
-      -- Outbound Buffer Status
-      L2P_RDY    : in std_logic;                     -- Tx Buffer Full Flag
-      L_WR_RDY   : in std_logic_vector(1 downto 0);  -- Local-to-PCIe Write
-      P_RD_D_RDY : in std_logic_vector(1 downto 0);  -- PCIe-to-Local Read Response Data Ready
-      TX_ERROR   : in std_logic;                     -- Transmit Error
-      VC_RDY     : in std_logic_vector(1 downto 0);  -- Channel ready
-
-      -- DDR2 SDRAM Interface
-      CNTRL0_DDR2_DQ         : inout std_logic_vector(31 downto 0);
-      CNTRL0_DDR2_A          : out   std_logic_vector(12 downto 0);
-      CNTRL0_DDR2_BA         : out   std_logic_vector(1 downto 0);
-      CNTRL0_DDR2_CKE        : out   std_logic;
-      CNTRL0_DDR2_CS_N       : out   std_logic;
-      CNTRL0_DDR2_RAS_N      : out   std_logic;
-      CNTRL0_DDR2_CAS_N      : out   std_logic;
-      CNTRL0_DDR2_WE_N       : out   std_logic;
-      CNTRL0_DDR2_ODT        : out   std_logic;
-      CNTRL0_DDR2_DM         : out   std_logic_vector(3 downto 0);
-      CNTRL0_RST_DQS_DIV_IN  : in    std_logic;
-      CNTRL0_RST_DQS_DIV_OUT : out   std_logic;
-      CNTRL0_DDR2_DQS        : inout std_logic_vector(3 downto 0);
-      CNTRL0_DDR2_DQS_N      : inout std_logic_vector(3 downto 0);
-      CNTRL0_DDR2_CK         : out   std_logic_vector(1 downto 0);
-      CNTRL0_DDR2_CK_N       : out   std_logic_vector(1 downto 0);
-
-      MIC_CLKA : out   std_logic;
-      MIC_CLKB : out   std_logic;
-      MIC_DATA : inout std_logic_vector(31 downto 0);
-
-      -- GN1559 related
-      SER              : out std_logic_vector(19 downto 0);
-      SER_H            : out std_logic;
-      SER_V            : out std_logic;
-      SER_F            : out std_logic;
-      SER_SMPTE_BYPASS : out std_logic;
-      SER_DVB_ASI      : out std_logic;
-      SER_SDHDN        : out std_logic;
-
-      -- GN1531 de-serializer6
-      DES              : in    std_logic_vector(19 downto 0);
-      DES_PCLK         : in    std_logic;
-      DES_H            : in    std_logic;
-      DES_V            : in    std_logic;
-      DES_F            : in    std_logic;
-      DES_SMPTE_BYPASS : inout std_logic;
-      DES_DVB_ASI      : inout std_logic;
-      DES_SDHDN        : inout std_logic;
-
-      -- GN4911 Timing Generator
-      SYNCSEPERATOR_H_TIMING : in std_logic;
-      SYNCSEPERATOR_V_TIMING : in std_logic;
-      SYNCSEPERATOR_F_TIMING : in std_logic;
-
-      -- I2C
-      SDA : inout std_logic;
-      SCL : in    std_logic;
-
-      -- Debug Switches
-      DEBUG : in  std_logic_vector(7 downto 0);
-      LED   : out std_logic_vector(7 downto 0);
-
-      -- SPI
-      SPI_SCK  : in  std_logic;
-      SPI_SS   : in  std_logic_vector(4 downto 0);
-      SPI_MOSI : in  std_logic;
-      SPI_MISO : out std_logic;
-
-      PCLK_4911_1531   : in  std_logic;  -- requested by Jared
-      GS4911_HOST_B    : out std_logic;
-      GS4911_SCLK      : out std_logic;
-      GS4911_SDIN      : out std_logic;
-      GS4911_SDOUT     : in  std_logic;
-      GS4911_CSB       : out std_logic;
-      GS4911_LOCK_LOST : in  std_logic;  -- requested by Jared
-      GS4911_REF_LOST  : in  std_logic   -- requested by Jared
-      );
-end gw_wrapper;
-
-architecture rtl of gw_wrapper is
-
-  ------------------------------------------------------------------------------
-  -- Components declaration
-  ------------------------------------------------------------------------------
-
-  component gn4124_core
-    generic(
-      g_BAR0_APERTURE     : integer := 20;  -- BAR0 aperture, defined in GN4124 PCI_BAR_CONFIG register (0x80C)
-                                            -- => number of bits to address periph on the board
-      g_CSR_WB_SLAVES_NB  : integer := 1;   -- Number of CSR wishbone slaves
-      g_DMA_WB_SLAVES_NB  : integer := 1;   -- Number of DMA wishbone slaves
-      g_DMA_WB_ADDR_WIDTH : integer := 26   -- DMA wishbone address bus width
-      );
-    port
-      (
-        ---------------------------------------------------------
-        -- Asynchronous reset from GN4124
-        rst_n_a_i : in std_logic;
-
-        ---------------------------------------------------------
-        -- P2L Direction
-        --
-        -- Source Sync DDR related signals
-        p2l_clk_p_i  : in  std_logic;                      -- Receiver Source Synchronous Clock+
-        p2l_clk_n_i  : in  std_logic;                      -- Receiver Source Synchronous Clock-
-        p2l_data_i   : in  std_logic_vector(15 downto 0);  -- Parallel receive data
-        p2l_dframe_i : in  std_logic;                      -- Receive Frame
-        p2l_valid_i  : in  std_logic;                      -- Receive Data Valid
-        -- P2L Control
-        p2l_rdy_o    : out std_logic;                      -- Rx Buffer Full Flag
-        p_wr_req_i   : in  std_logic_vector(1 downto 0);   -- PCIe Write Request
-        p_wr_rdy_o   : out std_logic_vector(1 downto 0);   -- PCIe Write Ready
-        rx_error_o   : out std_logic;                      -- Receive Error
-
-        ---------------------------------------------------------
-        -- L2P Direction
-        --
-        -- Source Sync DDR related signals
-        l2p_clk_p_o  : out std_logic;                      -- Transmitter Source Synchronous Clock+
-        l2p_clk_n_o  : out std_logic;                      -- Transmitter Source Synchronous Clock-
-        l2p_data_o   : out std_logic_vector(15 downto 0);  -- Parallel transmit data
-        l2p_dframe_o : out std_logic;                      -- Transmit Data Frame
-        l2p_valid_o  : out std_logic;                      -- Transmit Data Valid
-        l2p_edb_o    : out std_logic;                      -- Packet termination and discard
-        -- L2P Control
-        l2p_rdy_i    : in  std_logic;                      -- Tx Buffer Full Flag
-        l_wr_rdy_i   : in  std_logic_vector(1 downto 0);   -- Local-to-PCIe Write
-        p_rd_d_rdy_i : in  std_logic_vector(1 downto 0);   -- PCIe-to-Local Read Response Data Ready
-        tx_error_i   : in  std_logic;                      -- Transmit Error
-        vc_rdy_i     : in  std_logic_vector(1 downto 0);   -- Channel ready
-
-        ---------------------------------------------------------
-        -- Interrupt interface
-        dma_irq_o : out std_logic_vector(1 downto 0);  -- Interrupts sources to IRQ manager
-        irq_p_i   : in  std_logic;                     -- Interrupt request pulse from IRQ manager
-        irq_p_o   : out std_logic;                     -- Interrupt request pulse to GN4124 GPIO
-
-        ---------------------------------------------------------
-        -- Target interface (CSR wishbone master)
-        wb_clk_i : in  std_logic;
-        wb_adr_o : out std_logic_vector(g_BAR0_APERTURE-log2_ceil(g_CSR_WB_SLAVES_NB+1)-1 downto 0);
-        wb_dat_o : out std_logic_vector(31 downto 0);                         -- Data out
-        wb_sel_o : out std_logic_vector(3 downto 0);                          -- Byte select
-        wb_stb_o : out std_logic;
-        wb_we_o  : out std_logic;
-        wb_cyc_o : out std_logic_vector(g_CSR_WB_SLAVES_NB-1 downto 0);
-        wb_dat_i : in  std_logic_vector((32*g_CSR_WB_SLAVES_NB)-1 downto 0);  -- Data in
-        wb_ack_i : in  std_logic_vector(g_CSR_WB_SLAVES_NB-1 downto 0);
-
-        ---------------------------------------------------------
-        -- DMA interface (Pipelined wishbone master)
-        dma_clk_i   : in  std_logic;
-        dma_adr_o   : out std_logic_vector(31 downto 0);
-        dma_dat_o   : out std_logic_vector(31 downto 0);                         -- Data out
-        dma_sel_o   : out std_logic_vector(3 downto 0);                          -- Byte select
-        dma_stb_o   : out std_logic;
-        dma_we_o    : out std_logic;
-        dma_cyc_o   : out std_logic;                                             --_vector(g_DMA_WB_SLAVES_NB-1 downto 0);
-        dma_dat_i   : in  std_logic_vector((32*g_DMA_WB_SLAVES_NB)-1 downto 0);  -- Data in
-        dma_ack_i   : in  std_logic;                                             --_vector(g_DMA_WB_SLAVES_NB-1 downto 0);
-        dma_stall_i : in  std_logic--_vector(g_DMA_WB_SLAVES_NB-1 downto 0)        -- for pipelined Wishbone
-        );
-  end component;  --  gn4124_core
-
-  component dummy_stat_regs_wb_slave
-    port (
-      rst_n_i                 : in  std_logic;
-      wb_clk_i                : in  std_logic;
-      wb_addr_i               : in  std_logic_vector(1 downto 0);
-      wb_data_i               : in  std_logic_vector(31 downto 0);
-      wb_data_o               : out std_logic_vector(31 downto 0);
-      wb_cyc_i                : in  std_logic;
-      wb_sel_i                : in  std_logic_vector(3 downto 0);
-      wb_stb_i                : in  std_logic;
-      wb_we_i                 : in  std_logic;
-      wb_ack_o                : out std_logic;
-      dummy_stat_reg_1_i      : in  std_logic_vector(31 downto 0);
-      dummy_stat_reg_2_i      : in  std_logic_vector(31 downto 0);
-      dummy_stat_reg_3_i      : in  std_logic_vector(31 downto 0);
-      dummy_stat_reg_switch_i : in  std_logic_vector(31 downto 0)
-      );
-  end component;
-
-  component dummy_ctrl_regs_wb_slave
-    port (
-      rst_n_i         : in  std_logic;
-      wb_clk_i        : in  std_logic;
-      wb_addr_i       : in  std_logic_vector(1 downto 0);
-      wb_data_i       : in  std_logic_vector(31 downto 0);
-      wb_data_o       : out std_logic_vector(31 downto 0);
-      wb_cyc_i        : in  std_logic;
-      wb_sel_i        : in  std_logic_vector(3 downto 0);
-      wb_stb_i        : in  std_logic;
-      wb_we_i         : in  std_logic;
-      wb_ack_o        : out std_logic;
-      dummy_reg_1_o   : out std_logic_vector(31 downto 0);
-      dummy_reg_2_o   : out std_logic_vector(31 downto 0);
-      dummy_reg_3_o   : out std_logic_vector(31 downto 0);
-      dummy_reg_led_o : out std_logic_vector(31 downto 0)
-      );
-  end component;
-
-  component ram_2048x32
-    port (
-      clka  : in  std_logic;
-      wea   : in  std_logic_vector(0 downto 0);
-      addra : in  std_logic_vector(10 downto 0);
-      dina  : in  std_logic_vector(31 downto 0);
-      douta : out std_logic_vector(31 downto 0)
-      );
-  end component;
-
-  ------------------------------------------------------------------------------
-  -- Constants declaration
-  ------------------------------------------------------------------------------
-  constant c_BAR0_APERTURE     : integer := 20;
-  constant c_CSR_WB_SLAVES_NB  : integer := 2;
-  constant c_DMA_WB_SLAVES_NB  : integer := 1;
-  constant c_DMA_WB_ADDR_WIDTH : integer := 26;
-
-  ------------------------------------------------------------------------------
-  -- Signals declaration
-  ------------------------------------------------------------------------------
-
-  -- LCLK from GN4124 used as system clock
-  signal l_clk : std_logic;
-
-  -- CSR wishbone bus
-  signal wb_adr   : std_logic_vector(c_BAR0_APERTURE-log2_ceil(c_CSR_WB_SLAVES_NB+1)-1 downto 0);
-  signal wb_dat_i : std_logic_vector((32*c_CSR_WB_SLAVES_NB)-1 downto 0);
-  signal wb_dat_o : std_logic_vector(31 downto 0);
-  signal wb_sel   : std_logic_vector(3 downto 0);
-  signal wb_cyc   : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0);
-  signal wb_stb   : std_logic;
-  signal wb_we    : std_logic;
-  signal wb_ack   : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0);
-
-  -- DMA wishbone bus
-  signal dma_adr_o   : std_logic_vector(31 downto 0);
-  signal dma_dat_i   : std_logic_vector((32*c_DMA_WB_SLAVES_NB)-1 downto 0);
-  signal dma_dat_o   : std_logic_vector(31 downto 0);
-  signal dma_sel_o   : std_logic_vector(3 downto 0);
-  signal dma_cyc_o   : std_logic;       --_vector(c_DMA_WB_SLAVES_NB-1 downto 0);
-  signal dma_stb_o   : std_logic;
-  signal dma_we_o    : std_logic;
-  signal dma_ack_i   : std_logic;       --_vector(c_DMA_WB_SLAVES_NB-1 downto 0);
-  signal dma_stall_i : std_logic;       --_vector(c_DMA_WB_SLAVES_NB-1 downto 0);
-  signal ram_we      : std_logic_vector(0 downto 0);
-
-  -- Interrupts stuff
-  signal irq_sources   : std_logic_vector(1 downto 0);
-  signal irq_to_gn4124 : std_logic;
-
-  -- CSR whisbone slaves for test
-  signal dummy_stat_reg_1      : std_logic_vector(31 downto 0);
-  signal dummy_stat_reg_2      : std_logic_vector(31 downto 0);
-  signal dummy_stat_reg_3      : std_logic_vector(31 downto 0);
-  signal dummy_stat_reg_switch : std_logic_vector(31 downto 0);
-
-  signal dummy_ctrl_reg_1   : std_logic_vector(31 downto 0);
-  signal dummy_ctrl_reg_2   : std_logic_vector(31 downto 0);
-  signal dummy_ctrl_reg_3   : std_logic_vector(31 downto 0);
-  signal dummy_ctrl_reg_led : std_logic_vector(31 downto 0);
-
-begin
-
-  ------------------------------------------------------------------------------
-  -- System clock from gennum LCLK
-  ------------------------------------------------------------------------------
-  cmp_sysclk_buf : IBUFDS
-    generic map (
-      DIFF_TERM    => false,            -- Differential Termination
-      IBUF_LOW_PWR => true,             -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
-      IOSTANDARD   => "DEFAULT")
-    port map (
-      O  => l_clk,                      -- Buffer output
-      I  => L_CLKp,                     -- Diff_p buffer input (connect directly to top-level port)
-      IB => L_CLKn                      -- Diff_n buffer input (connect directly to top-level port)
-      );
-
-
-  ------------------------------------------------------------------------------
-  -- Assign static (unused) outputs
-  ------------------------------------------------------------------------------
-  GS4911_CSB       <= '1';
-  SER_SDHDN        <= '0';
-  SER_H            <= '0';
-  SER_V            <= '0';
-  SER_F            <= '0';
-  SPI_MISO         <= '0';
-  GS4911_SCLK      <= '0';
-  GS4911_SDIN      <= '0';
-  SER_DVB_ASI      <= '0';
-  GS4911_HOST_B    <= '0';
-  SER_SMPTE_BYPASS <= '0';
-
-  ------------------------------------------------------------------------------
-  -- GN4124 interface
-  ------------------------------------------------------------------------------
-  cmp_gn4124_core : gn4124_core
-    generic map (
-      g_BAR0_APERTURE     => c_BAR0_APERTURE,
-      g_CSR_WB_SLAVES_NB  => c_CSR_WB_SLAVES_NB,
-      g_DMA_WB_SLAVES_NB  => c_DMA_WB_SLAVES_NB,
-      g_DMA_WB_ADDR_WIDTH => c_DMA_WB_ADDR_WIDTH
-      )
-    port map
-    (
-      ---------------------------------------------------------
-      -- Reset from GN4124
-      rst_n_a_i => L_RST_N,
-
-      ---------------------------------------------------------
-      -- P2L Direction
-      --
-      -- Source Sync DDR related signals
-      p2l_clk_p_i  => P2L_CLKp,
-      p2l_clk_n_i  => P2L_CLKn,
-      p2l_data_i   => P2L_DATA,
-      p2l_dframe_i => P2L_DFRAME,
-      p2l_valid_i  => P2L_VALID,
-
-      -- P2L Control
-      p2l_rdy_o  => P2L_RDY,
-      p_wr_req_i => P_WR_REQ,
-      p_wr_rdy_o => P_WR_RDY,
-      rx_error_o => RX_ERROR,
-
-      ---------------------------------------------------------
-      -- L2P Direction
-      --
-      -- Source Sync DDR related signals
-      l2p_clk_p_o  => L2P_CLKp,
-      l2p_clk_n_o  => L2P_CLKn,
-      l2p_data_o   => L2P_DATA,
-      l2p_dframe_o => L2P_DFRAME,
-      l2p_valid_o  => L2P_VALID,
-      l2p_edb_o    => L2P_EDB,
-
-      -- L2P Control
-      l2p_rdy_i    => L2P_RDY,
-      l_wr_rdy_i   => L_WR_RDY,
-      p_rd_d_rdy_i => P_RD_D_RDY,
-      tx_error_i   => TX_ERROR,
-      vc_rdy_i     => VC_RDY,
-
-      ---------------------------------------------------------
-      -- Interrupt interface
-      dma_irq_o => irq_sources,
-      irq_p_i   => irq_to_gn4124,
-      irq_p_o   => GPIO(8),
-
-      ---------------------------------------------------------
-      -- Target Interface (Wishbone master)
-      wb_clk_i => l_clk,
-      wb_adr_o => wb_adr,
-      wb_dat_o => wb_dat_o,
-      wb_sel_o => wb_sel,
-      wb_stb_o => wb_stb,
-      wb_we_o  => wb_we,
-      wb_cyc_o => wb_cyc,
-      wb_dat_i => wb_dat_i,
-      wb_ack_i => wb_ack,
-
-      ---------------------------------------------------------
-      -- L2P DMA Interface (Pipelined Wishbone master)
-      dma_clk_i   => l_clk,
-      dma_adr_o   => dma_adr_o,
-      dma_dat_o   => dma_dat_o,
-      dma_sel_o   => dma_sel_o,
-      dma_stb_o   => dma_stb_o,
-      dma_we_o    => dma_we_o,
-      dma_cyc_o   => dma_cyc_o,
-      dma_dat_i   => dma_dat_i,
-      dma_ack_i   => dma_ack_i,
-      dma_stall_i => dma_stall_i
-      );
-
-
-  ------------------------------------------------------------------------------
-  -- CSR wishbone bus slaves
-  ------------------------------------------------------------------------------
-  cmp_dummy_stat_regs : dummy_stat_regs_wb_slave
-    port map(
-      rst_n_i                 => L_RST_N,
-      wb_clk_i                => l_clk,
-      wb_addr_i               => wb_adr(1 downto 0),
-      wb_data_i               => wb_dat_o,
-      wb_data_o               => wb_dat_i(31 downto 0),
-      wb_cyc_i                => wb_cyc(0),
-      wb_sel_i                => wb_sel,
-      wb_stb_i                => wb_stb,
-      wb_we_i                 => wb_we,
-      wb_ack_o                => wb_ack(0),
-      dummy_stat_reg_1_i      => dummy_stat_reg_1,
-      dummy_stat_reg_2_i      => dummy_stat_reg_2,
-      dummy_stat_reg_3_i      => dummy_stat_reg_3,
-      dummy_stat_reg_switch_i => dummy_stat_reg_switch
-      );
-
-  dummy_stat_reg_1      <= X"DEADBABE";
-  dummy_stat_reg_2      <= X"BEEFFACE";
-  dummy_stat_reg_3      <= X"12345678";
-  dummy_stat_reg_switch <= X"000000" & DEBUG;
-
-  cmp_dummy_ctrl_regs : dummy_ctrl_regs_wb_slave
-    port map(
-      rst_n_i         => L_RST_N,
-      wb_clk_i        => l_clk,
-      wb_addr_i       => wb_adr(1 downto 0),
-      wb_data_i       => wb_dat_o,
-      wb_data_o       => wb_dat_i(63 downto 32),
-      wb_cyc_i        => wb_cyc(1),
-      wb_sel_i        => wb_sel,
-      wb_stb_i        => wb_stb,
-      wb_we_i         => wb_we,
-      wb_ack_o        => wb_ack(1),
-      dummy_reg_1_o   => dummy_ctrl_reg_1,
-      dummy_reg_2_o   => dummy_ctrl_reg_2,
-      dummy_reg_3_o   => dummy_ctrl_reg_3,
-      dummy_reg_led_o => dummy_ctrl_reg_led
-      );
-
-  LED <= dummy_ctrl_reg_led(7 downto 0);
-
-  ------------------------------------------------------------------------------
-  -- DMA wishbone bus connected to a DPRAM
-  ------------------------------------------------------------------------------
-  process (l_clk, L_RST_N)
-  begin
-    if (L_RST_N = '0') then
-      dma_ack_i <= '0';
-    elsif rising_edge(l_clk) then
-      if (dma_cyc_o = '1' and dma_stb_o = '1') then
-        dma_ack_i <= '1';
-      else
-        dma_ack_i <= '0';
-      end if;
-    end if;
-  end process;
-
-  dma_stall_i <= '0';
-
-  ram_we(0) <= dma_we_o and dma_cyc_o and dma_stb_o;
-
-  cmp_test_ram : ram_2048x32
-    port map (
-      clka  => l_clk,
-      wea   => ram_we,
-      addra => dma_adr_o(10 downto 0),
-      dina  => dma_dat_o,
-      douta => dma_dat_i
-      );
-
-
-  ------------------------------------------------------------------------------
-  -- Interrupt stuff
-  ------------------------------------------------------------------------------
-  -- just forward irq pulses for test
-  irq_to_gn4124 <= irq_sources(1) or irq_sources(0) or dummy_ctrl_reg_1(0);
-
-
-end rtl;
-
-
diff --git a/hdl/pfc/ip_cores/coregen.cgc b/hdl/pfc/ip_cores/coregen.cgc
deleted file mode 100644
index d348fff8535919534a1dde547436282fdeeace9f..0000000000000000000000000000000000000000
--- a/hdl/pfc/ip_cores/coregen.cgc
+++ /dev/null
@@ -1,705 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<spirit:design xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.4" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xilinx="http://www.xilinx.com" >
-   <spirit:vendor>xilinx.com</spirit:vendor>
-   <spirit:library>project</spirit:library>
-   <spirit:name>coregen</spirit:name>
-   <spirit:version>1.0</spirit:version>
-   <spirit:componentInstances>
-      <spirit:componentInstance>
-         <spirit:instanceName>fifo_32x512</spirit:instanceName>
-         <spirit:displayName></spirit:displayName>
-         <spirit:description></spirit:description>
-         <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="6.2" />
-         <spirit:configurableElementValues>
-            <spirit:configurableElementValue spirit:referenceId="parameter_almost_empty_flag">false</spirit:configurableElementValue>
-            <spirit:configurableElementValue spirit:referenceId="parameter_write_data_count">false</spirit:configurableElementValue>
-            <spirit:configurableElementValue spirit:referenceId="parameter_full_threshold_negate_value">508</spirit:configurableElementValue>
-            <spirit:configurableElementValue spirit:referenceId="parameter_empty_threshold_negate_value">3</spirit:configurableElementValue>
-            <spirit:configurableElementValue spirit:referenceId="parameter_output_data_width">32</spirit:configurableElementValue>
-            <spirit:configurableElementValue spirit:referenceId="parameter_input_depth">512</spirit:configurableElementValue>
-            <spirit:configurableElementValue spirit:referenceId="parameter_valid_flag">true</spirit:configurableElementValue>
-            <spirit:configurableElementValue spirit:referenceId="parameter_programmable_empty_type">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
-            <spirit:configurableElementValue spirit:referenceId="parameter_write_acknowledge_flag">false</spirit:configurableElementValue>
-            <spirit:configurableElementValue spirit:referenceId="parameter_enable_int_clk">false</spirit:configurableElementValue>
-            <spirit:configurableElementValue spirit:referenceId="parameter_fifo_implementation">Independent_Clocks_Block_RAM</spirit:configurableElementValue>
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--- a/hdl/pfc/ip_cores/coregen.cgp
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diff --git a/hdl/pfc/ip_cores/fifo_32x512.gise b/hdl/pfc/ip_cores/fifo_32x512.gise
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diff --git a/hdl/pfc/ip_cores/fifo_32x512.ncf b/hdl/pfc/ip_cores/fifo_32x512.ncf
deleted file mode 100644
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diff --git a/hdl/pfc/ip_cores/fifo_32x512.ngc b/hdl/pfc/ip_cores/fifo_32x512.ngc
deleted file mode 100644
index 7f60e3d15e357e64a723e6dd027ad11c179c36b3..0000000000000000000000000000000000000000
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rn8::>5<6sA>8=6sa99c94?7|@=9:7p`68c83>4}O<:;0qc77c;295~N3;81vb46k:182M2492we55k50;3xL1563td24k4?:0yK067<ug32<7>51zJ774=zf03:6=4>{I605>{i1081<7?tH512?xh>1:0;6<uG4238yk?><3:1=vF;309~j<?2290:wE:<1:m=<0=83;pD9=>;|l:=2<728qC8>?4}o;:<?6=9rB??<5rn8;:>5<6sA>8=6sa98c94?7|@=9:7p`69c83>4}O<:;0qc76c;295~N3;81vb47k:182M2492we54k50;3xL1563td25k4?:0yK067<ug3j<7>51zJ774=zf0k:6=4>{I605>{i1h81<7?tH512?xh>i:0;6<uG4238yk?f<3:1=vF;309~j<g2290:wE:<1:m=d0=83;pD9=>;|l:e2<728qC8>?4}o;b<?6=9rB??<5rn8c:>5<6sA>8=6sa9`c94?7|@=9:7p`6ac83>4}O<:;0qc7nc;295~N3;81vb4ok:182M2492we5lk50;3xL1563td2mk4?:0yK067<ug3i<7>51zJ774=zf0h:6=4>{I605>{i1k81<7?tH512?xh>j:0;6<uG4238yk?e<3:1=vF;309~j<d2290:wE:<1:m=g0=83;pD9=>;|l:f2<728qC8>?4}o;a<?6=9rB??<5rn8`:>5<6sA>8=6sa9cc94?7|@=9:7p`6bc83>4}O<:;0qc7mc;295~N3;81vb4lk:182M2492we5ok50;3xL1563td2nk4?:0yK067<ug3h<7>51zJ774=zf0i:6=4>{I605>{i1j81<7?tH512?xh>k:0;6<uG4238yk?d<3:1=vF;309~j<e2290:wE:<1:m=f0=83;pD9=>;|l:g2<728qC8>?4}o;`<?6=9rB??<5rn8a:>5<6sA>8=6sa9bc94?7|@=9:7p`6cc83>4}O<:;0qc7lc;295~N3;81vb4mk:182M2492we5nk50;3xL1563td2ok4?:0yK067<ug3o<7>51zJ774=zf0n:6=4>{I605>{i1m81<7?tH512?xh>l:0;6<uG4238yk?c<3:1=vF;309~j<b2290:wE:<1:m=a0=83;pD9=>;|l:`2<728qC8>?4}o;g<?6=9rB??<5rn8f:>5<6sA>8=6sa9ec94?7|@=9:7p`6dc83>4}O<:;0qc7kc;295~N3;81vb4jk:182M2492we5ik50;3xL1563td2hk4?:0yK067<ug3n<7>51zJ774=zf0o:6=4>{I605>{i1l81<7?tH512?xh>m:0;6<uG4238yk?b<3:1=vF;309~j<c2290:wE:<1:m=`0=83;pD9=>;|l:a2<728qC8>?4}o;f<?6=9rB??<5rn8g:>5<6sA>8=6sa9dc94?7|@=9:7p`6ec83>4}O<:;0qc7jc;295~N3;81vb4kk:182M2492we5hk50;3xL1563td2ik4?:0yK067<ug3m<7>51zJ774=zf0l:6=4>{I605>{i1o81<7?tH512?xh>n:0;6<uG4238yk?a<3:1=vF;309~j<`2290:wE:<1:m=c0=83;pD9=>;|l:b2<728qC8>?4}o;e<?6=9rB??<5rn8d:>5<6sA>8=6sa9gc94?7|@=9:7p`6fc83>4}O<:;0qc7ic;295~N3;81vb4hk:182M2492we5kk50;3xL1563td2jk4?:0yK067<ugk;<7>51zJ774=zfh::6=4>{I605>{ii981<7?tH512?xhf8:0;6<uG4238ykg7<3:1=vF;309~jd62290:wE:<1:me50=83;pD9=>;|lb42<728qC8>?4}oc3<?6=9rB??<5rn`2:>5<6sA>8=6saa1c94?7|@=9:7p`n0c83>4}O<:;0qco?c;295~N3;81vqpsO@By`47<a1j>ih=>r@A@x4xFGXrwKL
\ No newline at end of file
diff --git a/hdl/pfc/ip_cores/fifo_32x512.vhd b/hdl/pfc/ip_cores/fifo_32x512.vhd
deleted file mode 100644
index 7441cb13f3cc22b2cba611eb28b545e7cd31d6c0..0000000000000000000000000000000000000000
--- a/hdl/pfc/ip_cores/fifo_32x512.vhd
+++ /dev/null
@@ -1,164 +0,0 @@
---------------------------------------------------------------------------------
---     This file is owned and controlled by Xilinx and must be used           --
---     solely for design, simulation, implementation and creation of          --
---     design files limited to Xilinx devices or technologies. Use            --
---     with non-Xilinx devices or technologies is expressly prohibited        --
---     and immediately terminates your license.                               --
---                                                                            --
---     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"          --
---     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                --
---     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION        --
---     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            --
---     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS              --
---     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                --
---     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE       --
---     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY               --
---     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                --
---     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR         --
---     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF        --
---     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS        --
---     FOR A PARTICULAR PURPOSE.                                              --
---                                                                            --
---     Xilinx products are not intended for use in life support               --
---     appliances, devices, or systems. Use in such applications are          --
---     expressly prohibited.                                                  --
---                                                                            --
---     (c) Copyright 1995-2009 Xilinx, Inc.                                   --
---     All rights reserved.                                                   --
---------------------------------------------------------------------------------
--- You must compile the wrapper file fifo_32x512.vhd when simulating
--- the core, fifo_32x512. When compiling the wrapper file, be sure to
--- reference the XilinxCoreLib VHDL simulation library. For detailed
--- instructions, please refer to the "CORE Generator Help".
-
--- The synthesis directives "translate_off/translate_on" specified
--- below are supported by Xilinx, Mentor Graphics and Synplicity
--- synthesis tools. Ensure they are correct for your synthesis tool(s).
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
--- synthesis translate_off
-Library XilinxCoreLib;
--- synthesis translate_on
-ENTITY fifo_32x512 IS
-	port (
-	rst: IN std_logic;
-	wr_clk: IN std_logic;
-	rd_clk: IN std_logic;
-	din: IN std_logic_VECTOR(31 downto 0);
-	wr_en: IN std_logic;
-	rd_en: IN std_logic;
-	prog_full_thresh_assert: IN std_logic_VECTOR(8 downto 0);
-	prog_full_thresh_negate: IN std_logic_VECTOR(8 downto 0);
-	dout: OUT std_logic_VECTOR(31 downto 0);
-	full: OUT std_logic;
-	empty: OUT std_logic;
-	valid: OUT std_logic;
-	prog_full: OUT std_logic);
-END fifo_32x512;
-
-ARCHITECTURE fifo_32x512_a OF fifo_32x512 IS
--- synthesis translate_off
-component wrapped_fifo_32x512
-	port (
-	rst: IN std_logic;
-	wr_clk: IN std_logic;
-	rd_clk: IN std_logic;
-	din: IN std_logic_VECTOR(31 downto 0);
-	wr_en: IN std_logic;
-	rd_en: IN std_logic;
-	prog_full_thresh_assert: IN std_logic_VECTOR(8 downto 0);
-	prog_full_thresh_negate: IN std_logic_VECTOR(8 downto 0);
-	dout: OUT std_logic_VECTOR(31 downto 0);
-	full: OUT std_logic;
-	empty: OUT std_logic;
-	valid: OUT std_logic;
-	prog_full: OUT std_logic);
-end component;
-
--- Configuration specification 
-	for all : wrapped_fifo_32x512 use entity XilinxCoreLib.fifo_generator_v6_2(behavioral)
-		generic map(
-			c_has_int_clk => 0,
-			c_wr_response_latency => 1,
-			c_rd_freq => 1,
-			c_has_srst => 0,
-			c_enable_rst_sync => 1,
-			c_has_rd_data_count => 0,
-			c_din_width => 32,
-			c_has_wr_data_count => 0,
-			c_full_flags_rst_val => 1,
-			c_implementation_type => 2,
-			c_family => "spartan6",
-			c_use_embedded_reg => 0,
-			c_has_wr_rst => 0,
-			c_wr_freq => 1,
-			c_use_dout_rst => 1,
-			c_underflow_low => 0,
-			c_has_meminit_file => 0,
-			c_has_overflow => 0,
-			c_preload_latency => 1,
-			c_dout_width => 32,
-			c_msgon_val => 1,
-			c_rd_depth => 512,
-			c_default_value => "BlankString",
-			c_mif_file_name => "BlankString",
-			c_error_injection_type => 0,
-			c_has_underflow => 0,
-			c_has_rd_rst => 0,
-			c_has_almost_full => 0,
-			c_has_rst => 1,
-			c_data_count_width => 9,
-			c_has_wr_ack => 0,
-			c_use_ecc => 0,
-			c_wr_ack_low => 0,
-			c_common_clock => 0,
-			c_rd_pntr_width => 9,
-			c_use_fwft_data_count => 0,
-			c_has_almost_empty => 0,
-			c_rd_data_count_width => 9,
-			c_enable_rlocs => 0,
-			c_wr_pntr_width => 9,
-			c_overflow_low => 0,
-			c_prog_empty_type => 0,
-			c_optimization_mode => 0,
-			c_wr_data_count_width => 9,
-			c_preload_regs => 0,
-			c_dout_rst_val => "0",
-			c_has_data_count => 0,
-			c_prog_full_thresh_negate_val => 508,
-			c_wr_depth => 512,
-			c_prog_empty_thresh_negate_val => 3,
-			c_prog_empty_thresh_assert_val => 2,
-			c_has_valid => 1,
-			c_init_wr_pntr_val => 0,
-			c_prog_full_thresh_assert_val => 509,
-			c_use_fifo16_flags => 0,
-			c_has_backup => 0,
-			c_valid_low => 0,
-			c_prim_fifo_type => "512x36",
-			c_count_type => 0,
-			c_prog_full_type => 4,
-			c_memory_type => 1);
--- synthesis translate_on
-BEGIN
--- synthesis translate_off
-U0 : wrapped_fifo_32x512
-		port map (
-			rst => rst,
-			wr_clk => wr_clk,
-			rd_clk => rd_clk,
-			din => din,
-			wr_en => wr_en,
-			rd_en => rd_en,
-			prog_full_thresh_assert => prog_full_thresh_assert,
-			prog_full_thresh_negate => prog_full_thresh_negate,
-			dout => dout,
-			full => full,
-			empty => empty,
-			valid => valid,
-			prog_full => prog_full);
--- synthesis translate_on
-
-END fifo_32x512_a;
-
diff --git a/hdl/pfc/ip_cores/fifo_32x512.vho b/hdl/pfc/ip_cores/fifo_32x512.vho
deleted file mode 100644
index b507e4a76d54224b59abed3c498df93bbf36183f..0000000000000000000000000000000000000000
--- a/hdl/pfc/ip_cores/fifo_32x512.vho
+++ /dev/null
@@ -1,80 +0,0 @@
---------------------------------------------------------------------------------
---     This file is owned and controlled by Xilinx and must be used           --
---     solely for design, simulation, implementation and creation of          --
---     design files limited to Xilinx devices or technologies. Use            --
---     with non-Xilinx devices or technologies is expressly prohibited        --
---     and immediately terminates your license.                               --
---                                                                            --
---     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"          --
---     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                --
---     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION        --
---     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            --
---     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS              --
---     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                --
---     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE       --
---     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY               --
---     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                --
---     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR         --
---     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF        --
---     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS        --
---     FOR A PARTICULAR PURPOSE.                                              --
---                                                                            --
---     Xilinx products are not intended for use in life support               --
---     appliances, devices, or systems. Use in such applications are          --
---     expressly prohibited.                                                  --
---                                                                            --
---     (c) Copyright 1995-2009 Xilinx, Inc.                                   --
---     All rights reserved.                                                   --
---------------------------------------------------------------------------------
--- The following code must appear in the VHDL architecture header:
-
-------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
-component fifo_32x512
-	port (
-	rst: IN std_logic;
-	wr_clk: IN std_logic;
-	rd_clk: IN std_logic;
-	din: IN std_logic_VECTOR(31 downto 0);
-	wr_en: IN std_logic;
-	rd_en: IN std_logic;
-	prog_full_thresh_assert: IN std_logic_VECTOR(8 downto 0);
-	prog_full_thresh_negate: IN std_logic_VECTOR(8 downto 0);
-	dout: OUT std_logic_VECTOR(31 downto 0);
-	full: OUT std_logic;
-	empty: OUT std_logic;
-	valid: OUT std_logic;
-	prog_full: OUT std_logic);
-end component;
-
--- Synplicity black box declaration
-attribute syn_black_box : boolean;
-attribute syn_black_box of fifo_32x512: component is true;
-
--- COMP_TAG_END ------ End COMPONENT Declaration ------------
-
--- The following code must appear in the VHDL architecture
--- body. Substitute your own instance name and net names.
-
-------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
-your_instance_name : fifo_32x512
-		port map (
-			rst => rst,
-			wr_clk => wr_clk,
-			rd_clk => rd_clk,
-			din => din,
-			wr_en => wr_en,
-			rd_en => rd_en,
-			prog_full_thresh_assert => prog_full_thresh_assert,
-			prog_full_thresh_negate => prog_full_thresh_negate,
-			dout => dout,
-			full => full,
-			empty => empty,
-			valid => valid,
-			prog_full => prog_full);
--- INST_TAG_END ------ End INSTANTIATION Template ------------
-
--- You must compile the wrapper file fifo_32x512.vhd when simulating
--- the core, fifo_32x512. When compiling the wrapper file, be sure to
--- reference the XilinxCoreLib VHDL simulation library. For detailed
--- instructions, please refer to the "CORE Generator Help".
-
diff --git a/hdl/pfc/ip_cores/fifo_32x512.xco b/hdl/pfc/ip_cores/fifo_32x512.xco
deleted file mode 100644
index 09cd510a7b37edaa7a8f89ce6d1de4237036f22c..0000000000000000000000000000000000000000
--- a/hdl/pfc/ip_cores/fifo_32x512.xco
+++ /dev/null
@@ -1,84 +0,0 @@
-##############################################################
-#
-# Xilinx Core Generator version 12.2
-# Date: Fri Jan  7 10:26:48 2011
-#
-##############################################################
-#
-#  This file contains the customisation parameters for a
-#  Xilinx CORE Generator IP GUI. It is strongly recommended
-#  that you do not manually alter this file as it may cause
-#  unexpected and unsupported behavior.
-#
-##############################################################
-#
-# BEGIN Project Options
-SET addpads = false
-SET asysymbol = true
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = false
-SET designentry = VHDL
-SET device = xc6slx150t
-SET devicefamily = spartan6
-SET flowvendor = Foundation_ISE
-SET formalverification = false
-SET foundationsym = false
-SET implementationfiletype = Ngc
-SET package = fgg676
-SET removerpms = false
-SET simulationfiles = Behavioral
-SET speedgrade = -2
-SET verilogsim = true
-SET vhdlsim = true
-# END Project Options
-# BEGIN Select
-SELECT Fifo_Generator family Xilinx,_Inc. 6.2
-# END Select
-# BEGIN Parameters
-CSET almost_empty_flag=false
-CSET almost_full_flag=false
-CSET component_name=fifo_32x512
-CSET data_count=false
-CSET data_count_width=9
-CSET disable_timing_violations=false
-CSET dout_reset_value=0
-CSET empty_threshold_assert_value=2
-CSET empty_threshold_negate_value=3
-CSET enable_ecc=false
-CSET enable_int_clk=false
-CSET enable_reset_synchronization=true
-CSET fifo_implementation=Independent_Clocks_Block_RAM
-CSET full_flags_reset_value=1
-CSET full_threshold_assert_value=509
-CSET full_threshold_negate_value=508
-CSET inject_dbit_error=false
-CSET inject_sbit_error=false
-CSET input_data_width=32
-CSET input_depth=512
-CSET output_data_width=32
-CSET output_depth=512
-CSET overflow_flag=false
-CSET overflow_sense=Active_High
-CSET performance_options=Standard_FIFO
-CSET programmable_empty_type=No_Programmable_Empty_Threshold
-CSET programmable_full_type=Multiple_Programmable_Full_Threshold_Input_Ports
-CSET read_clock_frequency=1
-CSET read_data_count=false
-CSET read_data_count_width=9
-CSET reset_pin=true
-CSET reset_type=Asynchronous_Reset
-CSET underflow_flag=false
-CSET underflow_sense=Active_High
-CSET use_dout_reset=true
-CSET use_embedded_registers=false
-CSET use_extra_logic=false
-CSET valid_flag=true
-CSET valid_sense=Active_High
-CSET write_acknowledge_flag=false
-CSET write_acknowledge_sense=Active_High
-CSET write_clock_frequency=1
-CSET write_data_count=false
-CSET write_data_count_width=9
-# END Parameters
-GENERATE
-# CRC: 67a0ef27
diff --git a/hdl/pfc/ip_cores/fifo_32x512.xise b/hdl/pfc/ip_cores/fifo_32x512.xise
deleted file mode 100644
index 5d65b1e829eaae107fea22665d439c5c1ae7a1fc..0000000000000000000000000000000000000000
--- a/hdl/pfc/ip_cores/fifo_32x512.xise
+++ /dev/null
@@ -1,79 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <header>
-    <!-- ISE source project file created by Project Navigator.             -->
-    <!--                                                                   -->
-    <!-- This file contains project source information including a list of -->
-    <!-- project source files, project and process properties.  This file, -->
-    <!-- along with the project source files, is sufficient to open and    -->
-    <!-- implement in ISE Project Navigator.                               -->
-    <!--                                                                   -->
-    <!-- Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved. -->
-  </header>
-
-  <version xil_pn:ise_version="12.2" xil_pn:schema_version="2"/>
-
-  <files>
-    <file xil_pn:name="fifo_32x512.ngc" xil_pn:type="FILE_NGC">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="fifo_32x512.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-      <association xil_pn:name="PostMapSimulation"/>
-      <association xil_pn:name="PostRouteSimulation"/>
-      <association xil_pn:name="PostTranslateSimulation"/>
-    </file>
-    <file xil_pn:name="fifo_32x512.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-      <association xil_pn:name="PostMapSimulation"/>
-      <association xil_pn:name="PostRouteSimulation"/>
-      <association xil_pn:name="PostTranslateSimulation"/>
-    </file>
-  </files>
-
-  <properties>
-    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device" xil_pn:value="xc6slx150t" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|fifo_32x512|fifo_32x512_a" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="fifo_32x512.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/fifo_32x512" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Package" xil_pn:value="fgg676" xil_pn:valueState="default"/>
-    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
-    <!--                                                                                  -->
-    <!-- The following properties are for internal use only. These should not be modified.-->
-    <!--                                                                                  -->
-    <property xil_pn:name="PROP_DesignName" xil_pn:value="fifo_32x512" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-01-07T11:26:53" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="8B4D5ECA23A72BAA598A3BFFBA924B85" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
-  </properties>
-
-  <bindings/>
-
-  <libraries/>
-
-  <autoManagedFiles>
-    <!-- The following files are identified by `include statements in verilog -->
-    <!-- source files and are automatically managed by Project Navigator.     -->
-    <!--                                                                      -->
-    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
-    <!-- project is analyzed based on files automatically identified as       -->
-    <!-- include files.                                                       -->
-  </autoManagedFiles>
-
-</project>
diff --git a/hdl/pfc/ip_cores/fifo_64x512.gise b/hdl/pfc/ip_cores/fifo_64x512.gise
deleted file mode 100644
index 9d7a65cfc9969f1159a15f2526f8ab4951da144d..0000000000000000000000000000000000000000
--- a/hdl/pfc/ip_cores/fifo_64x512.gise
+++ /dev/null
@@ -1,34 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <!--                                                          -->
-
-  <!--             For tool use only. Do not edit.              -->
-
-  <!--                                                          -->
-
-  <!-- ProjectNavigator created generated project file.         -->
-
-  <!-- For use in tracking generated file and other information -->
-
-  <!-- allowing preservation of process status.                 -->
-
-  <!--                                                          -->
-
-  <!-- Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved. -->
-
-  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
-
-  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="fifo_64x512.xise"/>
-
-  <files xmlns="http://www.xilinx.com/XMLSchema">
-    <file xil_pn:fileType="FILE_ASY" xil_pn:name="fifo_64x512.asy" xil_pn:origination="imported"/>
-    <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="fifo_64x512.sym" xil_pn:origination="imported"/>
-    <file xil_pn:fileType="FILE_VEO" xil_pn:name="fifo_64x512.veo" xil_pn:origination="imported"/>
-    <file xil_pn:fileType="FILE_VHO" xil_pn:name="fifo_64x512.vho" xil_pn:origination="imported"/>
-    <file xil_pn:fileType="FILE_USERDOC" xil_pn:name="fifo_generator_readme.txt" xil_pn:origination="imported"/>
-  </files>
-
-  <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
-
-</generated_project>
diff --git a/hdl/pfc/ip_cores/fifo_64x512.ncf b/hdl/pfc/ip_cores/fifo_64x512.ncf
deleted file mode 100644
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..0000000000000000000000000000000000000000
diff --git a/hdl/pfc/ip_cores/fifo_64x512.ngc b/hdl/pfc/ip_cores/fifo_64x512.ngc
deleted file mode 100644
index c63aac739866d0c1b647ab6c5462926d82a297bf..0000000000000000000000000000000000000000
--- a/hdl/pfc/ip_cores/fifo_64x512.ngc
+++ /dev/null
@@ -1,3 +0,0 @@
-XILINX-XDB 0.1 STUB 0.1 ASCII
-XILINX-XDM V1.6e
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\ No newline at end of file
diff --git a/hdl/pfc/ip_cores/fifo_64x512.vhd b/hdl/pfc/ip_cores/fifo_64x512.vhd
deleted file mode 100644
index ab4fcb069caae7ed9cf5cfdf544cf73d816cabad..0000000000000000000000000000000000000000
--- a/hdl/pfc/ip_cores/fifo_64x512.vhd
+++ /dev/null
@@ -1,164 +0,0 @@
---------------------------------------------------------------------------------
---     This file is owned and controlled by Xilinx and must be used           --
---     solely for design, simulation, implementation and creation of          --
---     design files limited to Xilinx devices or technologies. Use            --
---     with non-Xilinx devices or technologies is expressly prohibited        --
---     and immediately terminates your license.                               --
---                                                                            --
---     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"          --
---     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                --
---     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION        --
---     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            --
---     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS              --
---     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                --
---     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE       --
---     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY               --
---     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                --
---     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR         --
---     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF        --
---     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS        --
---     FOR A PARTICULAR PURPOSE.                                              --
---                                                                            --
---     Xilinx products are not intended for use in life support               --
---     appliances, devices, or systems. Use in such applications are          --
---     expressly prohibited.                                                  --
---                                                                            --
---     (c) Copyright 1995-2009 Xilinx, Inc.                                   --
---     All rights reserved.                                                   --
---------------------------------------------------------------------------------
--- You must compile the wrapper file fifo_64x512.vhd when simulating
--- the core, fifo_64x512. When compiling the wrapper file, be sure to
--- reference the XilinxCoreLib VHDL simulation library. For detailed
--- instructions, please refer to the "CORE Generator Help".
-
--- The synthesis directives "translate_off/translate_on" specified
--- below are supported by Xilinx, Mentor Graphics and Synplicity
--- synthesis tools. Ensure they are correct for your synthesis tool(s).
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
--- synthesis translate_off
-Library XilinxCoreLib;
--- synthesis translate_on
-ENTITY fifo_64x512 IS
-	port (
-	rst: IN std_logic;
-	wr_clk: IN std_logic;
-	rd_clk: IN std_logic;
-	din: IN std_logic_VECTOR(63 downto 0);
-	wr_en: IN std_logic;
-	rd_en: IN std_logic;
-	prog_full_thresh_assert: IN std_logic_VECTOR(8 downto 0);
-	prog_full_thresh_negate: IN std_logic_VECTOR(8 downto 0);
-	dout: OUT std_logic_VECTOR(63 downto 0);
-	full: OUT std_logic;
-	empty: OUT std_logic;
-	valid: OUT std_logic;
-	prog_full: OUT std_logic);
-END fifo_64x512;
-
-ARCHITECTURE fifo_64x512_a OF fifo_64x512 IS
--- synthesis translate_off
-component wrapped_fifo_64x512
-	port (
-	rst: IN std_logic;
-	wr_clk: IN std_logic;
-	rd_clk: IN std_logic;
-	din: IN std_logic_VECTOR(63 downto 0);
-	wr_en: IN std_logic;
-	rd_en: IN std_logic;
-	prog_full_thresh_assert: IN std_logic_VECTOR(8 downto 0);
-	prog_full_thresh_negate: IN std_logic_VECTOR(8 downto 0);
-	dout: OUT std_logic_VECTOR(63 downto 0);
-	full: OUT std_logic;
-	empty: OUT std_logic;
-	valid: OUT std_logic;
-	prog_full: OUT std_logic);
-end component;
-
--- Configuration specification 
-	for all : wrapped_fifo_64x512 use entity XilinxCoreLib.fifo_generator_v6_2(behavioral)
-		generic map(
-			c_has_int_clk => 0,
-			c_wr_response_latency => 1,
-			c_rd_freq => 1,
-			c_has_srst => 0,
-			c_enable_rst_sync => 1,
-			c_has_rd_data_count => 0,
-			c_din_width => 64,
-			c_has_wr_data_count => 0,
-			c_full_flags_rst_val => 1,
-			c_implementation_type => 2,
-			c_family => "spartan6",
-			c_use_embedded_reg => 0,
-			c_has_wr_rst => 0,
-			c_wr_freq => 1,
-			c_use_dout_rst => 1,
-			c_underflow_low => 0,
-			c_has_meminit_file => 0,
-			c_has_overflow => 0,
-			c_preload_latency => 1,
-			c_dout_width => 64,
-			c_msgon_val => 1,
-			c_rd_depth => 512,
-			c_default_value => "BlankString",
-			c_mif_file_name => "BlankString",
-			c_error_injection_type => 0,
-			c_has_underflow => 0,
-			c_has_rd_rst => 0,
-			c_has_almost_full => 0,
-			c_has_rst => 1,
-			c_data_count_width => 9,
-			c_has_wr_ack => 0,
-			c_use_ecc => 0,
-			c_wr_ack_low => 0,
-			c_common_clock => 0,
-			c_rd_pntr_width => 9,
-			c_use_fwft_data_count => 0,
-			c_has_almost_empty => 0,
-			c_rd_data_count_width => 9,
-			c_enable_rlocs => 0,
-			c_wr_pntr_width => 9,
-			c_overflow_low => 0,
-			c_prog_empty_type => 0,
-			c_optimization_mode => 0,
-			c_wr_data_count_width => 9,
-			c_preload_regs => 0,
-			c_dout_rst_val => "0",
-			c_has_data_count => 0,
-			c_prog_full_thresh_negate_val => 508,
-			c_wr_depth => 512,
-			c_prog_empty_thresh_negate_val => 3,
-			c_prog_empty_thresh_assert_val => 2,
-			c_has_valid => 1,
-			c_init_wr_pntr_val => 0,
-			c_prog_full_thresh_assert_val => 509,
-			c_use_fifo16_flags => 0,
-			c_has_backup => 0,
-			c_valid_low => 0,
-			c_prim_fifo_type => "512x72",
-			c_count_type => 0,
-			c_prog_full_type => 4,
-			c_memory_type => 1);
--- synthesis translate_on
-BEGIN
--- synthesis translate_off
-U0 : wrapped_fifo_64x512
-		port map (
-			rst => rst,
-			wr_clk => wr_clk,
-			rd_clk => rd_clk,
-			din => din,
-			wr_en => wr_en,
-			rd_en => rd_en,
-			prog_full_thresh_assert => prog_full_thresh_assert,
-			prog_full_thresh_negate => prog_full_thresh_negate,
-			dout => dout,
-			full => full,
-			empty => empty,
-			valid => valid,
-			prog_full => prog_full);
--- synthesis translate_on
-
-END fifo_64x512_a;
-
diff --git a/hdl/pfc/ip_cores/fifo_64x512.vho b/hdl/pfc/ip_cores/fifo_64x512.vho
deleted file mode 100644
index 9cabd0735fff175caf7c1f793cf67581d01f9f56..0000000000000000000000000000000000000000
--- a/hdl/pfc/ip_cores/fifo_64x512.vho
+++ /dev/null
@@ -1,80 +0,0 @@
---------------------------------------------------------------------------------
---     This file is owned and controlled by Xilinx and must be used           --
---     solely for design, simulation, implementation and creation of          --
---     design files limited to Xilinx devices or technologies. Use            --
---     with non-Xilinx devices or technologies is expressly prohibited        --
---     and immediately terminates your license.                               --
---                                                                            --
---     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"          --
---     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                --
---     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION        --
---     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            --
---     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS              --
---     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                --
---     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE       --
---     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY               --
---     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                --
---     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR         --
---     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF        --
---     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS        --
---     FOR A PARTICULAR PURPOSE.                                              --
---                                                                            --
---     Xilinx products are not intended for use in life support               --
---     appliances, devices, or systems. Use in such applications are          --
---     expressly prohibited.                                                  --
---                                                                            --
---     (c) Copyright 1995-2009 Xilinx, Inc.                                   --
---     All rights reserved.                                                   --
---------------------------------------------------------------------------------
--- The following code must appear in the VHDL architecture header:
-
-------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
-component fifo_64x512
-	port (
-	rst: IN std_logic;
-	wr_clk: IN std_logic;
-	rd_clk: IN std_logic;
-	din: IN std_logic_VECTOR(63 downto 0);
-	wr_en: IN std_logic;
-	rd_en: IN std_logic;
-	prog_full_thresh_assert: IN std_logic_VECTOR(8 downto 0);
-	prog_full_thresh_negate: IN std_logic_VECTOR(8 downto 0);
-	dout: OUT std_logic_VECTOR(63 downto 0);
-	full: OUT std_logic;
-	empty: OUT std_logic;
-	valid: OUT std_logic;
-	prog_full: OUT std_logic);
-end component;
-
--- Synplicity black box declaration
-attribute syn_black_box : boolean;
-attribute syn_black_box of fifo_64x512: component is true;
-
--- COMP_TAG_END ------ End COMPONENT Declaration ------------
-
--- The following code must appear in the VHDL architecture
--- body. Substitute your own instance name and net names.
-
-------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
-your_instance_name : fifo_64x512
-		port map (
-			rst => rst,
-			wr_clk => wr_clk,
-			rd_clk => rd_clk,
-			din => din,
-			wr_en => wr_en,
-			rd_en => rd_en,
-			prog_full_thresh_assert => prog_full_thresh_assert,
-			prog_full_thresh_negate => prog_full_thresh_negate,
-			dout => dout,
-			full => full,
-			empty => empty,
-			valid => valid,
-			prog_full => prog_full);
--- INST_TAG_END ------ End INSTANTIATION Template ------------
-
--- You must compile the wrapper file fifo_64x512.vhd when simulating
--- the core, fifo_64x512. When compiling the wrapper file, be sure to
--- reference the XilinxCoreLib VHDL simulation library. For detailed
--- instructions, please refer to the "CORE Generator Help".
-
diff --git a/hdl/pfc/ip_cores/fifo_64x512.xco b/hdl/pfc/ip_cores/fifo_64x512.xco
deleted file mode 100644
index ffbe9ef79c8fab3e9bd7642b1948d22007a28128..0000000000000000000000000000000000000000
--- a/hdl/pfc/ip_cores/fifo_64x512.xco
+++ /dev/null
@@ -1,84 +0,0 @@
-##############################################################
-#
-# Xilinx Core Generator version 12.2
-# Date: Fri Jan  7 10:35:25 2011
-#
-##############################################################
-#
-#  This file contains the customisation parameters for a
-#  Xilinx CORE Generator IP GUI. It is strongly recommended
-#  that you do not manually alter this file as it may cause
-#  unexpected and unsupported behavior.
-#
-##############################################################
-#
-# BEGIN Project Options
-SET addpads = false
-SET asysymbol = true
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = false
-SET designentry = VHDL
-SET device = xc6slx150t
-SET devicefamily = spartan6
-SET flowvendor = Foundation_ISE
-SET formalverification = false
-SET foundationsym = false
-SET implementationfiletype = Ngc
-SET package = fgg676
-SET removerpms = false
-SET simulationfiles = Behavioral
-SET speedgrade = -2
-SET verilogsim = true
-SET vhdlsim = true
-# END Project Options
-# BEGIN Select
-SELECT Fifo_Generator family Xilinx,_Inc. 6.2
-# END Select
-# BEGIN Parameters
-CSET almost_empty_flag=false
-CSET almost_full_flag=false
-CSET component_name=fifo_64x512
-CSET data_count=false
-CSET data_count_width=9
-CSET disable_timing_violations=false
-CSET dout_reset_value=0
-CSET empty_threshold_assert_value=2
-CSET empty_threshold_negate_value=3
-CSET enable_ecc=false
-CSET enable_int_clk=false
-CSET enable_reset_synchronization=true
-CSET fifo_implementation=Independent_Clocks_Block_RAM
-CSET full_flags_reset_value=1
-CSET full_threshold_assert_value=509
-CSET full_threshold_negate_value=508
-CSET inject_dbit_error=false
-CSET inject_sbit_error=false
-CSET input_data_width=64
-CSET input_depth=512
-CSET output_data_width=64
-CSET output_depth=512
-CSET overflow_flag=false
-CSET overflow_sense=Active_High
-CSET performance_options=Standard_FIFO
-CSET programmable_empty_type=No_Programmable_Empty_Threshold
-CSET programmable_full_type=Multiple_Programmable_Full_Threshold_Input_Ports
-CSET read_clock_frequency=1
-CSET read_data_count=false
-CSET read_data_count_width=9
-CSET reset_pin=true
-CSET reset_type=Asynchronous_Reset
-CSET underflow_flag=false
-CSET underflow_sense=Active_High
-CSET use_dout_reset=true
-CSET use_embedded_registers=false
-CSET use_extra_logic=false
-CSET valid_flag=true
-CSET valid_sense=Active_High
-CSET write_acknowledge_flag=false
-CSET write_acknowledge_sense=Active_High
-CSET write_clock_frequency=1
-CSET write_data_count=false
-CSET write_data_count_width=9
-# END Parameters
-GENERATE
-# CRC: 1278c894
diff --git a/hdl/pfc/ip_cores/fifo_64x512.xise b/hdl/pfc/ip_cores/fifo_64x512.xise
deleted file mode 100644
index 4d6e0d84aef105b65fb599e86e99ae8ef843b939..0000000000000000000000000000000000000000
--- a/hdl/pfc/ip_cores/fifo_64x512.xise
+++ /dev/null
@@ -1,79 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <header>
-    <!-- ISE source project file created by Project Navigator.             -->
-    <!--                                                                   -->
-    <!-- This file contains project source information including a list of -->
-    <!-- project source files, project and process properties.  This file, -->
-    <!-- along with the project source files, is sufficient to open and    -->
-    <!-- implement in ISE Project Navigator.                               -->
-    <!--                                                                   -->
-    <!-- Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved. -->
-  </header>
-
-  <version xil_pn:ise_version="12.2" xil_pn:schema_version="2"/>
-
-  <files>
-    <file xil_pn:name="fifo_64x512.ngc" xil_pn:type="FILE_NGC">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="fifo_64x512.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-      <association xil_pn:name="PostMapSimulation"/>
-      <association xil_pn:name="PostRouteSimulation"/>
-      <association xil_pn:name="PostTranslateSimulation"/>
-    </file>
-    <file xil_pn:name="fifo_64x512.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-      <association xil_pn:name="PostMapSimulation"/>
-      <association xil_pn:name="PostRouteSimulation"/>
-      <association xil_pn:name="PostTranslateSimulation"/>
-    </file>
-  </files>
-
-  <properties>
-    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device" xil_pn:value="xc6slx150t" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|fifo_64x512|fifo_64x512_a" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="fifo_64x512.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/fifo_64x512" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Package" xil_pn:value="fgg676" xil_pn:valueState="default"/>
-    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
-    <!--                                                                                  -->
-    <!-- The following properties are for internal use only. These should not be modified.-->
-    <!--                                                                                  -->
-    <property xil_pn:name="PROP_DesignName" xil_pn:value="fifo_64x512" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-01-07T11:35:30" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="C54CB5DD4A299865B42DBF323214859D" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
-  </properties>
-
-  <bindings/>
-
-  <libraries/>
-
-  <autoManagedFiles>
-    <!-- The following files are identified by `include statements in verilog -->
-    <!-- source files and are automatically managed by Project Navigator.     -->
-    <!--                                                                      -->
-    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
-    <!-- project is analyzed based on files automatically identified as       -->
-    <!-- include files.                                                       -->
-  </autoManagedFiles>
-
-</project>
diff --git a/hdl/pfc/ip_cores/ram_2048x32.gise b/hdl/pfc/ip_cores/ram_2048x32.gise
deleted file mode 100644
index 91c82b8b4f5df41fc73cb12c2519e61d35c74561..0000000000000000000000000000000000000000
--- a/hdl/pfc/ip_cores/ram_2048x32.gise
+++ /dev/null
@@ -1,34 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <!--                                                          -->
-
-  <!--             For tool use only. Do not edit.              -->
-
-  <!--                                                          -->
-
-  <!-- ProjectNavigator created generated project file.         -->
-
-  <!-- For use in tracking generated file and other information -->
-
-  <!-- allowing preservation of process status.                 -->
-
-  <!--                                                          -->
-
-  <!-- Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved. -->
-
-  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
-
-  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="ram_2048x32.xise"/>
-
-  <files xmlns="http://www.xilinx.com/XMLSchema">
-    <file xil_pn:fileType="FILE_USERDOC" xil_pn:name="blk_mem_gen_readme.txt" xil_pn:origination="imported"/>
-    <file xil_pn:fileType="FILE_ASY" xil_pn:name="ram_2048x32.asy" xil_pn:origination="imported"/>
-    <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="ram_2048x32.sym" xil_pn:origination="imported"/>
-    <file xil_pn:fileType="FILE_VEO" xil_pn:name="ram_2048x32.veo" xil_pn:origination="imported"/>
-    <file xil_pn:fileType="FILE_VHO" xil_pn:name="ram_2048x32.vho" xil_pn:origination="imported"/>
-  </files>
-
-  <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
-
-</generated_project>
diff --git a/hdl/pfc/ip_cores/ram_2048x32.mif b/hdl/pfc/ip_cores/ram_2048x32.mif
deleted file mode 100644
index b909ba07a296ec0c90c9af38f0bd669f35f0f91e..0000000000000000000000000000000000000000
--- a/hdl/pfc/ip_cores/ram_2048x32.mif
+++ /dev/null
@@ -1,16 +0,0 @@
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-00000000000000000001000100010001
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-00000000000000000000000100000001
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-00000000000000000001000100010001
-00000000000000000001000100010001
-00000000000000000001000100010001
-00000000000000000001000100010001
-00000000000000000001000100010001
-00000000000000000001000100010001
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diff --git a/hdl/pfc/ip_cores/ram_2048x32.ncf b/hdl/pfc/ip_cores/ram_2048x32.ncf
deleted file mode 100644
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..0000000000000000000000000000000000000000
diff --git a/hdl/pfc/ip_cores/ram_2048x32.ngc b/hdl/pfc/ip_cores/ram_2048x32.ngc
deleted file mode 100644
index 457167a90e4d9d773e1443f7ac1ce3985601f192..0000000000000000000000000000000000000000
--- a/hdl/pfc/ip_cores/ram_2048x32.ngc
+++ /dev/null
@@ -1,3 +0,0 @@
-XILINX-XDB 0.1 STUB 0.1 ASCII
-XILINX-XDM V1.6e
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\ No newline at end of file
diff --git a/hdl/pfc/ip_cores/ram_2048x32.vhd b/hdl/pfc/ip_cores/ram_2048x32.vhd
deleted file mode 100644
index 55c99f646d96c13a640f8826931e378e76c42a37..0000000000000000000000000000000000000000
--- a/hdl/pfc/ip_cores/ram_2048x32.vhd
+++ /dev/null
@@ -1,132 +0,0 @@
---------------------------------------------------------------------------------
---     This file is owned and controlled by Xilinx and must be used           --
---     solely for design, simulation, implementation and creation of          --
---     design files limited to Xilinx devices or technologies. Use            --
---     with non-Xilinx devices or technologies is expressly prohibited        --
---     and immediately terminates your license.                               --
---                                                                            --
---     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"          --
---     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                --
---     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION        --
---     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            --
---     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS              --
---     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                --
---     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE       --
---     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY               --
---     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                --
---     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR         --
---     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF        --
---     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS        --
---     FOR A PARTICULAR PURPOSE.                                              --
---                                                                            --
---     Xilinx products are not intended for use in life support               --
---     appliances, devices, or systems. Use in such applications are          --
---     expressly prohibited.                                                  --
---                                                                            --
---     (c) Copyright 1995-2009 Xilinx, Inc.                                   --
---     All rights reserved.                                                   --
---------------------------------------------------------------------------------
--- You must compile the wrapper file ram_2048x32.vhd when simulating
--- the core, ram_2048x32. When compiling the wrapper file, be sure to
--- reference the XilinxCoreLib VHDL simulation library. For detailed
--- instructions, please refer to the "CORE Generator Help".
-
--- The synthesis directives "translate_off/translate_on" specified
--- below are supported by Xilinx, Mentor Graphics and Synplicity
--- synthesis tools. Ensure they are correct for your synthesis tool(s).
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
--- synthesis translate_off
-Library XilinxCoreLib;
--- synthesis translate_on
-ENTITY ram_2048x32 IS
-	port (
-	clka: IN std_logic;
-	wea: IN std_logic_VECTOR(0 downto 0);
-	addra: IN std_logic_VECTOR(10 downto 0);
-	dina: IN std_logic_VECTOR(31 downto 0);
-	douta: OUT std_logic_VECTOR(31 downto 0));
-END ram_2048x32;
-
-ARCHITECTURE ram_2048x32_a OF ram_2048x32 IS
--- synthesis translate_off
-component wrapped_ram_2048x32
-	port (
-	clka: IN std_logic;
-	wea: IN std_logic_VECTOR(0 downto 0);
-	addra: IN std_logic_VECTOR(10 downto 0);
-	dina: IN std_logic_VECTOR(31 downto 0);
-	douta: OUT std_logic_VECTOR(31 downto 0));
-end component;
-
--- Configuration specification 
-	for all : wrapped_ram_2048x32 use entity XilinxCoreLib.blk_mem_gen_v4_2(behavioral)
-		generic map(
-			c_has_regceb => 0,
-			c_has_regcea => 0,
-			c_mem_type => 0,
-			c_rstram_b => 0,
-			c_rstram_a => 0,
-			c_has_injecterr => 0,
-			c_rst_type => "SYNC",
-			c_prim_type => 1,
-			c_read_width_b => 32,
-			c_initb_val => "0",
-			c_family => "spartan6",
-			c_read_width_a => 32,
-			c_disable_warn_bhv_coll => 0,
-			c_use_softecc => 0,
-			c_write_mode_b => "WRITE_FIRST",
-			c_init_file_name => "no_coe_file_loaded",
-			c_write_mode_a => "WRITE_FIRST",
-			c_mux_pipeline_stages => 0,
-			c_has_softecc_output_regs_b => 0,
-			c_has_mem_output_regs_b => 0,
-			c_has_mem_output_regs_a => 0,
-			c_load_init_file => 0,
-			c_xdevicefamily => "spartan6",
-			c_write_depth_b => 2048,
-			c_write_depth_a => 2048,
-			c_has_rstb => 0,
-			c_has_rsta => 0,
-			c_has_mux_output_regs_b => 0,
-			c_inita_val => "0",
-			c_has_mux_output_regs_a => 0,
-			c_addra_width => 11,
-			c_has_softecc_input_regs_a => 0,
-			c_addrb_width => 11,
-			c_default_data => "0",
-			c_use_ecc => 0,
-			c_algorithm => 1,
-			c_disable_warn_bhv_range => 0,
-			c_write_width_b => 32,
-			c_write_width_a => 32,
-			c_read_depth_b => 2048,
-			c_read_depth_a => 2048,
-			c_byte_size => 9,
-			c_sim_collision_check => "ALL",
-			c_common_clk => 0,
-			c_wea_width => 1,
-			c_has_enb => 0,
-			c_web_width => 1,
-			c_has_ena => 0,
-			c_use_byte_web => 0,
-			c_use_byte_wea => 0,
-			c_rst_priority_b => "CE",
-			c_rst_priority_a => "CE",
-			c_use_default_data => 0);
--- synthesis translate_on
-BEGIN
--- synthesis translate_off
-U0 : wrapped_ram_2048x32
-		port map (
-			clka => clka,
-			wea => wea,
-			addra => addra,
-			dina => dina,
-			douta => douta);
--- synthesis translate_on
-
-END ram_2048x32_a;
-
diff --git a/hdl/pfc/ip_cores/ram_2048x32.vho b/hdl/pfc/ip_cores/ram_2048x32.vho
deleted file mode 100644
index 0a94946b6ae2347cae227a612ead262fd0b41bf2..0000000000000000000000000000000000000000
--- a/hdl/pfc/ip_cores/ram_2048x32.vho
+++ /dev/null
@@ -1,64 +0,0 @@
---------------------------------------------------------------------------------
---     This file is owned and controlled by Xilinx and must be used           --
---     solely for design, simulation, implementation and creation of          --
---     design files limited to Xilinx devices or technologies. Use            --
---     with non-Xilinx devices or technologies is expressly prohibited        --
---     and immediately terminates your license.                               --
---                                                                            --
---     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"          --
---     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                --
---     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION        --
---     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            --
---     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS              --
---     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                --
---     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE       --
---     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY               --
---     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                --
---     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR         --
---     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF        --
---     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS        --
---     FOR A PARTICULAR PURPOSE.                                              --
---                                                                            --
---     Xilinx products are not intended for use in life support               --
---     appliances, devices, or systems. Use in such applications are          --
---     expressly prohibited.                                                  --
---                                                                            --
---     (c) Copyright 1995-2009 Xilinx, Inc.                                   --
---     All rights reserved.                                                   --
---------------------------------------------------------------------------------
--- The following code must appear in the VHDL architecture header:
-
-------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
-component ram_2048x32
-	port (
-	clka: IN std_logic;
-	wea: IN std_logic_VECTOR(0 downto 0);
-	addra: IN std_logic_VECTOR(10 downto 0);
-	dina: IN std_logic_VECTOR(31 downto 0);
-	douta: OUT std_logic_VECTOR(31 downto 0));
-end component;
-
--- Synplicity black box declaration
-attribute syn_black_box : boolean;
-attribute syn_black_box of ram_2048x32: component is true;
-
--- COMP_TAG_END ------ End COMPONENT Declaration ------------
-
--- The following code must appear in the VHDL architecture
--- body. Substitute your own instance name and net names.
-
-------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
-your_instance_name : ram_2048x32
-		port map (
-			clka => clka,
-			wea => wea,
-			addra => addra,
-			dina => dina,
-			douta => douta);
--- INST_TAG_END ------ End INSTANTIATION Template ------------
-
--- You must compile the wrapper file ram_2048x32.vhd when simulating
--- the core, ram_2048x32. When compiling the wrapper file, be sure to
--- reference the XilinxCoreLib VHDL simulation library. For detailed
--- instructions, please refer to the "CORE Generator Help".
-
diff --git a/hdl/pfc/ip_cores/ram_2048x32.xco b/hdl/pfc/ip_cores/ram_2048x32.xco
deleted file mode 100644
index f5499f47a1f6057ba1d099b648606b91905c0cc1..0000000000000000000000000000000000000000
--- a/hdl/pfc/ip_cores/ram_2048x32.xco
+++ /dev/null
@@ -1,93 +0,0 @@
-##############################################################
-#
-# Xilinx Core Generator version 12.2
-# Date: Fri Jan  7 10:41:56 2011
-#
-##############################################################
-#
-#  This file contains the customisation parameters for a
-#  Xilinx CORE Generator IP GUI. It is strongly recommended
-#  that you do not manually alter this file as it may cause
-#  unexpected and unsupported behavior.
-#
-##############################################################
-#
-# BEGIN Project Options
-SET addpads = false
-SET asysymbol = true
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = false
-SET designentry = VHDL
-SET device = xc6slx150t
-SET devicefamily = spartan6
-SET flowvendor = Foundation_ISE
-SET formalverification = false
-SET foundationsym = false
-SET implementationfiletype = Ngc
-SET package = fgg676
-SET removerpms = false
-SET simulationfiles = Behavioral
-SET speedgrade = -2
-SET verilogsim = true
-SET vhdlsim = true
-# END Project Options
-# BEGIN Select
-SELECT Block_Memory_Generator family Xilinx,_Inc. 4.2
-# END Select
-# BEGIN Parameters
-CSET additional_inputs_for_power_estimation=false
-CSET algorithm=Minimum_Area
-CSET assume_synchronous_clk=false
-CSET byte_size=9
-CSET coe_file=no_coe_file_loaded
-CSET collision_warnings=ALL
-CSET component_name=ram_2048x32
-CSET disable_collision_warnings=false
-CSET disable_out_of_range_warnings=false
-CSET ecc=false
-CSET ecctype=No_ECC
-CSET enable_a=Always_Enabled
-CSET enable_b=Always_Enabled
-CSET error_injection_type=Single_Bit_Error_Injection
-CSET fill_remaining_memory_locations=false
-CSET load_init_file=false
-CSET memory_type=Single_Port_RAM
-CSET operating_mode_a=WRITE_FIRST
-CSET operating_mode_b=WRITE_FIRST
-CSET output_reset_value_a=0
-CSET output_reset_value_b=0
-CSET pipeline_stages=0
-CSET port_a_clock=100
-CSET port_a_enable_rate=100
-CSET port_a_write_rate=50
-CSET port_b_clock=0
-CSET port_b_enable_rate=0
-CSET port_b_write_rate=0
-CSET primitive=8kx2
-CSET read_width_a=32
-CSET read_width_b=32
-CSET register_porta_input_of_softecc=false
-CSET register_porta_output_of_memory_core=false
-CSET register_porta_output_of_memory_primitives=false
-CSET register_portb_output_of_memory_core=false
-CSET register_portb_output_of_memory_primitives=false
-CSET register_portb_output_of_softecc=false
-CSET remaining_memory_locations=0
-CSET reset_memory_latch_a=false
-CSET reset_memory_latch_b=false
-CSET reset_priority_a=CE
-CSET reset_priority_b=CE
-CSET reset_type=SYNC
-CSET softecc=false
-CSET use_byte_write_enable=false
-CSET use_error_injection_pins=false
-CSET use_regcea_pin=false
-CSET use_regceb_pin=false
-CSET use_rsta_pin=false
-CSET use_rstb_pin=false
-CSET write_depth_a=2048
-CSET write_width_a=32
-CSET write_width_b=32
-# END Parameters
-GENERATE
-# CRC: 9849e069
diff --git a/hdl/pfc/ip_cores/ram_2048x32.xise b/hdl/pfc/ip_cores/ram_2048x32.xise
deleted file mode 100644
index c12bb6eefa9ff5caed01db7729a7a7608a068037..0000000000000000000000000000000000000000
--- a/hdl/pfc/ip_cores/ram_2048x32.xise
+++ /dev/null
@@ -1,79 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <header>
-    <!-- ISE source project file created by Project Navigator.             -->
-    <!--                                                                   -->
-    <!-- This file contains project source information including a list of -->
-    <!-- project source files, project and process properties.  This file, -->
-    <!-- along with the project source files, is sufficient to open and    -->
-    <!-- implement in ISE Project Navigator.                               -->
-    <!--                                                                   -->
-    <!-- Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved. -->
-  </header>
-
-  <version xil_pn:ise_version="12.2" xil_pn:schema_version="2"/>
-
-  <files>
-    <file xil_pn:name="ram_2048x32.ngc" xil_pn:type="FILE_NGC">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="ram_2048x32.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-      <association xil_pn:name="PostMapSimulation"/>
-      <association xil_pn:name="PostRouteSimulation"/>
-      <association xil_pn:name="PostTranslateSimulation"/>
-    </file>
-    <file xil_pn:name="ram_2048x32.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-      <association xil_pn:name="PostMapSimulation"/>
-      <association xil_pn:name="PostRouteSimulation"/>
-      <association xil_pn:name="PostTranslateSimulation"/>
-    </file>
-  </files>
-
-  <properties>
-    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device" xil_pn:value="xc6slx150t" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|ram_2048x32|ram_2048x32_a" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="ram_2048x32.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/ram_2048x32" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Package" xil_pn:value="fgg676" xil_pn:valueState="default"/>
-    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
-    <!--                                                                                  -->
-    <!-- The following properties are for internal use only. These should not be modified.-->
-    <!--                                                                                  -->
-    <property xil_pn:name="PROP_DesignName" xil_pn:value="ram_2048x32" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-01-07T11:42:01" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="D84A7A8449658988155D127CC78AD79C" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
-  </properties>
-
-  <bindings/>
-
-  <libraries/>
-
-  <autoManagedFiles>
-    <!-- The following files are identified by `include statements in verilog -->
-    <!-- source files and are automatically managed by Project Navigator.     -->
-    <!--                                                                      -->
-    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
-    <!-- project is analyzed based on files automatically identified as       -->
-    <!-- include files.                                                       -->
-  </autoManagedFiles>
-
-</project>
diff --git a/hdl/pfc/ip_cores/ram_2048x32_init.coe b/hdl/pfc/ip_cores/ram_2048x32_init.coe
deleted file mode 100644
index afcf1456a26e36c5db8e4944a760e3561012fd57..0000000000000000000000000000000000000000
--- a/hdl/pfc/ip_cores/ram_2048x32_init.coe
+++ /dev/null
@@ -1,41 +0,0 @@
-; This .COE file specifies the contents for a block
-
-; memory of depth=2046, and width=32. In this case, values
-
-; are specified in hexadecimal format.
-
-memory_initialization_radix=16;
-
-memory_initialization_vector=
-
-1111,
-
-1111,
-
-1111,
-
-1111,
-
-1111,
-
-0000,
-
-0101,
-
-0011,
-
-0000,
-
-1111,
-
-1111,
-
-1111,
-
-1111,
-
-1111,
-
-1111,
-
-1111; 
\ No newline at end of file
diff --git a/hdl/pfc/ise_project/pfc_wrapper.bit b/hdl/pfc/ise_project/pfc_wrapper.bit
deleted file mode 100644
index a76e1c83b601291c73ff10fa2acde5921a280e3b..0000000000000000000000000000000000000000
Binary files a/hdl/pfc/ise_project/pfc_wrapper.bit and /dev/null differ
diff --git a/hdl/pfc/ise_project/pfc_wrapper.par b/hdl/pfc/ise_project/pfc_wrapper.par
deleted file mode 100644
index fa1693a6f4873342a0095f2a6d973a7adb3524bc..0000000000000000000000000000000000000000
--- a/hdl/pfc/ise_project/pfc_wrapper.par
+++ /dev/null
@@ -1,353 +0,0 @@
-Release 12.2 par M.63c (lin)
-Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
-
-ABPC10853::  Fri Dec 10 09:45:57 2010
-
-par -w -intstyle ise -ol high -mt off pfc_wrapper_map.ncd pfc_wrapper.ncd
-pfc_wrapper.pcf 
-
-
-Constraints file: pfc_wrapper.pcf.
-Loading device for application Rf_Device from file '6slx150t.nph' in environment /opt/Xilinx/12.2/ISE_DS/ISE/.
-   "pfc_wrapper" is an NCD, version 3.2, device xc6slx150t, package fgg676, speed -3
-WARNING:ConstraintSystem:64 - Constraint <NET "L_WR_RDY_1_IBUF" MAXDELAY = 2 ns;> [pfc_wrapper.pcf(9225)] overrides
-   constraint <NET "L_WR_RDY_1_IBUF" MAXDELAY = 2 ns;> [pfc_wrapper.pcf(9224)] on the design object 'L_WR_RDY_1_IBUF'.
-
-WARNING:ConstraintSystem:64 - Constraint <NET "L_WR_RDY_0_IBUF" MAXDELAY = 2 ns;> [pfc_wrapper.pcf(9227)] overrides
-   constraint <NET "L_WR_RDY_0_IBUF" MAXDELAY = 2 ns;> [pfc_wrapper.pcf(9226)] on the design object 'L_WR_RDY_0_IBUF'.
-
-WARNING:ConstraintSystem:64 - Constraint <NET "VC_RDY<1>_IBUF" MAXDELAY = 2 ns;> [pfc_wrapper.pcf(9231)] overrides
-   constraint <NET "VC_RDY<1>_IBUF" MAXDELAY = 2 ns;> [pfc_wrapper.pcf(9230)] on the design object 'VC_RDY<1>_IBUF'.
-
-WARNING:ConstraintSystem:64 - Constraint <NET "VC_RDY<0>_IBUF" MAXDELAY = 2 ns;> [pfc_wrapper.pcf(9233)] overrides
-   constraint <NET "VC_RDY<0>_IBUF" MAXDELAY = 2 ns;> [pfc_wrapper.pcf(9232)] on the design object 'VC_RDY<0>_IBUF'.
-
-
-Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
-Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
-
-
-Device speed data version:  "PRELIMINARY 1.10 2010-06-28".
-
-
-
-Device Utilization Summary:
-
-Slice Logic Utilization:
-  Number of Slice Registers:                 3,476 out of 184,304    1%
-    Number used as Flip Flops:               3,444
-    Number used as Latches:                     32
-    Number used as Latch-thrus:                  0
-    Number used as AND/OR logics:                0
-  Number of Slice LUTs:                      2,209 out of  92,152    2%
-    Number used as logic:                    1,793 out of  92,152    1%
-      Number using O6 output only:           1,131
-      Number using O5 output only:              66
-      Number using O5 and O6:                  596
-      Number used as ROM:                        0
-    Number used as Memory:                       1 out of  21,680    1%
-      Number used as Dual Port RAM:              0
-      Number used as Single Port RAM:            0
-      Number used as Shift Register:             1
-        Number using O6 output only:             1
-        Number using O5 output only:             0
-        Number using O5 and O6:                  0
-    Number used exclusively as route-thrus:    415
-      Number with same-slice register load:    413
-      Number with same-slice carry load:         2
-      Number with other load:                    0
-
-Slice Logic Distribution:
-  Number of occupied Slices:                 1,111 out of  23,038    4%
-  Number of LUT Flip Flop pairs used:        3,337
-    Number with an unused Flip Flop:           529 out of   3,337   15%
-    Number with an unused LUT:               1,128 out of   3,337   33%
-    Number of fully used LUT-FF pairs:       1,680 out of   3,337   50%
-    Number of slice register sites lost
-      to control set restrictions:               0 out of 184,304    0%
-
-  A LUT Flip Flop pair for this architecture represents one LUT paired with
-  one Flip Flop within a slice.  A control set is a unique combination of
-  clock, reset, set, and enable signals for a registered element.
-  The Slice Logic Distribution report is not meaningful if the design is
-  over-mapped for a non-slice resource or if Placement fails.
-
-IO Utilization:
-  Number of bonded IOBs:                        66 out of     396   16%
-    Number of LOCed IOBs:                       66 out of      66  100%
-    IOB Flip Flops:                              5
-
-Specific Feature Utilization:
-  Number of RAMB16BWERs:                        11 out of     268    4%
-  Number of RAMB8BWERs:                          0 out of     536    0%
-  Number of BUFIO2/BUFIO2_2CLKs:                 1 out of      32    3%
-    Number used as BUFIO2s:                      1
-    Number used as BUFIO2_2CLKs:                 0
-  Number of BUFIO2FB/BUFIO2FB_2CLKs:             1 out of      32    3%
-    Number used as BUFIO2FBs:                    1
-    Number used as BUFIO2FB_2CLKs:               0
-  Number of BUFG/BUFGMUXs:                       3 out of      16   18%
-    Number used as BUFGs:                        3
-    Number used as BUFGMUX:                      0
-  Number of DCM/DCM_CLKGENs:                     0 out of      12    0%
-  Number of ILOGIC2/ISERDES2s:                  25 out of     586    4%
-    Number used as ILOGIC2s:                     5
-    Number used as ISERDES2s:                   20
-  Number of IODELAY2/IODRP2/IODRP2_MCBs:         2 out of     586    1%
-    Number used as IODELAY2s:                    2
-    Number used as IODRP2s:                      0
-    Number used as IODRP2_MCBs:                  0
-  Number of OLOGIC2/OSERDES2s:                  20 out of     586    3%
-    Number used as OLOGIC2s:                     0
-    Number used as OSERDES2s:                   20
-  Number of BSCANs:                              0 out of       4    0%
-  Number of BUFHs:                               0 out of     384    0%
-  Number of BUFPLLs:                             1 out of       8   12%
-  Number of BUFPLL_MCBs:                         0 out of       4    0%
-  Number of DSP48A1s:                            0 out of     180    0%
-  Number of GTPA1_DUALs:                         0 out of       4    0%
-  Number of ICAPs:                               0 out of       1    0%
-  Number of MCBs:                                0 out of       4    0%
-  Number of PCIE_A1s:                            0 out of       1    0%
-  Number of PCILOGICSEs:                         0 out of       2    0%
-  Number of PLL_ADVs:                            1 out of       6   16%
-  Number of PMVs:                                0 out of       1    0%
-  Number of STARTUPs:                            0 out of       1    0%
-  Number of SUSPEND_SYNCs:                       0 out of       1    0%
-
-
-Overall effort level (-ol):   High 
-Router effort level (-rl):    High 
-
-INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more information, see the TSI report.  Please consult the Xilinx
-   Command Line Tools User Guide for information on generating a TSI report.
-Starting initial Timing Analysis.  REAL time: 32 secs 
-Finished initial Timing Analysis.  REAL time: 32 secs 
-
-WARNING:Par:288 - The signal VC_RDY<0>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal VC_RDY<1>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal TX_ERROR_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal P_WR_REQ<0>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal P_WR_REQ<1>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal GPIO<1>_IBUF has no load.  PAR will not attempt to route this signal.
-Starting Router
-
-
-Phase  1  : 15115 unrouted;      REAL time: 37 secs 
-
-Phase  2  : 12467 unrouted;      REAL time: 46 secs 
-
-Phase  3  : 3144 unrouted;      REAL time: 1 mins 25 secs 
-
-Phase  4  : 3162 unrouted; (Setup:1730, Hold:0, Component Switching Limit:0)     REAL time: 1 mins 46 secs 
-
-Updating file: pfc_wrapper.ncd with current fully routed design.
-
-Phase  5  : 0 unrouted; (Setup:1736, Hold:0, Component Switching Limit:0)     REAL time: 2 mins 36 secs 
-
-Phase  6  : 0 unrouted; (Setup:1736, Hold:0, Component Switching Limit:0)     REAL time: 2 mins 38 secs 
-
-Phase  7  : 0 unrouted; (Setup:948, Hold:0, Component Switching Limit:0)     REAL time: 4 mins 11 secs 
-
-Phase  8  : 0 unrouted; (Setup:948, Hold:0, Component Switching Limit:0)     REAL time: 4 mins 11 secs 
-
-Phase  9  : 0 unrouted; (Setup:948, Hold:0, Component Switching Limit:0)     REAL time: 4 mins 11 secs 
-
-Phase 10  : 0 unrouted; (Setup:579, Hold:0, Component Switching Limit:0)     REAL time: 4 mins 15 secs 
-Total REAL time to Router completion: 4 mins 15 secs 
-Total CPU time to Router completion: 4 mins 27 secs 
-
-Partition Implementation Status
--------------------------------
-
-  No Partitions were found in this design.
-
--------------------------------
-
-Generating "PAR" statistics.
-
-**************************
-Generating Clock Report
-**************************
-
-+---------------------+--------------+------+------+------------+-------------+
-|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
-+---------------------+--------------+------+------+------------+-------------+
-|cmp_gn4124_core/sys_ |              |      |      |            |             |
-|                 clk | BUFGMUX_X3Y13| No   |  680 |  0.807     |  2.177      |
-+---------------------+--------------+------+------+------------+-------------+
-|          l_clk_BUFG | BUFGMUX_X3Y15| No   |  345 |  0.347     |  1.714      |
-+---------------------+--------------+------+------+------------+-------------+
-|cmp_gn4124_core/cmp_ |              |      |      |            |             |
-|wbmaster32/_n0440_BU |              |      |      |            |             |
-|                  FG |  BUFGMUX_X2Y3| No   |    8 |  0.005     |  1.638      |
-+---------------------+--------------+------+------+------------+-------------+
-|cmp_gn4124_core/io_c |              |      |      |            |             |
-|                  lk |         Local|      |   41 |  0.043     |  2.143      |
-+---------------------+--------------+------+------+------------+-------------+
-
-* Net Skew is the difference between the minimum and maximum routing
-only delays for the net. Note this is different from Clock Skew which
-is reported in TRCE timing report. Clock Skew is the difference between
-the minimum and maximum path delays which includes logic delays.
-
-Timing Score: 579 (Setup: 579, Hold: 0, Component Switching Limit: 0)
-
-WARNING:Par:468 - Your design did not meet timing.  The following are some suggestions to assist you to meet timing in your design.
-
-   Review the timing report using Timing Analyzer (In ISE select "Post-Place &
-   Route Static Timing Report"). Go to the failing constraint(s) and evaluate the failing paths for each constraint.
-
-   Try the Design Goal and Strategies for Timing Performance(In ISE select Project -> Design Goals & Strategies) to ensure the best options
-   are set in the tools for timing closure.
-
-   Use the Xilinx "SmartXplorer" script to try special combinations of
-   options known to produce very good results.
-
-   Visit the Xilinx technical support web at http://support.xilinx.com and go to
-   either "Troubleshoot->Tech Tips->Timing & Constraints" or "
-   TechXclusives->Timing Closure" for tips and suggestions for meeting timing
-   in your design.
-
-Number of Timing Constraints that were not applied: 11
-
-Asterisk (*) preceding a constraint indicates it was not met.
-   This may be due to a setup or hold violation.
-
-----------------------------------------------------------------------------------------------------------
-  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing   
-                                            |             |    Slack   | Achievable | Errors |    Score   
-----------------------------------------------------------------------------------------------------------
-* TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x | SETUP       |    -0.579ns|     5.579ns|       1|         579
-  1_0 = PERIOD TIMEGRP         "cmp_gn4124_ | HOLD        |     0.274ns|            |       0|           0
-  core_cmp_clk_in_rx_pllout_x1_0"         T |             |            |            |        |            
-  S_cmp_gn4124_core_cmp_clk_in_buf_P_clk_0  |             |            |            |        |            
-  PHASE 1.25 ns HIGH 50%                    |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  TS_l_clkp = PERIOD TIMEGRP "l_clkp_grp" 5 | SETUP       |     0.205ns|     4.795ns|       0|           0
-   ns HIGH 50%                              | HOLD        |     0.382ns|            |       0|           0
-----------------------------------------------------------------------------------------------------------
-  TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x | MINPERIOD   |     1.430ns|     3.570ns|       0|           0
-  1 = PERIOD TIMEGRP         "cmp_gn4124_co |             |            |            |        |            
-  re_cmp_clk_in_rx_pllout_x1"         TS_cm |             |            |            |        |            
-  p_gn4124_core_cmp_clk_in_buf_P_clk PHASE  |             |            |            |        |            
-  1.25 ns HIGH 50%                          |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk_0 | MINLOWPULSE |     2.200ns|     2.800ns|       0|           0
-   = PERIOD TIMEGRP         "cmp_gn4124_cor |             |            |            |        |            
-  e_cmp_clk_in_buf_P_clk_0" TS_p2l_clkn HIG |             |            |            |        |            
-  H 50%                                     |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk = | MINLOWPULSE |     2.200ns|     2.800ns|       0|           0
-   PERIOD TIMEGRP         "cmp_gn4124_core_ |             |            |            |        |            
-  cmp_clk_in_buf_P_clk" TS_p2l_clkp HIGH 50 |             |            |            |        |            
-  %                                         |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  NET "P_RD_D_RDY_0_IBUF" MAXDELAY = 2 ns   | MAXDELAY    |     1.676ns|     0.324ns|       0|           0
-----------------------------------------------------------------------------------------------------------
-  NET "P_RD_D_RDY_1_IBUF" MAXDELAY = 2 ns   | MAXDELAY    |     1.676ns|     0.324ns|       0|           0
-----------------------------------------------------------------------------------------------------------
-  NET "L_WR_RDY_0_IBUF" MAXDELAY = 2 ns     | MAXDELAY    |     1.676ns|     0.324ns|       0|           0
-----------------------------------------------------------------------------------------------------------
-  NET "L_WR_RDY_1_IBUF" MAXDELAY = 2 ns     | MAXDELAY    |     1.676ns|     0.324ns|       0|           0
-----------------------------------------------------------------------------------------------------------
-  NET "L2P_RDY_IBUF" MAXDELAY = 2 ns        | MAXDELAY    |     1.676ns|     0.324ns|       0|           0
-----------------------------------------------------------------------------------------------------------
-  NET "VC_RDY<1>_IBUF" MAXDELAY = 2 ns      | MAXDELAY    |     2.000ns|     0.000ns|       0|           0
-----------------------------------------------------------------------------------------------------------
-  NET "VC_RDY<0>_IBUF" MAXDELAY = 2 ns      | MAXDELAY    |     2.000ns|     0.000ns|       0|           0
-----------------------------------------------------------------------------------------------------------
-  TS_p2l_clkp = PERIOD TIMEGRP "p2l_clkp_gr | MINPERIOD   |     3.096ns|     1.904ns|       0|           0
-  p" 5 ns HIGH 50%                          |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  TS_p2l_clkn = PERIOD TIMEGRP "p2l_clkn_gr | MINPERIOD   |     3.096ns|     1.904ns|       0|           0
-  p" 5 ns HIGH 50%                          |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  NET "VC_RDY<1>_IBUF" MAXDELAY = 2 ns      | N/A         |         N/A|         N/A|     N/A|         N/A
-----------------------------------------------------------------------------------------------------------
-  NET "VC_RDY<0>_IBUF" MAXDELAY = 2 ns      | N/A         |         N/A|         N/A|     N/A|         N/A
-----------------------------------------------------------------------------------------------------------
-  NET "L_WR_RDY_0_IBUF" MAXDELAY = 2 ns     | N/A         |         N/A|         N/A|     N/A|         N/A
-----------------------------------------------------------------------------------------------------------
-  TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x | N/A         |         N/A|         N/A|     N/A|         N/A
-  s_int = PERIOD TIMEGRP         "cmp_gn412 |             |            |            |        |            
-  4_core_cmp_clk_in_rx_pllout_xs_int"       |             |            |            |        |            
-     TS_cmp_gn4124_core_cmp_clk_in_buf_P_cl |             |            |            |        |            
-  k / 2 HIGH 50%                            |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  NET "L_WR_RDY_1_IBUF" MAXDELAY = 2 ns     | N/A         |         N/A|         N/A|     N/A|         N/A
-----------------------------------------------------------------------------------------------------------
-  TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x | N/A         |         N/A|         N/A|     N/A|         N/A
-  s_int_0 = PERIOD TIMEGRP         "cmp_gn4 |             |            |            |        |            
-  124_core_cmp_clk_in_rx_pllout_xs_int_0"   |             |            |            |        |            
-         TS_cmp_gn4124_core_cmp_clk_in_buf_ |             |            |            |        |            
-  P_clk_0 / 2 HIGH 50%                      |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-
-
-Derived Constraint Report
-Review Timing Report for more details on the following derived constraints.
-To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
-or "Run Timing Analysis" from Timing Analyzer (timingan).
-Derived Constraints for TS_p2l_clkp
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
-|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
-|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-|TS_p2l_clkp                    |      5.000ns|      1.904ns|      3.570ns|            0|            0|            0|            0|
-| TS_cmp_gn4124_core_cmp_clk_in_|      5.000ns|      2.800ns|      3.570ns|            0|            0|            0|            0|
-| buf_P_clk                     |             |             |             |             |             |             |             |
-|  TS_cmp_gn4124_core_cmp_clk_in|      2.500ns|          N/A|          N/A|            0|            0|            0|            0|
-|  _rx_pllout_xs_int            |             |             |             |             |             |             |             |
-|  TS_cmp_gn4124_core_cmp_clk_in|      5.000ns|      3.570ns|          N/A|            0|            0|            0|            0|
-|  _rx_pllout_x1                |             |             |             |             |             |             |             |
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-
-Derived Constraints for TS_p2l_clkn
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
-|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
-|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-|TS_p2l_clkn                    |      5.000ns|      1.904ns|      5.579ns|            0|            1|            0|        29021|
-| TS_cmp_gn4124_core_cmp_clk_in_|      5.000ns|      2.800ns|      5.579ns|            0|            1|            0|        29021|
-| buf_P_clk_0                   |             |             |             |             |             |             |             |
-|  TS_cmp_gn4124_core_cmp_clk_in|      2.500ns|          N/A|          N/A|            0|            0|            0|            0|
-|  _rx_pllout_xs_int_0          |             |             |             |             |             |             |             |
-|  TS_cmp_gn4124_core_cmp_clk_in|      5.000ns|      5.579ns|          N/A|            1|            0|        29021|            0|
-|  _rx_pllout_x1_0              |             |             |             |             |             |             |             |
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-
-1 constraint not met.
-INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the 
-   constraint is not analyzed due to the following: No paths covered by this 
-   constraint; Other constraints intersect with this constraint; or This 
-   constraint was disabled by a Path Tracing Control. Please run the Timespec 
-   Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
-
-
-Generating Pad Report.
-
-All signals are completely routed.
-
-WARNING:Par:283 - There are 6 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
-
-Total REAL time to PAR completion: 4 mins 21 secs 
-Total CPU time to PAR completion: 4 mins 33 secs 
-
-Peak Memory Usage:  412 MB
-
-Placer: Placement generated during map.
-Routing: Completed - No errors found.
-Timing: Completed - 1 errors found.
-
-Number of error messages: 0
-Number of warning messages: 13
-Number of info messages: 1
-
-Writing design to file pfc_wrapper.ncd
-
-
-
-PAR done!
diff --git a/hdl/pfc/ise_project/pfc_wrapper.syr b/hdl/pfc/ise_project/pfc_wrapper.syr
deleted file mode 100644
index 120a6568e13d87849a71c36f000433371ba66547..0000000000000000000000000000000000000000
--- a/hdl/pfc/ise_project/pfc_wrapper.syr
+++ /dev/null
@@ -1,2070 +0,0 @@
-Release 12.2 - xst M.63c (lin)
-Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
---> 
-Parameter TMPDIR set to xst/projnav.tmp
-
-
-Total REAL time to Xst completion: 0.00 secs
-Total CPU time to Xst completion: 0.14 secs
- 
---> 
-Parameter xsthdpdir set to xst
-
-
-Total REAL time to Xst completion: 0.00 secs
-Total CPU time to Xst completion: 0.14 secs
- 
---> 
-Reading design: pfc_wrapper.prj
-
-TABLE OF CONTENTS
-  1) Synthesis Options Summary
-  2) HDL Parsing
-  3) HDL Elaboration
-  4) HDL Synthesis
-       4.1) HDL Synthesis Report
-  5) Advanced HDL Synthesis
-       5.1) Advanced HDL Synthesis Report
-  6) Low Level Synthesis
-  7) Partition Report
-  8) Design Summary
-       8.1) Primitive and Black Box Usage
-       8.2) Device utilization summary
-       8.3) Partition Resource Summary
-       8.4) Timing Report
-            8.4.1) Clock Information
-            8.4.2) Asynchronous Control Signals Information
-            8.4.3) Timing Summary
-            8.4.4) Timing Details
-
-
-=========================================================================
-*                      Synthesis Options Summary                        *
-=========================================================================
----- Source Parameters
-Input File Name                    : "pfc_wrapper.prj"
-Input Format                       : mixed
-Ignore Synthesis Constraint File   : NO
-
----- Target Parameters
-Output File Name                   : "pfc_wrapper"
-Output Format                      : NGC
-Target Device                      : xc6slx150t-3-fgg676
-
----- Source Options
-Top Module Name                    : pfc_wrapper
-Automatic FSM Extraction           : YES
-FSM Encoding Algorithm             : Auto
-Safe Implementation                : No
-FSM Style                          : LUT
-RAM Extraction                     : Yes
-RAM Style                          : Auto
-ROM Extraction                     : Yes
-Shift Register Extraction          : YES
-ROM Style                          : Auto
-Resource Sharing                   : YES
-Asynchronous To Synchronous        : NO
-Shift Register Minimum Size        : 2
-Use DSP Block                      : Auto
-Automatic Register Balancing       : No
-
----- Target Options
-LUT Combining                      : Auto
-Reduce Control Sets                : Auto
-Add IO Buffers                     : YES
-Global Maximum Fanout              : 100000
-Add Generic Clock Buffer(BUFG)     : 16
-Register Duplication               : YES
-Optimize Instantiated Primitives   : NO
-Use Clock Enable                   : Auto
-Use Synchronous Set                : Auto
-Use Synchronous Reset              : Auto
-Pack IO Registers into IOBs        : Auto
-Equivalent register Removal        : YES
-
----- General Options
-Optimization Goal                  : Speed
-Optimization Effort                : 1
-Power Reduction                    : NO
-Keep Hierarchy                     : No
-Netlist Hierarchy                  : As_Optimized
-RTL Output                         : Yes
-Global Optimization                : AllClockNets
-Read Cores                         : YES
-Write Timing Constraints           : NO
-Cross Clock Analysis               : NO
-Hierarchy Separator                : /
-Bus Delimiter                      : <>
-Case Specifier                     : Maintain
-Slice Utilization Ratio            : 100
-BRAM Utilization Ratio             : 100
-DSP48 Utilization Ratio            : 100
-Auto BRAM Packing                  : NO
-Slice Utilization Ratio Delta      : 5
-
----- Other Options
-Cores Search Directories           : {"../ip_cores"  }
-
-=========================================================================
-
-
-=========================================================================
-*                          HDL Parsing                                  *
-=========================================================================
-Parsing VHDL file "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../ip_cores/fifo_32x512.vhd" into library work
-Parsing entity <fifo_32x512>.
-Parsing architecture <fifo_32x512_a> of entity <fifo_32x512>.
-Parsing VHDL file "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/serdes_n_to_1_s2_se.vhd" into library work
-Parsing entity <serdes_n_to_1_s2_se>.
-Parsing architecture <arch_serdes_n_to_1_s2_se> of entity <serdes_n_to_1_s2_se>.
-Parsing VHDL file "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/serdes_n_to_1_s2_diff.vhd" into library work
-Parsing entity <serdes_n_to_1_s2_diff>.
-Parsing architecture <arch_serdes_n_to_1_s2_diff> of entity <serdes_n_to_1_s2_diff>.
-Parsing VHDL file "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/serdes_1_to_n_data_s2_se.vhd" into library work
-Parsing entity <serdes_1_to_n_data_s2_se>.
-Parsing architecture <arch_serdes_1_to_n_data_s2_se> of entity <serdes_1_to_n_data_s2_se>.
-Parsing VHDL file "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/gn4124_core_pkg_s6.vhd" into library work
-Parsing package <gn4124_core_pkg>.
-Parsing package body <gn4124_core_pkg>.
-Parsing VHDL file "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/dma_controller_wb_slave.vhd" into library work
-Parsing entity <dma_controller_wb_slave>.
-Parsing architecture <syn> of entity <dma_controller_wb_slave>.
-Parsing VHDL file "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/wbmaster32.vhd" into library work
-Parsing entity <wbmaster32>.
-Parsing architecture <behaviour> of entity <wbmaster32>.
-Parsing VHDL file "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/serdes_1_to_n_clk_pll_s2_diff.vhd" into library work
-Parsing entity <serdes_1_to_n_clk_pll_s2_diff>.
-Parsing architecture <arch_serdes_1_to_n_clk_pll_s2_diff> of entity <serdes_1_to_n_clk_pll_s2_diff>.
-Parsing VHDL file "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/p2l_dma_master.vhd" into library work
-Parsing entity <p2l_dma_master>.
-Parsing architecture <behaviour> of entity <p2l_dma_master>.
-Parsing VHDL file "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/p2l_des_s6.vhd" into library work
-Parsing entity <p2l_des>.
-Parsing architecture <rtl> of entity <p2l_des>.
-Parsing VHDL file "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/p2l_decode32.vhd" into library work
-Parsing entity <p2l_decode32>.
-Parsing architecture <rtl> of entity <p2l_decode32>.
-Parsing VHDL file "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/l2p_ser_s6.vhd" into library work
-Parsing entity <l2p_ser>.
-Parsing architecture <rtl> of entity <l2p_ser>.
-Parsing VHDL file "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/l2p_dma_master.vhd" into library work
-Parsing entity <l2p_dma_master>.
-Parsing architecture <behaviour> of entity <l2p_dma_master>.
-Parsing VHDL file "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/l2p_arbiter.vhd" into library work
-Parsing entity <l2p_arbiter>.
-Parsing architecture <rtl> of entity <l2p_arbiter>.
-Parsing VHDL file "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/dma_controller.vhd" into library work
-Parsing entity <dma_controller>.
-Parsing architecture <behaviour> of entity <dma_controller>.
-Parsing VHDL file "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../ip_cores/ram_2048x32.vhd" into library work
-Parsing entity <ram_2048x32>.
-Parsing architecture <ram_2048x32_a> of entity <ram_2048x32>.
-Parsing VHDL file "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/gn4124_core_s6.vhd" into library work
-Parsing entity <gn4124_core>.
-Parsing architecture <rtl> of entity <gn4124_core>.
-Parsing VHDL file "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/dummy_stat_regs.vhd" into library work
-Parsing entity <dummy_stat_regs_wb_slave>.
-Parsing architecture <syn> of entity <dummy_stat_regs_wb_slave>.
-Parsing VHDL file "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/dummy_ctrl_regs.vhd" into library work
-Parsing entity <dummy_ctrl_regs_wb_slave>.
-Parsing architecture <syn> of entity <dummy_ctrl_regs_wb_slave>.
-Parsing VHDL file "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../rtl/pfc_wrapper.vhd" into library work
-Parsing entity <pfc_wrapper>.
-Parsing architecture <rtl> of entity <pfc_wrapper>.
-
-=========================================================================
-*                            HDL Elaboration                            *
-=========================================================================
-
-Elaborating entity <pfc_wrapper> (architecture <rtl>) with generics from library <work>.
-
-Elaborating entity <gn4124_core> (architecture <rtl>) with generics from library <work>.
-
-Elaborating entity <serdes_1_to_n_clk_pll_s2_diff> (architecture <arch_serdes_1_to_n_clk_pll_s2_diff>) with generics from library <work>.
-
-Elaborating entity <p2l_des> (architecture <rtl>) from library <work>.
-WARNING:HDLCompiler:1127 - "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/p2l_des_s6.vhd" Line 143: Assignment to p2l_data_bitslip_p ignored, since the identifier is never used
-
-Elaborating entity <serdes_1_to_n_data_s2_se> (architecture <arch_serdes_1_to_n_data_s2_se>) with generics from library <work>.
-WARNING:HDLCompiler:634 - "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/serdes_1_to_n_data_s2_se.vhd" Line 97: Net <busys[15]> does not have a driver.
-WARNING:HDLCompiler:634 - "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/serdes_1_to_n_data_s2_se.vhd" Line 111: Net <valid_data[15]> does not have a driver.
-WARNING:HDLCompiler:634 - "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/serdes_1_to_n_data_s2_se.vhd" Line 119: Net <incdec_data[15]> does not have a driver.
-
-Elaborating entity <serdes_1_to_n_data_s2_se> (architecture <arch_serdes_1_to_n_data_s2_se>) with generics from library <work>.
-
-Elaborating entity <p2l_decode32> (architecture <rtl>) from library <work>.
-
-Elaborating entity <wbmaster32> (architecture <behaviour>) with generics from library <work>.
-INFO:HDLCompiler:679 - Case statement is complete. Others clause is never selected and therefore discarded.
-WARNING:HDLCompiler:89 - "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/gn4124_core_pkg_s6.vhd" Line 461: <fifo_64x512> remains a black-box since it has no binding entity.
-
-Elaborating entity <fifo_32x512> (architecture <fifo_32x512_a>) from library <work>.
-INFO:HDLCompiler:679 - Case statement is complete. Others clause is never selected and therefore discarded.
-
-Elaborating entity <dma_controller> (architecture <behaviour>) from library <work>.
-
-Elaborating entity <dma_controller_wb_slave> (architecture <syn>) from library <work>.
-WARNING:HDLCompiler:1127 - "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/dma_controller_wb_slave.vhd" Line 167: Assignment to bwsel_reg ignored, since the identifier is never used
-WARNING:HDLCompiler:1127 - "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/dma_controller_wb_slave.vhd" Line 168: Assignment to bus_clock_int ignored, since the identifier is never used
-WARNING:HDLCompiler:1127 - "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/dma_controller_wb_slave.vhd" Line 169: Assignment to rd_int ignored, since the identifier is never used
-WARNING:HDLCompiler:1127 - "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/dma_controller_wb_slave.vhd" Line 170: Assignment to wr_int ignored, since the identifier is never used
-WARNING:HDLCompiler:1127 - "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/dma_controller_wb_slave.vhd" Line 171: Assignment to allones ignored, since the identifier is never used
-WARNING:HDLCompiler:1127 - "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/dma_controller_wb_slave.vhd" Line 172: Assignment to allzeros ignored, since the identifier is never used
-INFO:HDLCompiler:679 - Case statement is complete. Others clause is never selected and therefore discarded.
-
-Elaborating entity <l2p_dma_master> (architecture <behaviour>) with generics from library <work>.
-INFO:HDLCompiler:679 - Case statement is complete. Others clause is never selected and therefore discarded.
-
-Elaborating entity <p2l_dma_master> (architecture <behaviour>) with generics from library <work>.
-INFO:HDLCompiler:679 - Case statement is complete. Others clause is never selected and therefore discarded.
-
-Elaborating entity <l2p_arbiter> (architecture <rtl>) from library <work>.
-
-Elaborating entity <l2p_ser> (architecture <rtl>) from library <work>.
-
-Elaborating entity <serdes_n_to_1_s2_diff> (architecture <arch_serdes_n_to_1_s2_diff>) with generics from library <work>.
-WARNING:HDLCompiler:634 - "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/serdes_n_to_1_s2_diff.vhd" Line 93: Net <mdatainb[3]> does not have a driver.
-
-Elaborating entity <serdes_n_to_1_s2_se> (architecture <arch_serdes_n_to_1_s2_se>) with generics from library <work>.
-WARNING:HDLCompiler:634 - "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/serdes_n_to_1_s2_se.vhd" Line 92: Net <mdatainb[63]> does not have a driver.
-
-Elaborating entity <serdes_n_to_1_s2_se> (architecture <arch_serdes_n_to_1_s2_se>) with generics from library <work>.
-
-Elaborating entity <dummy_stat_regs_wb_slave> (architecture <syn>) from library <work>.
-WARNING:HDLCompiler:1127 - "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/dummy_stat_regs.vhd" Line 56: Assignment to wrdata_reg ignored, since the identifier is never used
-WARNING:HDLCompiler:1127 - "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/dummy_stat_regs.vhd" Line 57: Assignment to bwsel_reg ignored, since the identifier is never used
-WARNING:HDLCompiler:1127 - "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/dummy_stat_regs.vhd" Line 59: Assignment to rd_int ignored, since the identifier is never used
-WARNING:HDLCompiler:1127 - "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/dummy_stat_regs.vhd" Line 60: Assignment to wr_int ignored, since the identifier is never used
-WARNING:HDLCompiler:1127 - "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/dummy_stat_regs.vhd" Line 61: Assignment to allones ignored, since the identifier is never used
-WARNING:HDLCompiler:1127 - "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/dummy_stat_regs.vhd" Line 62: Assignment to allzeros ignored, since the identifier is never used
-INFO:HDLCompiler:679 - Case statement is complete. Others clause is never selected and therefore discarded.
-
-Elaborating entity <dummy_ctrl_regs_wb_slave> (architecture <syn>) from library <work>.
-WARNING:HDLCompiler:1127 - "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/dummy_ctrl_regs.vhd" Line 61: Assignment to bwsel_reg ignored, since the identifier is never used
-WARNING:HDLCompiler:1127 - "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/dummy_ctrl_regs.vhd" Line 63: Assignment to rd_int ignored, since the identifier is never used
-WARNING:HDLCompiler:1127 - "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/dummy_ctrl_regs.vhd" Line 64: Assignment to wr_int ignored, since the identifier is never used
-WARNING:HDLCompiler:1127 - "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/dummy_ctrl_regs.vhd" Line 65: Assignment to allones ignored, since the identifier is never used
-WARNING:HDLCompiler:1127 - "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/dummy_ctrl_regs.vhd" Line 66: Assignment to allzeros ignored, since the identifier is never used
-INFO:HDLCompiler:679 - Case statement is complete. Others clause is never selected and therefore discarded.
-
-Elaborating entity <ram_2048x32> (architecture <ram_2048x32_a>) from library <work>.
-
-=========================================================================
-*                           HDL Synthesis                               *
-=========================================================================
-
-Synthesizing Unit <pfc_wrapper>.
-    Related source file is "/home/mcattin/projects/GN4124_core/hdl/pfc/rtl/pfc_wrapper.vhd".
-        TAR_ADDR_WDTH = 13
-INFO:Xst:3010 - "/home/mcattin/projects/GN4124_core/hdl/pfc/rtl/pfc_wrapper.vhd" line 334: Output port <debug_o> of the instance <cmp_gn4124_core> is unconnected or connected to loadless signal.
-INFO:Xst:3010 - "/home/mcattin/projects/GN4124_core/hdl/pfc/rtl/pfc_wrapper.vhd" line 334: Output port <dma_sel_o> of the instance <cmp_gn4124_core> is unconnected or connected to loadless signal.
-INFO:Xst:3010 - "/home/mcattin/projects/GN4124_core/hdl/pfc/rtl/pfc_wrapper.vhd" line 447: Output port <dummy_reg_1_o> of the instance <cmp_dummy_ctrl_regs> is unconnected or connected to loadless signal.
-INFO:Xst:3010 - "/home/mcattin/projects/GN4124_core/hdl/pfc/rtl/pfc_wrapper.vhd" line 447: Output port <dummy_reg_2_o> of the instance <cmp_dummy_ctrl_regs> is unconnected or connected to loadless signal.
-INFO:Xst:3010 - "/home/mcattin/projects/GN4124_core/hdl/pfc/rtl/pfc_wrapper.vhd" line 447: Output port <dummy_reg_3_o> of the instance <cmp_dummy_ctrl_regs> is unconnected or connected to loadless signal.
-    Found 1-bit register for signal <USER_IO_0_P>.
-    Found 1-bit register for signal <dma_ack_i>.
-    Found 4-bit register for signal <clk_div_cnt>.
-    Found 4-bit adder for signal <clk_div_cnt[3]_GND_6_o_add_5_OUT> created at line 1241.
-    Summary:
-	inferred   1 Adder/Subtractor(s).
-	inferred   6 D-type flip-flop(s).
-	inferred   1 Multiplexer(s).
-Unit <pfc_wrapper> synthesized.
-
-Synthesizing Unit <gn4124_core>.
-    Related source file is "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/gn4124_core_s6.vhd".
-        g_IS_SPARTAN6 = true
-        g_BAR0_APERTURE = 20
-        g_CSR_WB_SLAVES_NB = 2
-        g_DMA_WB_SLAVES_NB = 1
-        g_DMA_WB_ADDR_WIDTH = 26
-WARNING:Xst:647 - Input <p_wr_req_i<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <vc_rdy_i<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <tx_error_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-INFO:Xst:3010 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/gn4124_core_s6.vhd" line 338: Output port <datain> of the instance <cmp_clk_in> is unconnected or connected to loadless signal.
-INFO:Xst:3010 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/gn4124_core_s6.vhd" line 338: Output port <rx_pll_lckd> of the instance <cmp_clk_in> is unconnected or connected to loadless signal.
-INFO:Xst:3010 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/gn4124_core_s6.vhd" line 338: Output port <rx_pllout_xs> of the instance <cmp_clk_in> is unconnected or connected to loadless signal.
-INFO:Xst:3010 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/gn4124_core_s6.vhd" line 338: Output port <bitslip> of the instance <cmp_clk_in> is unconnected or connected to loadless signal.
-INFO:Xst:3010 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/gn4124_core_s6.vhd" line 423: Output port <p2l_hdr_stat_o> of the instance <cmp_p2l_decode32> is unconnected or connected to loadless signal.
-INFO:Xst:3010 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/gn4124_core_s6.vhd" line 423: Output port <p2l_hdr_last_o> of the instance <cmp_p2l_decode32> is unconnected or connected to loadless signal.
-    Found 2-bit register for signal <l_wr_rdy_t>.
-    Found 2-bit register for signal <l_wr_rdy_t2>.
-    Found 2-bit register for signal <l_wr_rdy>.
-    Found 2-bit register for signal <p_rd_d_rdy_t>.
-    Found 2-bit register for signal <p_rd_d_rdy_t2>.
-    Found 2-bit register for signal <p_rd_d_rdy>.
-    Found 1-bit register for signal <rst_reg>.
-    Found 1-bit register for signal <l2p_rdy_t>.
-    Found 1-bit register for signal <l2p_rdy_t2>.
-    Found 1-bit register for signal <l2p_rdy>.
-    Found 1-bit register for signal <l2p_edb_o>.
-    Found 1-bit register for signal <l2p_edb_t>.
-    Found 1-bit register for signal <l2p_edb_t2>.
-    Summary:
-	inferred  19 D-type flip-flop(s).
-	inferred  12 Multiplexer(s).
-Unit <gn4124_core> synthesized.
-
-Synthesizing Unit <serdes_1_to_n_clk_pll_s2_diff>.
-    Related source file is "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/serdes_1_to_n_clk_pll_s2_diff.vhd".
-        PLLD = 1
-        PLLX = 2
-        CLKIN_PERIOD = 5.0
-        S = 2
-        BS = false
-        DIFF_TERM = false
-WARNING:Xst:647 - Input <pattern1<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <pattern2<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-    Found 1-bit register for signal <enable>.
-    Found 1-bit register for signal <cal_clk>.
-    Found 1-bit register for signal <rst_clk>.
-    Found 1-bit register for signal <bslip>.
-    Found 12-bit register for signal <counter>.
-    Found 3-bit register for signal <count>.
-    Found 4-bit register for signal <state>.
-    Found 1-bit register for signal <busyd>.
-    Found finite state machine <FSM_0> for signal <state>.
-    -----------------------------------------------------------------------
-    | States             | 9                                              |
-    | Transitions        | 24                                             |
-    | Inputs             | 4                                              |
-    | Outputs            | 9                                              |
-    | Clock              | rx_bufg_pll_x1_int (rising_edge)               |
-    | Reset              | not_rx_bufpll_lckd (positive)                  |
-    | Reset type         | asynchronous                                   |
-    | Reset State        | 0000                                           |
-    | Power Up State     | 0000                                           |
-    | Encoding           | auto                                           |
-    | Implementation     | LUT                                            |
-    -----------------------------------------------------------------------
-    Found 12-bit adder for signal <counter[11]_GND_10_o_add_1_OUT> created at line 176.
-    Found 3-bit adder for signal <count[2]_GND_10_o_add_14_OUT> created at line 205.
-    Summary:
-	inferred   2 Adder/Subtractor(s).
-	inferred  19 D-type flip-flop(s).
-	inferred   4 Multiplexer(s).
-	inferred   1 Finite State Machine(s).
-Unit <serdes_1_to_n_clk_pll_s2_diff> synthesized.
-
-Synthesizing Unit <p2l_des>.
-    Related source file is "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/p2l_des_s6.vhd".
-INFO:Xst:3010 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/p2l_des_s6.vhd" line 148: Output port <debug> of the instance <cmp_data_in> is unconnected or connected to loadless signal.
-INFO:Xst:3010 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/p2l_des_s6.vhd" line 168: Output port <debug> of the instance <cmp_dframe_in> is unconnected or connected to loadless signal.
-INFO:Xst:3010 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/p2l_des_s6.vhd" line 191: Output port <debug> of the instance <cmp_valid_in> is unconnected or connected to loadless signal.
-    Found 32-bit register for signal <p2l_data_o>.
-    Found 32-bit register for signal <p2l_data_t2>.
-    Found 1-bit register for signal <p2l_dframe_o>.
-    Found 1-bit register for signal <p2l_valid_o>.
-    Found 1-bit register for signal <p2l_dframe_t2>.
-    Found 1-bit register for signal <p2l_valid_t2>.
-    Summary:
-	inferred  68 D-type flip-flop(s).
-Unit <p2l_des> synthesized.
-
-Synthesizing Unit <serdes_1_to_n_data_s2_se_1>.
-    Related source file is "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/serdes_1_to_n_data_s2_se.vhd".
-        USE_PD = false
-        S = 2
-        D = 16
-WARNING:Xst:653 - Signal <busys> is used but never assigned. This sourceless signal will be automatically connected to value GND.
-WARNING:Xst:653 - Signal <valid_data> is used but never assigned. This sourceless signal will be automatically connected to value GND.
-WARNING:Xst:653 - Signal <incdec_data> is used but never assigned. This sourceless signal will be automatically connected to value GND.
-    Found 9-bit register for signal <counter>.
-    Found 4-bit register for signal <state>.
-    Found 16-bit register for signal <mux>.
-    Found 1-bit register for signal <cal_data_master>.
-    Found 1-bit register for signal <cal_data_sint>.
-    Found 1-bit register for signal <enable>.
-    Found 1-bit register for signal <rst_data>.
-    Found 1-bit register for signal <busy_data_d>.
-    Found 16-bit register for signal <ce_data>.
-    Found 1-bit register for signal <inc_data_int>.
-    Found finite state machine <FSM_1> for signal <state>.
-    -----------------------------------------------------------------------
-    | States             | 8                                              |
-    | Transitions        | 17                                             |
-    | Inputs             | 3                                              |
-    | Outputs            | 7                                              |
-    | Clock              | gclk (rising_edge)                             |
-    | Reset              | reset (positive)                               |
-    | Reset type         | asynchronous                                   |
-    | Reset State        | 0000                                           |
-    | Power Up State     | 0000                                           |
-    | Encoding           | auto                                           |
-    | Implementation     | LUT                                            |
-    -----------------------------------------------------------------------
-    Found 9-bit adder for signal <counter[8]_GND_55_o_add_2_OUT> created at line 150.
-    Summary:
-	inferred   1 Adder/Subtractor(s).
-	inferred  47 D-type flip-flop(s).
-	inferred   3 Multiplexer(s).
-	inferred   1 Finite State Machine(s).
-Unit <serdes_1_to_n_data_s2_se_1> synthesized.
-
-Synthesizing Unit <serdes_1_to_n_data_s2_se_2>.
-    Related source file is "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/serdes_1_to_n_data_s2_se.vhd".
-        USE_PD = false
-        S = 2
-        D = 1
-WARNING:Xst:653 - Signal <busys> is used but never assigned. This sourceless signal will be automatically connected to value GND.
-WARNING:Xst:653 - Signal <valid_data> is used but never assigned. This sourceless signal will be automatically connected to value GND.
-WARNING:Xst:653 - Signal <incdec_data> is used but never assigned. This sourceless signal will be automatically connected to value GND.
-    Found 9-bit register for signal <counter>.
-    Found 5-bit register for signal <pdcounter>.
-    Found 4-bit register for signal <state>.
-    Found 1-bit register for signal <cal_data_master>.
-    Found 1-bit register for signal <cal_data_sint>.
-    Found 1-bit register for signal <enable>.
-    Found 1-bit register for signal <ce_data_inta>.
-    Found 1-bit register for signal <flag>.
-    Found 1-bit register for signal <rst_data>.
-    Found 1-bit register for signal <busy_data_d>.
-    Found 1-bit register for signal <incdec_data_d>.
-    Found 1-bit register for signal <valid_data_d>.
-    Found 1-bit register for signal <ce_data>.
-    Found 1-bit register for signal <inc_data_int>.
-    Found finite state machine <FSM_2> for signal <state>.
-    -----------------------------------------------------------------------
-    | States             | 8                                              |
-    | Transitions        | 17                                             |
-    | Inputs             | 3                                              |
-    | Outputs            | 9                                              |
-    | Clock              | gclk (rising_edge)                             |
-    | Reset              | reset (positive)                               |
-    | Reset type         | asynchronous                                   |
-    | Reset State        | 0000                                           |
-    | Power Up State     | 0000                                           |
-    | Encoding           | auto                                           |
-    | Implementation     | LUT                                            |
-    -----------------------------------------------------------------------
-    Found 9-bit adder for signal <counter[8]_GND_125_o_add_1_OUT> created at line 150.
-    Found 5-bit adder for signal <pdcounter[4]_GND_125_o_add_34_OUT> created at line 242.
-    Found 5-bit subtractor for signal <GND_125_o_GND_125_o_sub_37_OUT<4:0>>.
-    Summary:
-	inferred   2 Adder/Subtractor(s).
-	inferred  24 D-type flip-flop(s).
-	inferred   9 Multiplexer(s).
-	inferred   1 Finite State Machine(s).
-Unit <serdes_1_to_n_data_s2_se_2> synthesized.
-
-Synthesizing Unit <p2l_decode32>.
-    Related source file is "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/p2l_decode32.vhd".
-    Found 10-bit register for signal <p2l_hdr_length>.
-    Found 2-bit register for signal <p2l_hdr_cid>.
-    Found 2-bit register for signal <p2l_hdr_stat>.
-    Found 4-bit register for signal <p2l_hdr_fbe>.
-    Found 4-bit register for signal <p2l_hdr_lbe>.
-    Found 4-bit register for signal <p2l_be>.
-    Found 32-bit register for signal <p2l_addr>.
-    Found 32-bit register for signal <p2l_d>.
-    Found 1-bit register for signal <des_p2l_valid_d>.
-    Found 1-bit register for signal <target_mrd>.
-    Found 1-bit register for signal <target_mwr>.
-    Found 1-bit register for signal <master_cpld>.
-    Found 1-bit register for signal <master_cpln>.
-    Found 1-bit register for signal <p2l_hdr_strobe>.
-    Found 1-bit register for signal <p2l_hdr_last>.
-    Found 1-bit register for signal <p2l_addr_cycle>.
-    Found 1-bit register for signal <p2l_addr_start>.
-    Found 1-bit register for signal <p2l_data_cycle>.
-    Found 1-bit register for signal <p2l_d_valid>.
-    Found 1-bit register for signal <p2l_d_last>.
-    Found 1-bit register for signal <des_p2l_dframe_d>.
-    Found 30-bit adder for signal <p2l_addr[31]_GND_140_o_add_17_OUT> created at line 1241.
-    Summary:
-	inferred   1 Adder/Subtractor(s).
-	inferred 103 D-type flip-flop(s).
-	inferred  38 Multiplexer(s).
-Unit <p2l_decode32> synthesized.
-
-Synthesizing Unit <wbmaster32>.
-    Related source file is "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/wbmaster32.vhd".
-        g_BAR0_APERTURE = 20
-        g_WB_SLAVES_NB = 3
-WARNING:Xst:647 - Input <pd_wbm_hdr_length_i<9:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <pd_wbm_addr_i<0:30>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <pd_wbm_be_i<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <pd_wbm_data_last_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-INFO:Xst:3010 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/wbmaster32.vhd" line 302: Output port <full> of the instance <cmp_fifo_to_wb> is unconnected or connected to loadless signal.
-INFO:Xst:3010 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/wbmaster32.vhd" line 302: Output port <valid> of the instance <cmp_fifo_to_wb> is unconnected or connected to loadless signal.
-INFO:Xst:3010 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/wbmaster32.vhd" line 323: Output port <full> of the instance <cmp_from_wb_fifo> is unconnected or connected to loadless signal.
-INFO:Xst:3010 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/wbmaster32.vhd" line 323: Output port <valid> of the instance <cmp_from_wb_fifo> is unconnected or connected to loadless signal.
-INFO:Xst:3010 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/wbmaster32.vhd" line 323: Output port <prog_full> of the instance <cmp_from_wb_fifo> is unconnected or connected to loadless signal.
-    Found 1-bit register for signal <to_wb_fifo_wr>.
-    Found 1-bit register for signal <wbm_arb_req_o>.
-    Found 1-bit register for signal <wbm_arb_valid_o>.
-    Found 1-bit register for signal <wbm_arb_dframe_o>.
-    Found 1-bit register for signal <from_wb_fifo_rd>.
-    Found 1-bit register for signal <to_wb_fifo_rd>.
-    Found 1-bit register for signal <wb_cyc_t>.
-    Found 1-bit register for signal <wb_stb_t>.
-    Found 1-bit register for signal <wb_we_t>.
-    Found 1-bit register for signal <from_wb_fifo_wr>.
-    Found 1-bit register for signal <wb_ack_t>.
-    Found 2-bit register for signal <p2l_cid>.
-    Found 2-bit register for signal <l2p_read_cpl_current_state>.
-    Found 2-bit register for signal <wishbone_current_state>.
-    Found 2-bit register for signal <wb_periph_addr>.
-    Found 32-bit register for signal <wbm_arb_data_o>.
-    Found 32-bit register for signal <wb_dat_o_t>.
-    Found 32-bit register for signal <from_wb_fifo_din>.
-    Found 32-bit register for signal <wb_dat_i_t>.
-    Found 4-bit register for signal <wb_sel_t>.
-    Found 31-bit register for signal <wb_adr_t>.
-    Found 64-bit register for signal <to_wb_fifo_din>.
-    Found finite state machine <FSM_3> for signal <l2p_read_cpl_current_state>.
-    -----------------------------------------------------------------------
-    | States             | 3                                              |
-    | Transitions        | 6                                              |
-    | Inputs             | 3                                              |
-    | Outputs            | 5                                              |
-    | Clock              | clk_i (rising_edge)                            |
-    | Reset              | rst_n_i (negative)                             |
-    | Reset type         | asynchronous                                   |
-    | Reset State        | l2p_idle                                       |
-    | Power Up State     | l2p_idle                                       |
-    | Encoding           | auto                                           |
-    | Implementation     | LUT                                            |
-    -----------------------------------------------------------------------
-    Found finite state machine <FSM_4> for signal <wishbone_current_state>.
-    -----------------------------------------------------------------------
-    | States             | 4                                              |
-    | Transitions        | 6                                              |
-    | Inputs             | 2                                              |
-    | Outputs            | 10                                             |
-    | Clock              | wb_clk_i (rising_edge)                         |
-    | Reset              | rst_n_i (negative)                             |
-    | Reset type         | asynchronous                                   |
-    | Reset State        | wb_idle                                        |
-    | Power Up State     | wb_idle                                        |
-    | Encoding           | auto                                           |
-    | Implementation     | LUT                                            |
-    -----------------------------------------------------------------------
-    Found 2-bit adder for signal <s_wb_periph_addr[1]_GND_141_o_add_39_OUT> created at line 439.
-    Found 8-bit adder for signal <n0264> created at line 477.
-    Found 32-bit 3-to-1 multiplexer for signal <l2p_read_cpl_current_state[1]_X_16_o_wide_mux_11_OUT> created at line 256.
-    Found 1-bit 3-to-1 multiplexer for signal <wb_periph_addr[1]_X_16_o_Mux_46_o> created at line 466.
-    Found 1-bit 3-to-1 multiplexer for signal <_n0304> created at line 477.
-    Found 1-bit 3-to-1 multiplexer for signal <_n0323> created at line 477.
-    Found 1-bit 3-to-1 multiplexer for signal <_n0343> created at line 477.
-    Found 1-bit 3-to-1 multiplexer for signal <_n0362> created at line 477.
-    Found 1-bit 3-to-1 multiplexer for signal <_n0381> created at line 477.
-    Found 1-bit 3-to-1 multiplexer for signal <_n0400> created at line 477.
-    Found 1-bit 3-to-1 multiplexer for signal <_n0419> created at line 477.
-    Found 1-bit 3-to-1 multiplexer for signal <_n0438> created at line 477.
-    Found 1-bit 3-to-1 multiplexer for signal <_n0457> created at line 477.
-    Found 1-bit 3-to-1 multiplexer for signal <_n0476> created at line 477.
-    Found 1-bit 3-to-1 multiplexer for signal <_n0495> created at line 477.
-    Found 1-bit 3-to-1 multiplexer for signal <_n0514> created at line 477.
-    Found 1-bit 3-to-1 multiplexer for signal <_n0533> created at line 477.
-    Found 1-bit 3-to-1 multiplexer for signal <_n0552> created at line 477.
-    Found 1-bit 3-to-1 multiplexer for signal <_n0571> created at line 477.
-    Found 1-bit 3-to-1 multiplexer for signal <_n0590> created at line 477.
-    Found 1-bit 3-to-1 multiplexer for signal <_n0609> created at line 477.
-    Found 1-bit 3-to-1 multiplexer for signal <_n0628> created at line 477.
-    Found 1-bit 3-to-1 multiplexer for signal <_n0647> created at line 477.
-    Found 1-bit 3-to-1 multiplexer for signal <_n0666> created at line 477.
-    Found 1-bit 3-to-1 multiplexer for signal <_n0685> created at line 477.
-    Found 1-bit 3-to-1 multiplexer for signal <_n0704> created at line 477.
-    Found 1-bit 3-to-1 multiplexer for signal <_n0723> created at line 477.
-    Found 1-bit 3-to-1 multiplexer for signal <_n0742> created at line 477.
-    Found 1-bit 3-to-1 multiplexer for signal <_n0761> created at line 477.
-    Found 1-bit 3-to-1 multiplexer for signal <_n0780> created at line 477.
-    Found 1-bit 3-to-1 multiplexer for signal <_n0799> created at line 477.
-    Found 1-bit 3-to-1 multiplexer for signal <_n0818> created at line 477.
-    Found 1-bit 3-to-1 multiplexer for signal <_n0837> created at line 477.
-    Found 1-bit 3-to-1 multiplexer for signal <_n0856> created at line 477.
-    Found 1-bit 3-to-1 multiplexer for signal <_n0875> created at line 477.
-    Found 1-bit 3-to-1 multiplexer for signal <_n0894> created at line 477.
-WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<30>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
-WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<29>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
-WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<28>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
-WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<27>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
-WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<26>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
-WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<25>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
-WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<24>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
-WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<23>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
-WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<22>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
-WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<21>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
-WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<20>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
-WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<19>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
-WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<18>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
-WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<17>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
-WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<16>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
-WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<15>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
-WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<14>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
-WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<13>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
-WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<12>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
-WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<11>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
-WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<10>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
-WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<9>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
-WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<8>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
-WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<7>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
-WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<6>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
-WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<5>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
-WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<4>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
-WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<3>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
-WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<2>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
-WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<1>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
-WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<0>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
-WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<31>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
-    Found 2-bit comparator greater for signal <wb_periph_addr[1]_PWR_57_o_LessThan_48_o> created at line 465
-    Summary:
-	inferred   2 Adder/Subtractor(s).
-	inferred 242 D-type flip-flop(s).
-	inferred  32 Latch(s).
-	inferred   1 Comparator(s).
-	inferred  72 Multiplexer(s).
-	inferred   2 Finite State Machine(s).
-Unit <wbmaster32> synthesized.
-
-Synthesizing Unit <dma_controller>.
-    Related source file is "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/dma_controller.vhd".
-INFO:Xst:3010 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/dma_controller.vhd" line 204: Output port <dma_stat_o> of the instance <dma_controller_wb_slave_0> is unconnected or connected to loadless signal.
-INFO:Xst:3010 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/dma_controller.vhd" line 204: Output port <dma_stat_load_o> of the instance <dma_controller_wb_slave_0> is unconnected or connected to loadless signal.
-    Found 32-bit register for signal <dma_cstart_reg>.
-    Found 32-bit register for signal <dma_hstartl_reg>.
-    Found 32-bit register for signal <dma_hstarth_reg>.
-    Found 32-bit register for signal <dma_len_reg>.
-    Found 32-bit register for signal <dma_nextl_reg>.
-    Found 32-bit register for signal <dma_nexth_reg>.
-    Found 32-bit register for signal <dma_attrib_reg>.
-    Found 32-bit register for signal <dma_ctrl_carrier_addr_o>.
-    Found 32-bit register for signal <dma_ctrl_host_addr_h_o>.
-    Found 32-bit register for signal <dma_ctrl_host_addr_l_o>.
-    Found 32-bit register for signal <dma_ctrl_len_o>.
-    Found 32-bit register for signal <dma_ctrl_reg>.
-    Found 3-bit register for signal <dma_ctrl_current_state>.
-    Found 3-bit register for signal <dma_status>.
-    Found 3-bit register for signal <dma_stat_reg>.
-    Found 1-bit register for signal <dma_ctrl_start_l2p_o>.
-    Found 1-bit register for signal <dma_ctrl_start_p2l_o>.
-    Found 1-bit register for signal <dma_ctrl_start_next_o>.
-    Found 1-bit register for signal <dma_error_irq>.
-    Found 1-bit register for signal <dma_done_irq>.
-    Found 1-bit register for signal <dma_ctrl_abort_o>.
-    Found finite state machine <FSM_5> for signal <dma_ctrl_current_state>.
-    -----------------------------------------------------------------------
-    | States             | 7                                              |
-    | Transitions        | 18                                             |
-    | Inputs             | 7                                              |
-    | Outputs            | 12                                             |
-    | Clock              | clk_i (rising_edge)                            |
-    | Reset              | rst_n_i (negative)                             |
-    | Reset type         | asynchronous                                   |
-    | Reset State        | dma_idle                                       |
-    | Power Up State     | dma_idle                                       |
-    | Encoding           | auto                                           |
-    | Implementation     | LUT                                            |
-    -----------------------------------------------------------------------
-    WARNING:Xst:2404 -  FFs/Latches <dma_stat_reg<31:3>> (without init value) have a constant value of 0 in block <dma_controller>.
-    Summary:
-	inferred 396 D-type flip-flop(s).
-	inferred  13 Multiplexer(s).
-	inferred   1 Finite State Machine(s).
-Unit <dma_controller> synthesized.
-
-Synthesizing Unit <dma_controller_wb_slave>.
-    Related source file is "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd".
-WARNING:Xst:647 - Input <wb_sel_i<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-    Found 9-bit register for signal <ack_sreg>.
-    Found 32-bit register for signal <rddata_reg>.
-    Found 32-bit register for signal <dma_ctrl_int_write>.
-    Found 32-bit register for signal <dma_stat_int_write>.
-    Found 32-bit register for signal <dma_cstart_int_write>.
-    Found 32-bit register for signal <dma_hstartl_int_write>.
-    Found 32-bit register for signal <dma_hstarth_int_write>.
-    Found 32-bit register for signal <dma_len_int_write>.
-    Found 32-bit register for signal <dma_nextl_int_write>.
-    Found 32-bit register for signal <dma_nexth_int_write>.
-    Found 32-bit register for signal <dma_attrib_int_write>.
-    Found 32-bit register for signal <dma_ctrl_o>.
-    Found 32-bit register for signal <dma_ctrl_int_read>.
-    Found 32-bit register for signal <dma_stat_o>.
-    Found 32-bit register for signal <dma_stat_int_read>.
-    Found 32-bit register for signal <dma_cstart_o>.
-    Found 32-bit register for signal <dma_cstart_int_read>.
-    Found 32-bit register for signal <dma_hstartl_o>.
-    Found 32-bit register for signal <dma_hstartl_int_read>.
-    Found 32-bit register for signal <dma_hstarth_o>.
-    Found 32-bit register for signal <dma_hstarth_int_read>.
-    Found 32-bit register for signal <dma_len_o>.
-    Found 32-bit register for signal <dma_len_int_read>.
-    Found 32-bit register for signal <dma_nextl_o>.
-    Found 32-bit register for signal <dma_nextl_int_read>.
-    Found 32-bit register for signal <dma_nexth_o>.
-    Found 32-bit register for signal <dma_nexth_int_read>.
-    Found 32-bit register for signal <dma_attrib_o>.
-    Found 32-bit register for signal <dma_attrib_int_read>.
-    Found 1-bit register for signal <ack_in_progress>.
-    Found 1-bit register for signal <dma_ctrl_lw>.
-    Found 1-bit register for signal <dma_ctrl_lw_delay>.
-    Found 1-bit register for signal <dma_ctrl_lw_read_in_progress>.
-    Found 1-bit register for signal <dma_ctrl_rwsel>.
-    Found 1-bit register for signal <dma_stat_lw>.
-    Found 1-bit register for signal <dma_stat_lw_delay>.
-    Found 1-bit register for signal <dma_stat_lw_read_in_progress>.
-    Found 1-bit register for signal <dma_stat_rwsel>.
-    Found 1-bit register for signal <dma_cstart_lw>.
-    Found 1-bit register for signal <dma_cstart_lw_delay>.
-    Found 1-bit register for signal <dma_cstart_lw_read_in_progress>.
-    Found 1-bit register for signal <dma_cstart_rwsel>.
-    Found 1-bit register for signal <dma_hstartl_lw>.
-    Found 1-bit register for signal <dma_hstartl_lw_delay>.
-    Found 1-bit register for signal <dma_hstartl_lw_read_in_progress>.
-    Found 1-bit register for signal <dma_hstartl_rwsel>.
-    Found 1-bit register for signal <dma_hstarth_lw>.
-    Found 1-bit register for signal <dma_hstarth_lw_delay>.
-    Found 1-bit register for signal <dma_hstarth_lw_read_in_progress>.
-    Found 1-bit register for signal <dma_hstarth_rwsel>.
-    Found 1-bit register for signal <dma_len_lw>.
-    Found 1-bit register for signal <dma_len_lw_delay>.
-    Found 1-bit register for signal <dma_len_lw_read_in_progress>.
-    Found 1-bit register for signal <dma_len_rwsel>.
-    Found 1-bit register for signal <dma_nextl_lw>.
-    Found 1-bit register for signal <dma_nextl_lw_delay>.
-    Found 1-bit register for signal <dma_nextl_lw_read_in_progress>.
-    Found 1-bit register for signal <dma_nextl_rwsel>.
-    Found 1-bit register for signal <dma_nexth_lw>.
-    Found 1-bit register for signal <dma_nexth_lw_delay>.
-    Found 1-bit register for signal <dma_nexth_lw_read_in_progress>.
-    Found 1-bit register for signal <dma_nexth_rwsel>.
-    Found 1-bit register for signal <dma_attrib_lw>.
-    Found 1-bit register for signal <dma_attrib_lw_delay>.
-    Found 1-bit register for signal <dma_attrib_lw_read_in_progress>.
-    Found 1-bit register for signal <dma_attrib_rwsel>.
-    Found 1-bit register for signal <dma_ctrl_lw_s0>.
-    Found 1-bit register for signal <dma_ctrl_lw_s1>.
-    Found 1-bit register for signal <dma_ctrl_lw_s2>.
-    Found 1-bit register for signal <dma_ctrl_load_o>.
-    Found 1-bit register for signal <dma_stat_lw_s0>.
-    Found 1-bit register for signal <dma_stat_lw_s1>.
-    Found 1-bit register for signal <dma_stat_lw_s2>.
-    Found 1-bit register for signal <dma_stat_load_o>.
-    Found 1-bit register for signal <dma_cstart_lw_s0>.
-    Found 1-bit register for signal <dma_cstart_lw_s1>.
-    Found 1-bit register for signal <dma_cstart_lw_s2>.
-    Found 1-bit register for signal <dma_cstart_load_o>.
-    Found 1-bit register for signal <dma_hstartl_lw_s0>.
-    Found 1-bit register for signal <dma_hstartl_lw_s1>.
-    Found 1-bit register for signal <dma_hstartl_lw_s2>.
-    Found 1-bit register for signal <dma_hstartl_load_o>.
-    Found 1-bit register for signal <dma_hstarth_lw_s0>.
-    Found 1-bit register for signal <dma_hstarth_lw_s1>.
-    Found 1-bit register for signal <dma_hstarth_lw_s2>.
-    Found 1-bit register for signal <dma_hstarth_load_o>.
-    Found 1-bit register for signal <dma_len_lw_s0>.
-    Found 1-bit register for signal <dma_len_lw_s1>.
-    Found 1-bit register for signal <dma_len_lw_s2>.
-    Found 1-bit register for signal <dma_len_load_o>.
-    Found 1-bit register for signal <dma_nextl_lw_s0>.
-    Found 1-bit register for signal <dma_nextl_lw_s1>.
-    Found 1-bit register for signal <dma_nextl_lw_s2>.
-    Found 1-bit register for signal <dma_nextl_load_o>.
-    Found 1-bit register for signal <dma_nexth_lw_s0>.
-    Found 1-bit register for signal <dma_nexth_lw_s1>.
-    Found 1-bit register for signal <dma_nexth_lw_s2>.
-    Found 1-bit register for signal <dma_nexth_load_o>.
-    Found 1-bit register for signal <dma_attrib_lw_s0>.
-    Found 1-bit register for signal <dma_attrib_lw_s1>.
-    Found 1-bit register for signal <dma_attrib_lw_s2>.
-    Found 1-bit register for signal <dma_attrib_load_o>.
-    WARNING:Xst:2404 -  FFs/Latches <ack_sreg<9:9>> (without init value) have a constant value of 0 in block <dma_controller_wb_slave>.
-    Summary:
-	inferred 978 D-type flip-flop(s).
-	inferred  41 Multiplexer(s).
-Unit <dma_controller_wb_slave> synthesized.
-
-Synthesizing Unit <l2p_dma_master>.
-    Related source file is "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/l2p_dma_master.vhd".
-        g_BYTE_SWAP = false
-WARNING:Xst:647 - Input <dma_ctrl_target_addr_i<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <dma_ctrl_len_i<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <dma_ctrl_byte_swap_i<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-INFO:Xst:3010 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/l2p_dma_master.vhd" line 481: Output port <full> of the instance <cmp_addr_fifo> is unconnected or connected to loadless signal.
-INFO:Xst:3010 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/l2p_dma_master.vhd" line 497: Output port <full> of the instance <cmp_data_fifo> is unconnected or connected to loadless signal.
-INFO:Xst:3010 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/l2p_dma_master.vhd" line 497: Output port <valid> of the instance <cmp_data_fifo> is unconnected or connected to loadless signal.
-    Found 1-bit register for signal <dma_ctrl_error_o>.
-    Found 1-bit register for signal <addr_fifo_wr>.
-    Found 1-bit register for signal <l2p_64b_address>.
-    Found 1-bit register for signal <l2p_last_packet>.
-    Found 1-bit register for signal <ldm_arb_req_o>.
-    Found 1-bit register for signal <ldm_arb_valid_o>.
-    Found 1-bit register for signal <ldm_arb_dframe_o>.
-    Found 1-bit register for signal <data_fifo_rd>.
-    Found 1-bit register for signal <dma_ctrl_done_o>.
-    Found 1-bit register for signal <l2p_edb_o>.
-    Found 1-bit register for signal <l2p_dma_stb_t>.
-    Found 1-bit register for signal <l2p_dma_cyc_t>.
-    Found 30-bit register for signal <dma_length_cnt>.
-    Found 30-bit register for signal <l2p_len_cnt>.
-    Found 30-bit register for signal <target_addr_cnt>.
-    Found 11-bit register for signal <l2p_data_cnt>.
-    Found 32-bit register for signal <l2p_address_h>.
-    Found 32-bit register for signal <l2p_address_l>.
-    Found 32-bit register for signal <ldm_arb_data_o>.
-    Found 32-bit register for signal <l2p_dma_adr_o>.
-    Found 10-bit register for signal <l2p_len_header>.
-    Found 3-bit register for signal <l2p_dma_current_state>.
-    Found 4-bit register for signal <l2p_dma_sel_o>.
-    Found 7-bit register for signal <wb_read_cnt>.
-    Found 7-bit register for signal <wb_ack_cnt>.
-    Found 32-bit register for signal <addr_fifo_din>.
-    Found finite state machine <FSM_6> for signal <l2p_dma_current_state>.
-    -----------------------------------------------------------------------
-    | States             | 8                                              |
-    | Transitions        | 23                                             |
-    | Inputs             | 9                                              |
-    | Outputs            | 11                                             |
-    | Clock              | clk_i (rising_edge)                            |
-    | Reset              | rst_n_i (negative)                             |
-    | Reset type         | asynchronous                                   |
-    | Reset State        | l2p_idle                                       |
-    | Power Up State     | l2p_idle                                       |
-    | Encoding           | auto                                           |
-    | Implementation     | LUT                                            |
-    -----------------------------------------------------------------------
-    Found 30-bit adder for signal <target_addr_cnt[29]_GND_190_o_add_4_OUT> created at line 1241.
-    Found 32-bit adder for signal <l2p_address_l[31]_GND_190_o_add_35_OUT> created at line 269.
-    Found 7-bit adder for signal <wb_read_cnt[6]_GND_190_o_add_111_OUT> created at line 1241.
-    Found 7-bit adder for signal <wb_ack_cnt[6]_GND_190_o_add_114_OUT> created at line 1241.
-    Found 30-bit subtractor for signal <GND_190_o_GND_190_o_sub_6_OUT<29:0>>.
-    Found 30-bit subtractor for signal <GND_190_o_GND_190_o_sub_31_OUT<29:0>>.
-    Found 11-bit subtractor for signal <GND_190_o_GND_190_o_sub_34_OUT<10:0>>.
-    Found 7-bit subtractor for signal <GND_190_o_GND_190_o_sub_108_OUT<6:0>>.
-    Found 30-bit comparator greater for signal <GND_190_o_l2p_len_cnt[29]_LessThan_37_o> created at line 271
-    Found 11-bit comparator greater for signal <n0097> created at line 401
-    Found 11-bit comparator greater for signal <n0109> created at line 414
-    Found 7-bit comparator equal for signal <wb_ack_cnt[6]_GND_190_o_equal_109_o> created at line 557
-    Summary:
-	inferred   8 Adder/Subtractor(s).
-	inferred 301 D-type flip-flop(s).
-	inferred   4 Comparator(s).
-	inferred  23 Multiplexer(s).
-	inferred   1 Finite State Machine(s).
-Unit <l2p_dma_master> synthesized.
-
-Synthesizing Unit <p2l_dma_master>.
-    Related source file is "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/p2l_dma_master.vhd".
-        g_BYTE_SWAP = false
-WARNING:Xst:647 - Input <dma_ctrl_carrier_addr_i<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <dma_ctrl_len_i<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <dma_ctrl_byte_swap_i<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <pd_pdm_hdr_length_i<9:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <pd_pdm_hdr_cid_i<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <pd_pdm_be_i<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <p2l_dma_dat_i<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <pd_pdm_hdr_start_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-INFO:Xst:3010 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/p2l_dma_master.vhd" line 493: Output port <full> of the instance <cmp_to_wb_fifo> is unconnected or connected to loadless signal.
-    Found 1-bit register for signal <l2p_64b_address>.
-    Found 1-bit register for signal <is_next_item>.
-    Found 1-bit register for signal <l2p_last_packet>.
-    Found 1-bit register for signal <pdm_arb_req_o>.
-    Found 1-bit register for signal <pdm_arb_valid_o>.
-    Found 1-bit register for signal <pdm_arb_dframe_o>.
-    Found 1-bit register for signal <dma_ctrl_done_t>.
-    Found 1-bit register for signal <next_item_valid_o>.
-    Found 1-bit register for signal <completion_error>.
-    Found 1-bit register for signal <rx_error_t>.
-    Found 1-bit register for signal <rx_error_o>.
-    Found 1-bit register for signal <dma_ctrl_done_o>.
-    Found 1-bit register for signal <dma_busy_error>.
-    Found 1-bit register for signal <to_wb_fifo_din<61>>.
-    Found 1-bit register for signal <to_wb_fifo_din<60>>.
-    Found 1-bit register for signal <to_wb_fifo_din<59>>.
-    Found 1-bit register for signal <to_wb_fifo_din<58>>.
-    Found 1-bit register for signal <to_wb_fifo_din<57>>.
-    Found 1-bit register for signal <to_wb_fifo_din<56>>.
-    Found 1-bit register for signal <to_wb_fifo_din<55>>.
-    Found 1-bit register for signal <to_wb_fifo_din<54>>.
-    Found 1-bit register for signal <to_wb_fifo_din<53>>.
-    Found 1-bit register for signal <to_wb_fifo_din<52>>.
-    Found 1-bit register for signal <to_wb_fifo_din<51>>.
-    Found 1-bit register for signal <to_wb_fifo_din<50>>.
-    Found 1-bit register for signal <to_wb_fifo_din<49>>.
-    Found 1-bit register for signal <to_wb_fifo_din<48>>.
-    Found 1-bit register for signal <to_wb_fifo_din<47>>.
-    Found 1-bit register for signal <to_wb_fifo_din<46>>.
-    Found 1-bit register for signal <to_wb_fifo_din<45>>.
-    Found 1-bit register for signal <to_wb_fifo_din<44>>.
-    Found 1-bit register for signal <to_wb_fifo_din<43>>.
-    Found 1-bit register for signal <to_wb_fifo_din<42>>.
-    Found 1-bit register for signal <to_wb_fifo_din<41>>.
-    Found 1-bit register for signal <to_wb_fifo_din<40>>.
-    Found 1-bit register for signal <to_wb_fifo_din<39>>.
-    Found 1-bit register for signal <to_wb_fifo_din<38>>.
-    Found 1-bit register for signal <to_wb_fifo_din<37>>.
-    Found 1-bit register for signal <to_wb_fifo_din<36>>.
-    Found 1-bit register for signal <to_wb_fifo_din<35>>.
-    Found 1-bit register for signal <to_wb_fifo_din<34>>.
-    Found 1-bit register for signal <to_wb_fifo_din<33>>.
-    Found 1-bit register for signal <to_wb_fifo_din<32>>.
-    Found 1-bit register for signal <to_wb_fifo_din<31>>.
-    Found 1-bit register for signal <to_wb_fifo_din<30>>.
-    Found 1-bit register for signal <to_wb_fifo_din<29>>.
-    Found 1-bit register for signal <to_wb_fifo_din<28>>.
-    Found 1-bit register for signal <to_wb_fifo_din<27>>.
-    Found 1-bit register for signal <to_wb_fifo_din<26>>.
-    Found 1-bit register for signal <to_wb_fifo_din<25>>.
-    Found 1-bit register for signal <to_wb_fifo_din<24>>.
-    Found 1-bit register for signal <to_wb_fifo_din<23>>.
-    Found 1-bit register for signal <to_wb_fifo_din<22>>.
-    Found 1-bit register for signal <to_wb_fifo_din<21>>.
-    Found 1-bit register for signal <to_wb_fifo_din<20>>.
-    Found 1-bit register for signal <to_wb_fifo_din<19>>.
-    Found 1-bit register for signal <to_wb_fifo_din<18>>.
-    Found 1-bit register for signal <to_wb_fifo_din<17>>.
-    Found 1-bit register for signal <to_wb_fifo_din<16>>.
-    Found 1-bit register for signal <to_wb_fifo_din<15>>.
-    Found 1-bit register for signal <to_wb_fifo_din<14>>.
-    Found 1-bit register for signal <to_wb_fifo_din<13>>.
-    Found 1-bit register for signal <to_wb_fifo_din<12>>.
-    Found 1-bit register for signal <to_wb_fifo_din<11>>.
-    Found 1-bit register for signal <to_wb_fifo_din<10>>.
-    Found 1-bit register for signal <to_wb_fifo_din<9>>.
-    Found 1-bit register for signal <to_wb_fifo_din<8>>.
-    Found 1-bit register for signal <to_wb_fifo_din<7>>.
-    Found 1-bit register for signal <to_wb_fifo_din<6>>.
-    Found 1-bit register for signal <to_wb_fifo_din<5>>.
-    Found 1-bit register for signal <to_wb_fifo_din<4>>.
-    Found 1-bit register for signal <to_wb_fifo_din<3>>.
-    Found 1-bit register for signal <to_wb_fifo_din<2>>.
-    Found 1-bit register for signal <to_wb_fifo_din<1>>.
-    Found 1-bit register for signal <to_wb_fifo_din<0>>.
-    Found 1-bit register for signal <to_wb_fifo_wr>.
-    Found 1-bit register for signal <p2l_dma_cyc_t>.
-    Found 1-bit register for signal <p2l_dma_stb_t>.
-    Found 32-bit register for signal <l2p_address_l>.
-    Found 32-bit register for signal <pdm_arb_data_o>.
-    Found 32-bit register for signal <next_item_carrier_addr_o>.
-    Found 32-bit register for signal <next_item_host_addr_h_o>.
-    Found 32-bit register for signal <next_item_host_addr_l_o>.
-    Found 32-bit register for signal <next_item_len_o>.
-    Found 32-bit register for signal <next_item_next_l_o>.
-    Found 32-bit register for signal <next_item_next_h_o>.
-    Found 32-bit register for signal <next_item_attrib_o>.
-    Found 32-bit register for signal <p2l_dma_adr_o>.
-    Found 32-bit register for signal <p2l_dma_dat_o>.
-    Found 32-bit register for signal <l2p_address_h>.
-    Found 30-bit register for signal <l2p_len_cnt>.
-    Found 30-bit register for signal <target_addr_cnt>.
-    Found 10-bit register for signal <l2p_len_header>.
-    Found 3-bit register for signal <p2l_dma_current_state>.
-    Found 11-bit register for signal <p2l_data_cnt>.
-    Found 4-bit register for signal <p2l_dma_sel_o>.
-    Found 7-bit register for signal <wb_write_cnt>.
-    Found 7-bit register for signal <wb_ack_cnt>.
-    Found finite state machine <FSM_7> for signal <p2l_dma_current_state>.
-    -----------------------------------------------------------------------
-    | States             | 5                                              |
-    | Transitions        | 16                                             |
-    | Inputs             | 9                                              |
-    | Outputs            | 13                                             |
-    | Clock              | clk_i (rising_edge)                            |
-    | Reset              | rst_n_i (negative)                             |
-    | Reset type         | asynchronous                                   |
-    | Reset State        | p2l_idle                                       |
-    | Power Up State     | p2l_idle                                       |
-    | Encoding           | auto                                           |
-    | Implementation     | LUT                                            |
-    -----------------------------------------------------------------------
-    Found 30-bit adder for signal <target_addr_cnt[29]_GND_203_o_add_79_OUT> created at line 1241.
-    Found 7-bit adder for signal <wb_write_cnt[6]_GND_203_o_add_93_OUT> created at line 1241.
-    Found 7-bit adder for signal <wb_ack_cnt[6]_GND_203_o_add_96_OUT> created at line 1241.
-    Found 30-bit subtractor for signal <GND_203_o_GND_203_o_sub_12_OUT<29:0>>.
-    Found 11-bit subtractor for signal <GND_203_o_GND_203_o_sub_50_OUT<10:0>>.
-    Found 7-bit subtractor for signal <GND_203_o_GND_203_o_sub_89_OUT<6:0>>.
-    Found 30-bit comparator greater for signal <GND_203_o_l2p_len_cnt[29]_LessThan_7_o> created at line 233
-    Found 11-bit comparator greater for signal <n0046> created at line 338
-    Found 7-bit comparator equal for signal <wb_ack_cnt[6]_GND_203_o_equal_90_o> created at line 550
-    Summary:
-	inferred   6 Adder/Subtractor(s).
-	inferred 561 D-type flip-flop(s).
-	inferred   3 Comparator(s).
-	inferred   7 Multiplexer(s).
-	inferred   1 Finite State Machine(s).
-Unit <p2l_dma_master> synthesized.
-
-Synthesizing Unit <l2p_arbiter>.
-    Related source file is "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/l2p_arbiter.vhd".
-    Found 32-bit register for signal <arb_ser_data_t>.
-    Found 32-bit register for signal <arb_ser_data_o>.
-    Found 1-bit register for signal <arb_pdm_gnt>.
-    Found 1-bit register for signal <arb_ldm_gnt>.
-    Found 1-bit register for signal <arb_ser_valid_t>.
-    Found 1-bit register for signal <arb_ser_dframe_t>.
-    Found 1-bit register for signal <arb_ser_valid_o>.
-    Found 1-bit register for signal <arb_ser_dframe_o>.
-    Found 1-bit register for signal <arb_wbm_gnt>.
-    Summary:
-	inferred  71 D-type flip-flop(s).
-	inferred  12 Multiplexer(s).
-Unit <l2p_arbiter> synthesized.
-
-Synthesizing Unit <l2p_ser>.
-    Related source file is "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/l2p_ser_s6.vhd".
-    Summary:
-	no macro.
-Unit <l2p_ser> synthesized.
-
-Synthesizing Unit <serdes_n_to_1_s2_diff>.
-    Related source file is "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/serdes_n_to_1_s2_diff.vhd".
-        S = 2
-        D = 1
-WARNING:Xst:653 - Signal <mdatainb<3:2>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
-    Summary:
-	no macro.
-Unit <serdes_n_to_1_s2_diff> synthesized.
-
-Synthesizing Unit <serdes_n_to_1_s2_se_1>.
-    Related source file is "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/serdes_n_to_1_s2_se.vhd".
-        S = 2
-        D = 16
-WARNING:Xst:653 - Signal <mdatainb<63:62>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
-WARNING:Xst:653 - Signal <mdatainb<59:58>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
-WARNING:Xst:653 - Signal <mdatainb<55:54>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
-WARNING:Xst:653 - Signal <mdatainb<51:50>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
-WARNING:Xst:653 - Signal <mdatainb<47:46>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
-WARNING:Xst:653 - Signal <mdatainb<43:42>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
-WARNING:Xst:653 - Signal <mdatainb<39:38>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
-WARNING:Xst:653 - Signal <mdatainb<35:34>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
-WARNING:Xst:653 - Signal <mdatainb<31:30>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
-WARNING:Xst:653 - Signal <mdatainb<27:26>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
-WARNING:Xst:653 - Signal <mdatainb<23:22>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
-WARNING:Xst:653 - Signal <mdatainb<19:18>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
-WARNING:Xst:653 - Signal <mdatainb<15:14>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
-WARNING:Xst:653 - Signal <mdatainb<11:10>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
-WARNING:Xst:653 - Signal <mdatainb<7:6>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
-WARNING:Xst:653 - Signal <mdatainb<3:2>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
-    Summary:
-	no macro.
-Unit <serdes_n_to_1_s2_se_1> synthesized.
-
-Synthesizing Unit <serdes_n_to_1_s2_se_2>.
-    Related source file is "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/serdes_n_to_1_s2_se.vhd".
-        S = 2
-        D = 1
-WARNING:Xst:653 - Signal <mdatainb<3:2>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
-    Summary:
-	no macro.
-Unit <serdes_n_to_1_s2_se_2> synthesized.
-
-Synthesizing Unit <dummy_stat_regs_wb_slave>.
-    Related source file is "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/dummy_stat_regs.vhd".
-WARNING:Xst:647 - Input <wb_data_i<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <wb_sel_i<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-    Found 9-bit register for signal <ack_sreg>.
-    Found 32-bit register for signal <rddata_reg>.
-    Found 1-bit register for signal <ack_in_progress>.
-    Found 32-bit 4-to-1 multiplexer for signal <rwaddr_reg[1]_dummy_stat_reg_switch_i[31]_wide_mux_8_OUT> created at line 82.
-    WARNING:Xst:2404 -  FFs/Latches <ack_sreg<9:9>> (without init value) have a constant value of 0 in block <dummy_stat_regs_wb_slave>.
-    Summary:
-	inferred  42 D-type flip-flop(s).
-	inferred   7 Multiplexer(s).
-Unit <dummy_stat_regs_wb_slave> synthesized.
-
-Synthesizing Unit <dummy_ctrl_regs_wb_slave>.
-    Related source file is "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/dummy_ctrl_regs.vhd".
-WARNING:Xst:647 - Input <wb_sel_i<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-    Found 8-bit register for signal <ack_sreg>.
-    Found 32-bit register for signal <rddata_reg>.
-    Found 32-bit register for signal <dummy_reg_1_int>.
-    Found 32-bit register for signal <dummy_reg_2_int>.
-    Found 32-bit register for signal <dummy_reg_3_int>.
-    Found 32-bit register for signal <dummy_reg_led_int>.
-    Found 1-bit register for signal <ack_in_progress>.
-    Found 32-bit 4-to-1 multiplexer for signal <rwaddr_reg[1]_dummy_reg_led_int[31]_wide_mux_13_OUT> created at line 90.
-    WARNING:Xst:2404 -  FFs/Latches <ack_sreg<9:9>> (without init value) have a constant value of 0 in block <dummy_ctrl_regs_wb_slave>.
-    WARNING:Xst:2404 -  FFs/Latches <ack_sreg<8:8>> (without init value) have a constant value of 0 in block <dummy_ctrl_regs_wb_slave>.
-    Summary:
-	inferred 169 D-type flip-flop(s).
-	inferred   7 Multiplexer(s).
-Unit <dummy_ctrl_regs_wb_slave> synthesized.
-RTL-Simplification CPUSTAT: 2.09 
-RTL-BasicInf CPUSTAT: 3.16 
-RTL-BasicOpt CPUSTAT: 0.02 
-RTL-Remain-Bus CPUSTAT: 0.15 
-
-=========================================================================
-HDL Synthesis Report
-
-Macro Statistics
-# Adders/Subtractors                                   : 25
- 11-bit subtractor                                     : 2
- 12-bit adder                                          : 1
- 2-bit adder                                           : 1
- 3-bit adder                                           : 1
- 30-bit adder                                          : 3
- 30-bit subtractor                                     : 3
- 32-bit adder                                          : 1
- 4-bit adder                                           : 1
- 5-bit addsub                                          : 2
- 7-bit adder                                           : 4
- 7-bit subtractor                                      : 2
- 8-bit adder                                           : 1
- 9-bit adder                                           : 3
-# Registers                                            : 365
- 1-bit register                                        : 245
- 10-bit register                                       : 3
- 11-bit register                                       : 2
- 12-bit register                                       : 1
- 16-bit register                                       : 2
- 2-bit register                                        : 10
- 3-bit register                                        : 3
- 30-bit register                                       : 5
- 31-bit register                                       : 1
- 32-bit register                                       : 73
- 4-bit register                                        : 7
- 5-bit register                                        : 2
- 64-bit register                                       : 1
- 7-bit register                                        : 4
- 8-bit register                                        : 1
- 9-bit register                                        : 5
-# Latches                                              : 32
- 1-bit latch                                           : 32
-# Comparators                                          : 8
- 11-bit comparator greater                             : 3
- 2-bit comparator greater                              : 1
- 30-bit comparator greater                             : 2
- 7-bit comparator equal                                : 2
-# Multiplexers                                         : 258
- 1-bit 2-to-1 multiplexer                              : 142
- 1-bit 3-to-1 multiplexer                              : 33
- 10-bit 2-to-1 multiplexer                             : 3
- 11-bit 2-to-1 multiplexer                             : 6
- 12-bit 2-to-1 multiplexer                             : 1
- 2-bit 2-to-1 multiplexer                              : 1
- 30-bit 2-to-1 multiplexer                             : 8
- 32-bit 2-to-1 multiplexer                             : 46
- 32-bit 3-to-1 multiplexer                             : 1
- 32-bit 4-to-1 multiplexer                             : 2
- 4-bit 2-to-1 multiplexer                              : 5
- 5-bit 2-to-1 multiplexer                              : 6
- 64-bit 2-to-1 multiplexer                             : 1
- 9-bit 2-to-1 multiplexer                              : 3
-# FSMs                                                 : 9
-
-=========================================================================
-
-=========================================================================
-*                       Advanced HDL Synthesis                          *
-=========================================================================
-
-Reading core <../ip_cores/ram_2048x32.ngc>.
-Reading core <../ip_cores/fifo_32x512.ngc>.
-Reading core <../ip_cores/fifo_64x512.ngc>.
-Loading core <ram_2048x32> for timing and area information for instance <cmp_test_ram>.
-Loading core <fifo_32x512> for timing and area information for instance <cmp_data_fifo>.
-Loading core <fifo_32x512> for timing and area information for instance <cmp_addr_fifo>.
-Loading core <fifo_64x512> for timing and area information for instance <cmp_to_wb_fifo>.
-Loading core <fifo_64x512> for timing and area information for instance <cmp_fifo_to_wb>.
-Loading core <fifo_32x512> for timing and area information for instance <cmp_from_wb_fifo>.
-INFO:Xst:2261 - The FF/Latch <addr_fifo_din_30> in Unit <cmp_l2p_dma_master> is equivalent to the following FF/Latch, which will be removed : <addr_fifo_din_31> 
-INFO:Xst:2261 - The FF/Latch <p2l_dma_adr_o_30> in Unit <cmp_p2l_dma_master> is equivalent to the following FF/Latch, which will be removed : <p2l_dma_adr_o_31> 
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_7> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_8> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_9> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_10> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_11> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_12> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_13> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_14> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_15> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_16> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_17> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_18> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_19> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_20> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_21> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_22> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_23> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_24> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_25> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_26> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_27> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_28> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_29> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_30> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_31> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <ack_sreg_8> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <ack_sreg_8> (without init value) has a constant value of 0 in block <cmp_dummy_stat_regs>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <ack_sreg_7> (without init value) has a constant value of 0 in block <cmp_dummy_ctrl_regs>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <busy_data_d> (without init value) has a constant value of 0 in block <cmp_data_in>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <ce_data_0> (without init value) has a constant value of 0 in block <cmp_data_in>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <ce_data_1> (without init value) has a constant value of 0 in block <cmp_data_in>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <ce_data_2> (without init value) has a constant value of 0 in block <cmp_data_in>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <ce_data_3> (without init value) has a constant value of 0 in block <cmp_data_in>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <ce_data_4> (without init value) has a constant value of 0 in block <cmp_data_in>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <ce_data_5> (without init value) has a constant value of 0 in block <cmp_data_in>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <ce_data_6> (without init value) has a constant value of 0 in block <cmp_data_in>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <ce_data_7> (without init value) has a constant value of 0 in block <cmp_data_in>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <ce_data_8> (without init value) has a constant value of 0 in block <cmp_data_in>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <ce_data_9> (without init value) has a constant value of 0 in block <cmp_data_in>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <ce_data_10> (without init value) has a constant value of 0 in block <cmp_data_in>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <ce_data_11> (without init value) has a constant value of 0 in block <cmp_data_in>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <ce_data_12> (without init value) has a constant value of 0 in block <cmp_data_in>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_6> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_5> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_4> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_3> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <p2l_dma_adr_o_30> (without init value) has a constant value of 0 in block <cmp_p2l_dma_master>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <addr_fifo_din_30> (without init value) has a constant value of 0 in block <cmp_l2p_dma_master>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <busy_data_d> (without init value) has a constant value of 0 in block <cmp_valid_in>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <ce_data_13> (without init value) has a constant value of 0 in block <cmp_data_in>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <ce_data_14> (without init value) has a constant value of 0 in block <cmp_data_in>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <ce_data_15> (without init value) has a constant value of 0 in block <cmp_data_in>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <ce_data_0> (without init value) has a constant value of 0 in block <cmp_valid_in>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <busy_data_d> (without init value) has a constant value of 0 in block <cmp_dframe_in>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <ce_data_0> (without init value) has a constant value of 0 in block <cmp_dframe_in>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <inc_data_int> (without init value) has a constant value of 0 in block <cmp_data_in>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_7> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_7> (without init value) has a constant value of 0 in block <cmp_dummy_stat_regs>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_6> (without init value) has a constant value of 0 in block <cmp_dummy_ctrl_regs>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_6> (without init value) has a constant value of 0 in block <cmp_dummy_stat_regs>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_6> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_5> (without init value) has a constant value of 0 in block <cmp_dummy_ctrl_regs>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_5> (without init value) has a constant value of 0 in block <cmp_dummy_stat_regs>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_4> (without init value) has a constant value of 0 in block <cmp_dummy_ctrl_regs>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_4> (without init value) has a constant value of 0 in block <cmp_dummy_stat_regs>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_3> (without init value) has a constant value of 0 in block <cmp_dummy_ctrl_regs>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_3> (without init value) has a constant value of 0 in block <cmp_dummy_stat_regs>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_2> (without init value) has a constant value of 0 in block <cmp_dummy_ctrl_regs>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_2> (without init value) has a constant value of 0 in block <cmp_dummy_stat_regs>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_1> (without init value) has a constant value of 0 in block <cmp_dummy_ctrl_regs>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_1> (without init value) has a constant value of 0 in block <cmp_dummy_stat_regs>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:2677 - Node <wb_adr_t_4> of sequential type is unconnected in block <cmp_wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_5> of sequential type is unconnected in block <cmp_wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_6> of sequential type is unconnected in block <cmp_wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_7> of sequential type is unconnected in block <cmp_wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_8> of sequential type is unconnected in block <cmp_wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_9> of sequential type is unconnected in block <cmp_wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_10> of sequential type is unconnected in block <cmp_wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_11> of sequential type is unconnected in block <cmp_wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_12> of sequential type is unconnected in block <cmp_wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_13> of sequential type is unconnected in block <cmp_wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_14> of sequential type is unconnected in block <cmp_wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_15> of sequential type is unconnected in block <cmp_wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_18> of sequential type is unconnected in block <cmp_wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_19> of sequential type is unconnected in block <cmp_wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_20> of sequential type is unconnected in block <cmp_wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_21> of sequential type is unconnected in block <cmp_wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_22> of sequential type is unconnected in block <cmp_wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_23> of sequential type is unconnected in block <cmp_wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_24> of sequential type is unconnected in block <cmp_wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_25> of sequential type is unconnected in block <cmp_wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_26> of sequential type is unconnected in block <cmp_wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_27> of sequential type is unconnected in block <cmp_wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_28> of sequential type is unconnected in block <cmp_wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_29> of sequential type is unconnected in block <cmp_wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_30> of sequential type is unconnected in block <cmp_wbmaster32>.
-WARNING:Xst:2677 - Node <dma_ctrl_carrier_addr_o_0> of sequential type is unconnected in block <cmp_dma_controller>.
-WARNING:Xst:2677 - Node <dma_ctrl_carrier_addr_o_1> of sequential type is unconnected in block <cmp_dma_controller>.
-WARNING:Xst:2677 - Node <dma_ctrl_len_o_0> of sequential type is unconnected in block <cmp_dma_controller>.
-WARNING:Xst:2677 - Node <dma_ctrl_len_o_1> of sequential type is unconnected in block <cmp_dma_controller>.
-WARNING:Xst:2404 -  FFs/Latches <addr_fifo_din<31:30>> (without init value) have a constant value of 0 in block <l2p_dma_master>.
-WARNING:Xst:2404 -  FFs/Latches <p2l_dma_adr_o<31:30>> (without init value) have a constant value of 0 in block <p2l_dma_master>.
-WARNING:Xst:2404 -  FFs/Latches <ack_sreg<8:6>> (without init value) have a constant value of 0 in block <dma_controller_wb_slave>.
-WARNING:Xst:2404 -  FFs/Latches <ack_sreg<8:1>> (without init value) have a constant value of 0 in block <dummy_stat_regs_wb_slave>.
-WARNING:Xst:2404 -  FFs/Latches <ack_sreg<7:1>> (without init value) have a constant value of 0 in block <dummy_ctrl_regs_wb_slave>.
-
-Synthesizing (advanced) Unit <l2p_dma_master>.
-The following registers are absorbed into counter <dma_length_cnt>: 1 register on signal <dma_length_cnt>.
-The following registers are absorbed into counter <target_addr_cnt>: 1 register on signal <target_addr_cnt>.
-The following registers are absorbed into counter <wb_read_cnt>: 1 register on signal <wb_read_cnt>.
-The following registers are absorbed into counter <wb_ack_cnt>: 1 register on signal <wb_ack_cnt>.
-Unit <l2p_dma_master> synthesized (advanced).
-
-Synthesizing (advanced) Unit <p2l_dma_master>.
-The following registers are absorbed into counter <target_addr_cnt>: 1 register on signal <target_addr_cnt>.
-The following registers are absorbed into counter <p2l_data_cnt>: 1 register on signal <p2l_data_cnt>.
-The following registers are absorbed into counter <wb_write_cnt>: 1 register on signal <wb_write_cnt>.
-The following registers are absorbed into counter <wb_ack_cnt>: 1 register on signal <wb_ack_cnt>.
-Unit <p2l_dma_master> synthesized (advanced).
-
-Synthesizing (advanced) Unit <pfc_wrapper>.
-The following registers are absorbed into counter <clk_div_cnt>: 1 register on signal <clk_div_cnt>.
-Unit <pfc_wrapper> synthesized (advanced).
-
-Synthesizing (advanced) Unit <serdes_1_to_n_clk_pll_s2_diff>.
-The following registers are absorbed into counter <count>: 1 register on signal <count>.
-The following registers are absorbed into counter <counter>: 1 register on signal <counter>.
-Unit <serdes_1_to_n_clk_pll_s2_diff> synthesized (advanced).
-
-Synthesizing (advanced) Unit <serdes_1_to_n_data_s2_se_1>.
-The following registers are absorbed into counter <counter>: 1 register on signal <counter>.
-Unit <serdes_1_to_n_data_s2_se_1> synthesized (advanced).
-
-Synthesizing (advanced) Unit <serdes_1_to_n_data_s2_se_2>.
-The following registers are absorbed into counter <counter>: 1 register on signal <counter>.
-Unit <serdes_1_to_n_data_s2_se_2> synthesized (advanced).
-WARNING:Xst:2677 - Node <wb_adr_t_18> of sequential type is unconnected in block <wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_19> of sequential type is unconnected in block <wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_20> of sequential type is unconnected in block <wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_21> of sequential type is unconnected in block <wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_22> of sequential type is unconnected in block <wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_23> of sequential type is unconnected in block <wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_24> of sequential type is unconnected in block <wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_25> of sequential type is unconnected in block <wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_26> of sequential type is unconnected in block <wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_27> of sequential type is unconnected in block <wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_28> of sequential type is unconnected in block <wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_29> of sequential type is unconnected in block <wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_30> of sequential type is unconnected in block <wbmaster32>.
-
-=========================================================================
-Advanced HDL Synthesis Report
-
-Macro Statistics
-# Adders/Subtractors                                   : 11
- 11-bit subtractor                                     : 1
- 2-bit adder                                           : 1
- 30-bit adder                                          : 1
- 30-bit subtractor                                     : 2
- 32-bit adder                                          : 1
- 5-bit addsub                                          : 2
- 7-bit subtractor                                      : 2
- 8-bit adder                                           : 1
-# Counters                                             : 14
- 11-bit down counter                                   : 1
- 12-bit up counter                                     : 1
- 3-bit up counter                                      : 1
- 30-bit down counter                                   : 1
- 30-bit up counter                                     : 2
- 4-bit up counter                                      : 1
- 7-bit up counter                                      : 4
- 9-bit up counter                                      : 3
-# Registers                                            : 2860
- Flip-Flops                                            : 2860
-# Comparators                                          : 8
- 11-bit comparator greater                             : 3
- 2-bit comparator greater                              : 1
- 30-bit comparator greater                             : 2
- 7-bit comparator equal                                : 2
-# Multiplexers                                         : 589
- 1-bit 2-to-1 multiplexer                              : 492
- 1-bit 3-to-1 multiplexer                              : 33
- 10-bit 2-to-1 multiplexer                             : 3
- 11-bit 2-to-1 multiplexer                             : 5
- 2-bit 2-to-1 multiplexer                              : 1
- 30-bit 2-to-1 multiplexer                             : 5
- 32-bit 2-to-1 multiplexer                             : 37
- 32-bit 3-to-1 multiplexer                             : 1
- 32-bit 4-to-1 multiplexer                             : 2
- 4-bit 2-to-1 multiplexer                              : 4
- 5-bit 2-to-1 multiplexer                              : 6
-# FSMs                                                 : 9
-
-=========================================================================
-
-=========================================================================
-*                         Low Level Synthesis                           *
-=========================================================================
-WARNING:Xst:1710 - FF/Latch <inc_data_int> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_1>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ce_data_15> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_1>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ce_data_14> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_1>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ce_data_13> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_1>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ce_data_12> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_1>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ce_data_11> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_1>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ce_data_10> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_1>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ce_data_9> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_1>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ce_data_8> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_1>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ce_data_7> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_1>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ce_data_6> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_1>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ce_data_5> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_1>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ce_data_4> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_1>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ce_data_3> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_1>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ce_data_2> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_1>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ce_data_1> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_1>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ce_data_0> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_1>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <busy_data_d> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_1>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <incdec_data_d> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_2>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <busy_data_d> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_2>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <valid_data_d> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_2>. This FF/Latch will be trimmed during the optimization process.
-INFO:Xst:2261 - The FF/Latch <l2p_dma_sel_o_0> in Unit <l2p_dma_master> is equivalent to the following 4 FFs/Latches, which will be removed : <l2p_dma_sel_o_1> <l2p_dma_sel_o_2> <l2p_dma_sel_o_3> <l2p_dma_stb_t> 
-INFO:Xst:2261 - The FF/Latch <p2l_dma_stb_t> in Unit <p2l_dma_master> is equivalent to the following 4 FFs/Latches, which will be removed : <p2l_dma_sel_o_0> <p2l_dma_sel_o_1> <p2l_dma_sel_o_2> <p2l_dma_sel_o_3> 
-INFO:Xst:2261 - The FF/Latch <dma_stat_int_read_3> in Unit <dma_controller_wb_slave> is equivalent to the following 28 FFs/Latches, which will be removed : <dma_stat_int_read_4> <dma_stat_int_read_5> <dma_stat_int_read_6> <dma_stat_int_read_7> <dma_stat_int_read_8> <dma_stat_int_read_9> <dma_stat_int_read_10> <dma_stat_int_read_11> <dma_stat_int_read_12> <dma_stat_int_read_13> <dma_stat_int_read_14> <dma_stat_int_read_15> <dma_stat_int_read_16> <dma_stat_int_read_17> <dma_stat_int_read_18> <dma_stat_int_read_19> <dma_stat_int_read_20> <dma_stat_int_read_21> <dma_stat_int_read_22> <dma_stat_int_read_23> <dma_stat_int_read_24> <dma_stat_int_read_25> <dma_stat_int_read_26> <dma_stat_int_read_27> <dma_stat_int_read_28> <dma_stat_int_read_29> <dma_stat_int_read_30> <dma_stat_int_read_31> 
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_3> (without init value) has a constant value of 0 in block <dma_controller_wb_slave>. This FF/Latch will be trimmed during the optimization process.
-Analyzing FSM <MFsm> for best encoding.
-Optimizing FSM <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/FSM_1> on signal <state[1:4]> with user encoding.
--------------------
- State | Encoding
--------------------
- 0000  | 0000
- 0010  | 0010
- 0011  | 0011
- 0100  | 0100
- 0101  | 0101
- 0110  | 0110
- 0111  | 0111
- 0001  | 0001
--------------------
-Analyzing FSM <MFsm> for best encoding.
-Optimizing FSM <cmp_gn4124_core/cmp_p2l_des/cmp_dframe_in/FSM_2> on signal <state[1:4]> with user encoding.
-Optimizing FSM <cmp_gn4124_core/cmp_p2l_des/cmp_valid_in/FSM_2> on signal <state[1:4]> with user encoding.
--------------------
- State | Encoding
--------------------
- 0000  | 0000
- 0010  | 0010
- 0011  | 0011
- 0100  | 0100
- 0101  | 0101
- 0110  | 0110
- 0111  | 0111
- 0001  | 0001
--------------------
-Analyzing FSM <MFsm> for best encoding.
-Optimizing FSM <cmp_gn4124_core/cmp_l2p_dma_master/FSM_6> on signal <l2p_dma_current_state[1:3]> with user encoding.
----------------------------
- State         | Encoding
----------------------------
- l2p_idle      | 000
- l2p_wait_data | 001
- l2p_header    | 010
- l2p_addr_h    | 011
- l2p_addr_l    | 100
- l2p_data      | 101
- l2p_last_data | 110
- l2p_wait_rdy  | 111
----------------------------
-Analyzing FSM <MFsm> for best encoding.
-Optimizing FSM <cmp_gn4124_core/cmp_p2l_dma_master/FSM_7> on signal <p2l_dma_current_state[1:3]> with user encoding.
---------------------------------------
- State                    | Encoding
---------------------------------------
- p2l_idle                 | 000
- p2l_header               | 001
- p2l_addr_h               | 010
- p2l_addr_l               | 011
- p2l_wait_read_completion | 100
---------------------------------------
-Analyzing FSM <MFsm> for best encoding.
-Optimizing FSM <cmp_gn4124_core/cmp_clk_in/FSM_0> on signal <state[1:9]> with one-hot encoding.
---------------------
- State | Encoding
---------------------
- 0000  | 000000001
- 0001  | 000000010
- 0010  | 000000100
- 0011  | 000001000
- 0100  | 000010000
- 0101  | 000100000
- 0111  | 001000000
- 1001  | 010000000
- 0110  | 100000000
---------------------
-Analyzing FSM <MFsm> for best encoding.
-Optimizing FSM <cmp_gn4124_core/cmp_wbmaster32/FSM_3> on signal <l2p_read_cpl_current_state[1:2]> with user encoding.
-------------------------
- State      | Encoding
-------------------------
- l2p_idle   | 00
- l2p_header | 01
- l2p_data   | 10
-------------------------
-Analyzing FSM <MFsm> for best encoding.
-Optimizing FSM <cmp_gn4124_core/cmp_wbmaster32/FSM_4> on signal <wishbone_current_state[1:2]> with user encoding.
---------------------------
- State        | Encoding
---------------------------
- wb_idle      | 00
- wb_read_fifo | 01
- wb_cycle     | 10
- wb_wait_ack  | 11
---------------------------
-Analyzing FSM <MFsm> for best encoding.
-Optimizing FSM <cmp_gn4124_core/cmp_dma_controller/FSM_5> on signal <dma_ctrl_current_state[1:3]> with user encoding.
---------------------------------
- State              | Encoding
---------------------------------
- dma_idle           | 000
- dma_start_transfer | 001
- dma_transfer       | 010
- dma_start_chain    | 011
- dma_chain          | 100
- dma_error          | 101
- dma_abort          | 110
---------------------------------
-WARNING:Xst:1710 - FF/Latch <rddata_reg_8> (without init value) has a constant value of 0 in block <dummy_stat_regs_wb_slave>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_24> (without init value) has a constant value of 0 in block <dummy_stat_regs_wb_slave>. This FF/Latch will be trimmed during the optimization process.
-INFO:Xst:2261 - The FF/Latch <wb_sel_t_0> in Unit <wbmaster32> is equivalent to the following 3 FFs/Latches, which will be removed : <wb_sel_t_1> <wb_sel_t_2> <wb_sel_t_3> 
-INFO:Xst:2261 - The FF/Latch <wb_cyc_t> in Unit <wbmaster32> is equivalent to the following FF/Latch, which will be removed : <wb_stb_t> 
-
-Optimizing unit <pfc_wrapper> ...
-
-Optimizing unit <gn4124_core> ...
-
-Optimizing unit <p2l_des> ...
-
-Optimizing unit <serdes_1_to_n_data_s2_se_1> ...
-
-Optimizing unit <serdes_1_to_n_data_s2_se_2> ...
-
-Optimizing unit <l2p_dma_master> ...
-
-Optimizing unit <p2l_dma_master> ...
-
-Optimizing unit <serdes_1_to_n_clk_pll_s2_diff> ...
-
-Optimizing unit <wbmaster32> ...
-
-Optimizing unit <dma_controller> ...
-
-Optimizing unit <dma_controller_wb_slave> ...
-
-Optimizing unit <p2l_decode32> ...
-
-Optimizing unit <l2p_arbiter> ...
-
-Optimizing unit <serdes_n_to_1_s2_se_1> ...
-
-Optimizing unit <dummy_stat_regs_wb_slave> ...
-
-Optimizing unit <dummy_ctrl_regs_wb_slave> ...
-WARNING:Xst:1710 - FF/Latch <cmp_gn4124_core/cmp_p2l_des/cmp_valid_in/pdcounter_1> (without init value) has a constant value of 0 in block <pfc_wrapper>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <cmp_gn4124_core/cmp_p2l_des/cmp_valid_in/ce_data_inta> (without init value) has a constant value of 0 in block <pfc_wrapper>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <cmp_gn4124_core/cmp_p2l_des/cmp_valid_in/inc_data_int> (without init value) has a constant value of 0 in block <pfc_wrapper>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <cmp_gn4124_core/cmp_p2l_des/cmp_valid_in/ce_data_0> (without init value) has a constant value of 0 in block <pfc_wrapper>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <cmp_gn4124_core/cmp_p2l_des/cmp_dframe_in/pdcounter_1> (without init value) has a constant value of 0 in block <pfc_wrapper>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <cmp_gn4124_core/cmp_p2l_des/cmp_dframe_in/ce_data_inta> (without init value) has a constant value of 0 in block <pfc_wrapper>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <cmp_gn4124_core/cmp_p2l_des/cmp_dframe_in/inc_data_int> (without init value) has a constant value of 0 in block <pfc_wrapper>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <cmp_gn4124_core/cmp_p2l_des/cmp_dframe_in/ce_data_0> (without init value) has a constant value of 0 in block <pfc_wrapper>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/cal_data_sint> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/mux_15> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/mux_14> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/mux_13> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/mux_12> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/mux_11> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/mux_10> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/mux_9> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/mux_8> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/mux_7> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/mux_6> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/mux_5> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/mux_4> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/mux_3> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/mux_2> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/mux_1> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/mux_0> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_valid_in/cal_data_sint> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_dframe_in/cal_data_sint> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_31> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_30> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_29> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_28> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_27> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_26> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_25> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_24> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_23> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_22> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_21> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_20> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_19> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_18> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_17> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_16> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_15> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_14> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_13> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_12> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_11> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_29> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_28> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_27> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_26> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_25> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_24> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_23> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_22> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_21> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_20> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_19> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_18> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_17> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_16> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_15> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_14> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_13> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_12> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_11> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_sel_t_0> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_15> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_14> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_13> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_12> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_11> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_10> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_9> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_8> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_7> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_6> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_5> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_4> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_ctrl_len_o_1> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_ctrl_len_o_0> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_ctrl_carrier_addr_o_1> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_ctrl_carrier_addr_o_0> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_load_o> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_31> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_30> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_29> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_28> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_27> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_26> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_25> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_24> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_23> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_22> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_21> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_20> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_19> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_18> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_17> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_16> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_15> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_14> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_13> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_12> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_11> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_10> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_9> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_8> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_7> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_6> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_5> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_4> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_3> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_2> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_1> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_0> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_31> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_30> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_29> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_28> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_27> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_26> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_25> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_24> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_23> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_22> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_21> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_20> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_19> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_18> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_17> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_16> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_15> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_14> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_13> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_12> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_11> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_10> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_9> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_8> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_7> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_6> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_5> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_4> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_3> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_2> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_1> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_0> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_be_3> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_be_2> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_be_1> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_be_0> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_last> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_lbe_3> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_lbe_2> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_lbe_1> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_lbe_0> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_fbe_3> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_fbe_2> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_fbe_1> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_fbe_0> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_stat_1> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_stat_0> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_length_9> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_length_8> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_length_7> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_length_6> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_length_5> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_length_4> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_length_3> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_length_2> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_length_1> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_length_0> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_addr_1> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_valid_in/pdcounter_4> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_valid_in/pdcounter_3> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_valid_in/pdcounter_2> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_valid_in/pdcounter_0> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_dframe_in/pdcounter_4> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_dframe_in/pdcounter_3> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_dframe_in/pdcounter_2> of sequential type is unconnected in block <pfc_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_dframe_in/pdcounter_0> of sequential type is unconnected in block <pfc_wrapper>.
-
-Mapping all equations...
-Building and optimizing final netlist ...
-Found area constraint ratio of 100 (+ 5) on block pfc_wrapper, actual ratio is 5.
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2> in Unit <BU2> is equivalent to the following 2 FFs/Latches : <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1> <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2> in Unit <BU2> is equivalent to the following 2 FFs/Latches : <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1> <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2> in Unit <BU2> is equivalent to the following 2 FFs/Latches : <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1> <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2> in Unit <BU2> is equivalent to the following 2 FFs/Latches : <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1> <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2> in Unit <BU2> is equivalent to the following 2 FFs/Latches : <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1> <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2> in Unit <BU2> is equivalent to the following 2 FFs/Latches : <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1> <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2> in Unit <BU2> is equivalent to the following 2 FFs/Latches : <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1> <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2> in Unit <BU2> is equivalent to the following 2 FFs/Latches : <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1> <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2> in Unit <BU2> is equivalent to the following 2 FFs/Latches : <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1> <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2> in Unit <BU2> is equivalent to the following 2 FFs/Latches : <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1> <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0> 
-INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i> 
-
-Final Macro Processing ...
-
-Processing Unit <pfc_wrapper> :
-	Found 4-bit shift register for signal <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/ack_sreg_1>.
-Unit <pfc_wrapper> processed.
-
-=========================================================================
-Final Register Report
-
-Macro Statistics
-# Registers                                            : 2805
- Flip-Flops                                            : 2805
-# Shift Registers                                      : 1
- 4-bit shift register                                  : 1
-
-=========================================================================
-
-=========================================================================
-*                           Partition Report                            *
-=========================================================================
-
-Partition Implementation Status
--------------------------------
-
-  No Partitions were found in this design.
-
--------------------------------
-
-=========================================================================
-*                            Design Summary                             *
-=========================================================================
-
-Top Level Output File Name         : pfc_wrapper.ngc
-
-Primitive and Black Box Usage:
-------------------------------
-# BELS                             : 3127
-#      GND                         : 7
-#      INV                         : 72
-#      LUT1                        : 56
-#      LUT2                        : 331
-#      LUT3                        : 654
-#      LUT4                        : 389
-#      LUT5                        : 363
-#      LUT6                        : 512
-#      MUXCY                       : 438
-#      MUXF7                       : 13
-#      VCC                         : 7
-#      XORCY                       : 285
-# FlipFlops/Latches                : 3622
-#      FD                          : 23
-#      FDC                         : 950
-#      FDCE                        : 2484
-#      FDE                         : 31
-#      FDP                         : 72
-#      FDPE                        : 30
-#      LDC                         : 32
-# RAMS                             : 11
-#      RAMB16BWER                  : 11
-# Shift Registers                  : 1
-#      SRLC16E                     : 1
-# Clock Buffers                    : 3
-#      BUFG                        : 3
-# IO Buffers                       : 59
-#      BUFIO2                      : 1
-#      IBUF                        : 24
-#      IBUFDS                      : 3
-#      OBUF                        : 30
-#      OBUFDS                      : 1
-# Others                           : 62
-#      BUFIO2FB                    : 1
-#      BUFPLL                      : 1
-#      IODELAY2                    : 20
-#      ISERDES2                    : 20
-#      OSERDES2                    : 19
-#      PLL_ADV                     : 1
-
-Device utilization summary:
----------------------------
-
-Selected Device : 6slx150tfgg676-3 
-
-
-Slice Logic Utilization: 
- Number of Slice Registers:            3622  out of  184304     1%  
- Number of Slice LUTs:                 2378  out of  92152     2%  
-    Number used as Logic:              2377  out of  92152     2%  
-    Number used as Memory:                1  out of  21680     0%  
-       Number used as SRL:                1
-
-Slice Logic Distribution: 
- Number of LUT Flip Flop pairs used:   4463
-   Number with an unused Flip Flop:     841  out of   4463    18%  
-   Number with an unused LUT:          2085  out of   4463    46%  
-   Number of fully used LUT-FF pairs:  1537  out of   4463    34%  
-   Number of unique control sets:       169
-
-IO Utilization: 
- Number of IOs:                          68
- Number of bonded IOBs:                  62  out of    396    15%  
-
-Specific Feature Utilization:
- Number of Block RAM/FIFO:               11  out of    268     4%  
-    Number using Block RAM only:         11
- Number of BUFG/BUFGCTRLs:                3  out of     16    18%  
- Number of PLL_ADVs:                      1  out of      6    16%  
-
----------------------------
-Partition Resource Summary:
----------------------------
-
-  No Partitions were found in this design.
-
----------------------------
-
-
-=========================================================================
-Timing Report
-
-NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
-      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
-      GENERATED AFTER PLACE-and-ROUTE.
-
-Clock Information:
-------------------
--------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+-------+
-Clock Signal                                                                   | Clock buffer(FF name)                                                                                     | Load  |
--------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+-------+
-L_CLKp                                                                         | IBUFDS+BUFG                                                                                               | 1116  |
-cmp_gn4124_core/cmp_clk_in/buf_P_clk                                           | cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst:CLKOUT2                                                        | 2493  |
-cmp_gn4124_core/cmp_wbmaster32/_n0326(cmp_gn4124_core/cmp_wbmaster32/_n03261:O)| BUFG(*)(cmp_gn4124_core/cmp_wbmaster32/s_wb_dat_i_muxed_0)                                                | 32    |
-cmp_test_ram/BU2/doutb(0)                                                      | NONE(cmp_test_ram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SP.SIMPLE_PRIM18.ram)| 4     |
--------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+-------+
-(*) This 1 clock signal(s) are generated by combinatorial logic,
-and XST is not able to identify which are the primary clock signals.
-Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
-INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
-
-Asynchronous Control Signals Information:
-----------------------------------------
-No asynchronous control signals found in this design
-
-Timing Summary:
----------------
-Speed Grade: -3
-
-   Minimum period: 6.848ns (Maximum Frequency: 146.022MHz)
-   Minimum input arrival time before clock: 4.574ns
-   Maximum output required time after clock: 4.828ns
-   Maximum combinational path delay: 4.115ns
-
-Timing Details:
----------------
-All values displayed in nanoseconds (ns)
-
-=========================================================================
-Timing constraint: Default period analysis for Clock 'L_CLKp'
-  Clock period: 5.849ns (frequency: 170.962MHz)
-  Total number of paths / destination ports: 9719 / 2378
--------------------------------------------------------------------------
-Delay:               5.849ns (Levels of Logic = 4)
-  Source:            cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/ack_sreg_1 (FF)
-  Destination:       cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_31 (FF)
-  Source Clock:      L_CLKp rising
-  Destination Clock: L_CLKp rising
-
-  Data Path: cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/ack_sreg_1 to cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_31
-                                Gate     Net
-    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
-    ----------------------------------------  ------------
-     FDCE:C->Q            56   0.525   1.588  cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/ack_sreg_1 (cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/ack_sreg_1)
-     LUT2:I1->O           31   0.254   1.506  cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/ack_sreg[1]_dma_cstart_lw_read_in_progress_AND_109_o1 (cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/ack_sreg[1]_dma_cstart_lw_read_in_progress_AND_109_o)
-     LUT6:I3->O            1   0.235   0.580  cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/Mmux_rddata_reg[31]_dma_attrib_int_read[31]_mux_12_OUT962 (cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/Mmux_rddata_reg[31]_dma_attrib_int_read[31]_mux_12_OUT961)
-     LUT6:I5->O            1   0.254   0.580  cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/Mmux_rddata_reg[31]_dma_attrib_int_read[31]_mux_12_OUT963 (cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/Mmux_rddata_reg[31]_dma_attrib_int_read[31]_mux_12_OUT962)
-     LUT6:I5->O            1   0.254   0.000  cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/Mmux_rddata_reg[31]_dma_attrib_int_read[31]_mux_12_OUT964 (cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg[31]_dma_attrib_int_read[31]_mux_12_OUT<9>)
-     FDCE:D                    0.074          cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_9
-    ----------------------------------------
-    Total                      5.849ns (1.596ns logic, 4.253ns route)
-                                       (27.3% logic, 72.7% route)
-
-=========================================================================
-Timing constraint: Default period analysis for Clock 'cmp_gn4124_core/cmp_clk_in/buf_P_clk'
-  Clock period: 6.848ns (frequency: 146.022MHz)
-  Total number of paths / destination ports: 31681 / 6549
--------------------------------------------------------------------------
-Delay:               6.848ns (Levels of Logic = 3)
-  Source:            cmp_gn4124_core/cmp_dma_controller/dma_len_reg_27 (FF)
-  Destination:       cmp_gn4124_core/cmp_dma_controller/dma_ctrl_carrier_addr_o_31 (FF)
-  Source Clock:      cmp_gn4124_core/cmp_clk_in/buf_P_clk rising +90
-  Destination Clock: cmp_gn4124_core/cmp_clk_in/buf_P_clk rising +90
-
-  Data Path: cmp_gn4124_core/cmp_dma_controller/dma_len_reg_27 to cmp_gn4124_core/cmp_dma_controller/dma_ctrl_carrier_addr_o_31
-                                Gate     Net
-    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
-    ----------------------------------------  ------------
-     FDCE:C->Q             3   0.525   1.106  cmp_gn4124_core/cmp_dma_controller/dma_len_reg_27 (cmp_gn4124_core/cmp_dma_controller/dma_len_reg_27)
-     LUT6:I0->O            1   0.254   1.010  cmp_gn4124_core/cmp_dma_controller/_n0212_inv31 (cmp_gn4124_core/cmp_dma_controller/_n0212_inv3)
-     LUT5:I0->O          101   0.254   1.880  cmp_gn4124_core/cmp_dma_controller/_n0212_inv36 (cmp_gn4124_core/cmp_dma_controller/_n0212_inv_bdd2)
-     LUT4:I3->O           30   0.254   1.263  cmp_gn4124_core/cmp_dma_controller/_n0212_inv11 (cmp_gn4124_core/cmp_dma_controller/_n0212_inv)
-     FDCE:CE                   0.302          cmp_gn4124_core/cmp_dma_controller/dma_ctrl_carrier_addr_o_2
-    ----------------------------------------
-    Total                      6.848ns (1.589ns logic, 5.259ns route)
-                                       (23.2% logic, 76.8% route)
-
-=========================================================================
-Timing constraint: Default OFFSET IN BEFORE for Clock 'L_CLKp'
-  Total number of paths / destination ports: 201 / 201
--------------------------------------------------------------------------
-Offset:              4.574ns (Levels of Logic = 2)
-  Source:            L_RST_N (PAD)
-  Destination:       dma_ack_i (FF)
-  Destination Clock: L_CLKp rising
-
-  Data Path: L_RST_N to dma_ack_i
-                                Gate     Net
-    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
-    ----------------------------------------  ------------
-     IBUF:I->O             1   1.228   0.579  L_RST_N_IBUF (L_RST_N_IBUF)
-     INV:I->O            201   0.255   2.053  L_RST_N_inv1_INV_0 (L_RST_N_inv)
-     FDC:CLR                   0.459          dma_ack_i
-    ----------------------------------------
-    Total                      4.574ns (1.942ns logic, 2.632ns route)
-                                       (42.5% logic, 57.5% route)
-
-=========================================================================
-Timing constraint: Default OFFSET IN BEFORE for Clock 'cmp_gn4124_core/cmp_clk_in/buf_P_clk'
-  Total number of paths / destination ports: 63 / 63
--------------------------------------------------------------------------
-Offset:              4.574ns (Levels of Logic = 2)
-  Source:            L_RST_N (PAD)
-  Destination:       cmp_gn4124_core/rst_reg (FF)
-  Destination Clock: cmp_gn4124_core/cmp_clk_in/buf_P_clk rising +90
-
-  Data Path: L_RST_N to cmp_gn4124_core/rst_reg
-                                Gate     Net
-    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
-    ----------------------------------------  ------------
-     IBUF:I->O             1   1.228   0.579  L_RST_N_IBUF (L_RST_N_IBUF)
-     INV:I->O            201   0.255   2.053  L_RST_N_inv1_INV_0 (L_RST_N_inv)
-     FDCE:CLR                  0.459          cmp_gn4124_core/rst_reg
-    ----------------------------------------
-    Total                      4.574ns (1.942ns logic, 2.632ns route)
-                                       (42.5% logic, 57.5% route)
-
-=========================================================================
-Timing constraint: Default OFFSET OUT AFTER for Clock 'cmp_gn4124_core/cmp_clk_in/buf_P_clk'
-  Total number of paths / destination ports: 119 / 117
--------------------------------------------------------------------------
-Offset:              4.828ns (Levels of Logic = 3)
-  Source:            cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i (FF)
-  Destination:       P2L_RDY (PAD)
-  Source Clock:      cmp_gn4124_core/cmp_clk_in/buf_P_clk rising +90
-
-  Data Path: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i to P2L_RDY
-                                Gate     Net
-    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
-    ----------------------------------------  ------------
-     FDP:C->Q              3   0.525   0.759  U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i (prog_full)
-     end scope: 'BU2'
-     end scope: 'cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb'
-     LUT2:I0->O            1   0.250   0.579  cmp_gn4124_core/p2l_rdy_o1 (P2L_RDY_OBUF)
-     OBUF:I->O                 2.715          P2L_RDY_OBUF (P2L_RDY)
-    ----------------------------------------
-    Total                      4.828ns (3.490ns logic, 1.338ns route)
-                                       (72.3% logic, 27.7% route)
-
-=========================================================================
-Timing constraint: Default OFFSET OUT AFTER for Clock 'L_CLKp'
-  Total number of paths / destination ports: 3 / 3
--------------------------------------------------------------------------
-Offset:              3.856ns (Levels of Logic = 1)
-  Source:            cmp_dummy_ctrl_regs/dummy_reg_led_int_0 (FF)
-  Destination:       LED_RED (PAD)
-  Source Clock:      L_CLKp rising
-
-  Data Path: cmp_dummy_ctrl_regs/dummy_reg_led_int_0 to LED_RED
-                                Gate     Net
-    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
-    ----------------------------------------  ------------
-     FDCE:C->Q             2   0.525   0.616  cmp_dummy_ctrl_regs/dummy_reg_led_int_0 (cmp_dummy_ctrl_regs/dummy_reg_led_int_0)
-     OBUF:I->O                 2.715          LED_RED_OBUF (LED_RED)
-    ----------------------------------------
-    Total                      3.856ns (3.240ns logic, 0.616ns route)
-                                       (84.0% logic, 16.0% route)
-
-=========================================================================
-Timing constraint: Default path analysis
-  Total number of paths / destination ports: 165 / 163
--------------------------------------------------------------------------
-Delay:               4.115ns (Levels of Logic = 2)
-  Source:            L_RST_N (PAD)
-  Destination:       cmp_gn4124_core/cmp_clk_in/iserdes_s:RST (PAD)
-
-  Data Path: L_RST_N to cmp_gn4124_core/cmp_clk_in/iserdes_s:RST
-                                Gate     Net
-    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
-    ----------------------------------------  ------------
-     IBUF:I->O             1   1.228   0.579  L_RST_N_IBUF (L_RST_N_IBUF)
-     INV:I->O            201   0.255   2.053  L_RST_N_inv1_INV_0 (L_RST_N_inv)
-    ISERDES2:RST               0.000          cmp_gn4124_core/cmp_clk_in/iserdes_m
-    ----------------------------------------
-    Total                      4.115ns (1.483ns logic, 2.632ns route)
-                                       (36.0% logic, 64.0% route)
-
-=========================================================================
-
-
-Total REAL time to Xst completion: 87.00 secs
-Total CPU time to Xst completion: 86.97 secs
- 
---> 
-
-
-Total memory usage is 181284 kilobytes
-
-Number of errors   :    0 (   0 filtered)
-Number of warnings :  434 (   0 filtered)
-Number of infos    :   80 (   0 filtered)
-
diff --git a/hdl/pfc/ise_project/pfc_wrapper.twr b/hdl/pfc/ise_project/pfc_wrapper.twr
deleted file mode 100644
index 65bc66d4349c924506b7bc3778cfbc731a1dc569..0000000000000000000000000000000000000000
--- a/hdl/pfc/ise_project/pfc_wrapper.twr
+++ /dev/null
@@ -1,870 +0,0 @@
---------------------------------------------------------------------------------
-Release 12.2 Trace  (lin)
-Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
-
-/opt/Xilinx/12.2/ISE_DS/ISE/bin/lin/unwrapped/trce -intstyle ise -v 3 -s 3 -n 3
--fastpaths -xml pfc_wrapper.twx pfc_wrapper.ncd -o pfc_wrapper.twr
-pfc_wrapper.pcf
-
-Design file:              pfc_wrapper.ncd
-Physical constraint file: pfc_wrapper.pcf
-Device,package,speed:     xc6slx150t,fgg676,C,-3 (PRELIMINARY 1.10 2010-06-28)
-Report level:             verbose report
-
-Environment Variable      Effect 
---------------------      ------ 
-NONE                      No environment variables were set
---------------------------------------------------------------------------------
-
-INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more 
-   information, see the TSI report.  Please consult the Xilinx Command Line 
-   Tools User Guide for information on generating a TSI report.
-INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
-   option. All paths that are not constrained will be reported in the 
-   unconstrained paths section(s) of the report.
-INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
-   a 50 Ohm transmission line loading model.  For the details of this model, 
-   and for more information on accounting for different loading conditions, 
-   please see the device datasheet.
-
-================================================================================
-Timing constraint: NET "L2P_RDY_IBUF" MAXDELAY = 2 ns;
-
- 1 net analyzed, 0 failing nets detected.
- 0 timing errors detected.
- Maximum net delay is   0.324ns.
---------------------------------------------------------------------------------
-Slack:                  1.676ns L2P_RDY_IBUF
-Report:    0.324ns delay meets   2.000ns timing constraint by 1.676ns
-From                              To                                Delay(ns)
-U9.I                              ILOGIC_X0Y41.D                        0.324  
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: NET "L_WR_RDY_1_IBUF" MAXDELAY = 2 ns;
-
- 0 nets analyzed, 0 failing nets detected.
- 0 timing errors detected.
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: NET "L_WR_RDY_1_IBUF" MAXDELAY = 2 ns;
-
- 1 net analyzed, 0 failing nets detected.
- 0 timing errors detected.
- Maximum net delay is   0.324ns.
---------------------------------------------------------------------------------
-Slack:                  1.676ns L_WR_RDY_1_IBUF
-Report:    0.324ns delay meets   2.000ns timing constraint by 1.676ns
-From                              To                                Delay(ns)
-R4.I                              ILOGIC_X0Y109.D                       0.324  
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: NET "L_WR_RDY_0_IBUF" MAXDELAY = 2 ns;
-
- 0 nets analyzed, 0 failing nets detected.
- 0 timing errors detected.
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: NET "L_WR_RDY_0_IBUF" MAXDELAY = 2 ns;
-
- 1 net analyzed, 0 failing nets detected.
- 0 timing errors detected.
- Maximum net delay is   0.324ns.
---------------------------------------------------------------------------------
-Slack:                  1.676ns L_WR_RDY_0_IBUF
-Report:    0.324ns delay meets   2.000ns timing constraint by 1.676ns
-From                              To                                Delay(ns)
-V7.I                              ILOGIC_X0Y21.D                        0.324  
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: NET "P_RD_D_RDY_1_IBUF" MAXDELAY = 2 ns;
-
- 1 net analyzed, 0 failing nets detected.
- 0 timing errors detected.
- Maximum net delay is   0.324ns.
---------------------------------------------------------------------------------
-Slack:                  1.676ns P_RD_D_RDY_1_IBUF
-Report:    0.324ns delay meets   2.000ns timing constraint by 1.676ns
-From                              To                                Delay(ns)
-U5.I                              ILOGIC_X0Y97.D                        0.324  
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: NET "P_RD_D_RDY_0_IBUF" MAXDELAY = 2 ns;
-
- 1 net analyzed, 0 failing nets detected.
- 0 timing errors detected.
- Maximum net delay is   0.324ns.
---------------------------------------------------------------------------------
-Slack:                  1.676ns P_RD_D_RDY_0_IBUF
-Report:    0.324ns delay meets   2.000ns timing constraint by 1.676ns
-From                              To                                Delay(ns)
-U2.I                              ILOGIC_X0Y85.D                        0.324  
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: NET "VC_RDY<1>_IBUF" MAXDELAY = 2 ns;
-
- 0 nets analyzed, 0 failing nets detected.
- 0 timing errors detected.
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: NET "VC_RDY<1>_IBUF" MAXDELAY = 2 ns;
-
- 1 net analyzed, 0 failing nets detected.
- 0 timing errors detected.
- Maximum net delay is   0.000ns.
---------------------------------------------------------------------------------
-Slack:                  2.000ns VC_RDY<1>_IBUF
-Report:    0.000ns delay meets   2.000ns timing constraint by 2.000ns
-From                              To                                Delay(ns)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: NET "VC_RDY<0>_IBUF" MAXDELAY = 2 ns;
-
- 0 nets analyzed, 0 failing nets detected.
- 0 timing errors detected.
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: NET "VC_RDY<0>_IBUF" MAXDELAY = 2 ns;
-
- 1 net analyzed, 0 failing nets detected.
- 0 timing errors detected.
- Maximum net delay is   0.000ns.
---------------------------------------------------------------------------------
-Slack:                  2.000ns VC_RDY<0>_IBUF
-Report:    0.000ns delay meets   2.000ns timing constraint by 2.000ns
-From                              To                                Delay(ns)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TS_l_clkp = PERIOD TIMEGRP "l_clkp_grp" 5 ns HIGH 50%;
-
- 9309 paths analyzed, 3250 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
- Minimum period is   4.795ns.
---------------------------------------------------------------------------------
-
-Paths for end point cmp_dummy_ctrl_regs/dummy_reg_3_int_6 (SLICE_X56Y72.CX), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.205ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               cmp_gn4124_core/cmp_wbmaster32/wb_dat_o_t_6 (FF)
-  Destination:          cmp_dummy_ctrl_regs/dummy_reg_3_int_6 (FF)
-  Requirement:          5.000ns
-  Data Path Delay:      4.804ns (Levels of Logic = 0)
-  Clock Path Skew:      0.044ns (0.893 - 0.849)
-  Source Clock:         l_clk_BUFG rising at 0.000ns
-  Destination Clock:    l_clk_BUFG rising at 5.000ns
-  Clock Uncertainty:    0.035ns
-
-  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
-    Total System Jitter (TSJ):  0.070ns
-    Total Input Jitter (TIJ):   0.000ns
-    Discrete Jitter (DJ):       0.000ns
-    Phase Error (PE):           0.000ns
-
-  Maximum Data Path at Slow Process Corner: cmp_gn4124_core/cmp_wbmaster32/wb_dat_o_t_6 to cmp_dummy_ctrl_regs/dummy_reg_3_int_6
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X43Y48.CQ      Tcko                  0.430   cmp_gn4124_core/cmp_wbmaster32/wb_dat_o_t<7>
-                                                       cmp_gn4124_core/cmp_wbmaster32/wb_dat_o_t_6
-    SLICE_X56Y72.CX      net (fanout=12)       4.289   cmp_gn4124_core/cmp_wbmaster32/wb_dat_o_t<6>
-    SLICE_X56Y72.CLK     Tdick                 0.085   cmp_dummy_ctrl_regs/dummy_reg_3_int<7>
-                                                       cmp_dummy_ctrl_regs/dummy_reg_3_int_6
-    -------------------------------------------------  ---------------------------
-    Total                                      4.804ns (0.515ns logic, 4.289ns route)
-                                                       (10.7% logic, 89.3% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_dummy_ctrl_regs/dummy_reg_3_int_20 (SLICE_X50Y72.AX), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.207ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               cmp_gn4124_core/cmp_wbmaster32/wb_dat_o_t_20 (FF)
-  Destination:          cmp_dummy_ctrl_regs/dummy_reg_3_int_20 (FF)
-  Requirement:          5.000ns
-  Data Path Delay:      4.802ns (Levels of Logic = 0)
-  Clock Path Skew:      0.044ns (0.892 - 0.848)
-  Source Clock:         l_clk_BUFG rising at 0.000ns
-  Destination Clock:    l_clk_BUFG rising at 5.000ns
-  Clock Uncertainty:    0.035ns
-
-  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
-    Total System Jitter (TSJ):  0.070ns
-    Total Input Jitter (TIJ):   0.000ns
-    Discrete Jitter (DJ):       0.000ns
-    Phase Error (PE):           0.000ns
-
-  Maximum Data Path at Slow Process Corner: cmp_gn4124_core/cmp_wbmaster32/wb_dat_o_t_20 to cmp_dummy_ctrl_regs/dummy_reg_3_int_20
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X42Y49.AMUX    Tshcko                0.535   cmp_gn4124_core/cmp_wbmaster32/wb_dat_o_t<11>
-                                                       cmp_gn4124_core/cmp_wbmaster32/wb_dat_o_t_20
-    SLICE_X50Y72.AX      net (fanout=12)       4.153   cmp_gn4124_core/cmp_wbmaster32/wb_dat_o_t<20>
-    SLICE_X50Y72.CLK     Tdick                 0.114   cmp_dummy_ctrl_regs/dummy_reg_3_int<23>
-                                                       cmp_dummy_ctrl_regs/dummy_reg_3_int_20
-    -------------------------------------------------  ---------------------------
-    Total                                      4.802ns (0.649ns logic, 4.153ns route)
-                                                       (13.5% logic, 86.5% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_0 (SLICE_X70Y73.AX), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.207ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_dma_master/cmp_addr_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram (RAM)
-  Destination:          cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_0 (FF)
-  Requirement:          5.000ns
-  Data Path Delay:      4.545ns (Levels of Logic = 0)
-  Clock Path Skew:      -0.213ns (0.715 - 0.928)
-  Source Clock:         l_clk_BUFG rising at 0.000ns
-  Destination Clock:    l_clk_BUFG rising at 5.000ns
-  Clock Uncertainty:    0.035ns
-
-  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
-    Total System Jitter (TSJ):  0.070ns
-    Total Input Jitter (TIJ):   0.000ns
-    Discrete Jitter (DJ):       0.000ns
-    Phase Error (PE):           0.000ns
-
-  Maximum Data Path at Slow Process Corner: cmp_gn4124_core/cmp_l2p_dma_master/cmp_addr_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram to cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    RAMB16_X2Y38.DOB0    Trcko_DOB             2.100   cmp_gn4124_core/cmp_l2p_dma_master/cmp_addr_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/cmp_addr_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram
-    SLICE_X70Y73.AX      net (fanout=1)        2.331   cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_dout<0>
-    SLICE_X70Y73.CLK     Tdick                 0.114   cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<2>
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_0
-    -------------------------------------------------  ---------------------------
-    Total                                      4.545ns (2.214ns logic, 2.331ns route)
-                                                       (48.7% logic, 51.3% route)
-
---------------------------------------------------------------------------------
-
-Hold Paths: TS_l_clkp = PERIOD TIMEGRP "l_clkp_grp" 5 ns HIGH 50%;
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_6 (SLICE_X24Y38.C5), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.382ns (requirement - (clock path skew + uncertainty - data path))
-  Source:               cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_6 (FF)
-  Destination:          cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_6 (FF)
-  Requirement:          0.000ns
-  Data Path Delay:      0.382ns (Levels of Logic = 1)
-  Clock Path Skew:      0.000ns
-  Source Clock:         l_clk_BUFG rising at 5.000ns
-  Destination Clock:    l_clk_BUFG rising at 5.000ns
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path at Fast Process Corner: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_6 to cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_6
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X24Y38.CQ      Tcko                  0.200   cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg<7>
-                                                       cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_6
-    SLICE_X24Y38.C5      net (fanout=1)        0.061   cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg<6>
-    SLICE_X24Y38.CLK     Tah         (-Th)    -0.121   cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg<7>
-                                                       cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg<6>_rt
-                                                       cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_6
-    -------------------------------------------------  ---------------------------
-    Total                                      0.382ns (0.321ns logic, 0.061ns route)
-                                                       (84.0% logic, 16.0% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/BU2/U0/grf.rf/gl0.wr/wpntr/gic0.gc1.count_d3_8 (SLICE_X16Y82.DX), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.392ns (requirement - (clock path skew + uncertainty - data path))
-  Source:               cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/BU2/U0/grf.rf/gl0.wr/wpntr/gic0.gc1.count_d2_8 (FF)
-  Destination:          cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/BU2/U0/grf.rf/gl0.wr/wpntr/gic0.gc1.count_d3_8 (FF)
-  Requirement:          0.000ns
-  Data Path Delay:      0.392ns (Levels of Logic = 0)
-  Clock Path Skew:      0.000ns
-  Source Clock:         l_clk_BUFG rising at 5.000ns
-  Destination Clock:    l_clk_BUFG rising at 5.000ns
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path at Fast Process Corner: cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/BU2/U0/grf.rf/gl0.wr/wpntr/gic0.gc1.count_d2_8 to cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/BU2/U0/grf.rf/gl0.wr/wpntr/gic0.gc1.count_d3_8
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X16Y82.CQ      Tcko                  0.200   cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/BU2/U0/grf.rf/gl0.wr/wpntr/gic0.gc1.count_d3<8>
-                                                       cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/BU2/U0/grf.rf/gl0.wr/wpntr/gic0.gc1.count_d2_8
-    SLICE_X16Y82.DX      net (fanout=2)        0.144   cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/BU2/U0/grf.rf/gl0.wr/wpntr/gic0.gc1.count_d2<8>
-    SLICE_X16Y82.CLK     Tckdi       (-Th)    -0.048   cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/BU2/U0/grf.rf/gl0.wr/wpntr/gic0.gc1.count_d3<8>
-                                                       cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/BU2/U0/grf.rf/gl0.wr/wpntr/gic0.gc1.count_d3_8
-    -------------------------------------------------  ---------------------------
-    Total                                      0.392ns (0.248ns logic, 0.144ns route)
-                                                       (63.3% logic, 36.7% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_5 (SLICE_X24Y38.B5), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.392ns (requirement - (clock path skew + uncertainty - data path))
-  Source:               cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_5 (FF)
-  Destination:          cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_5 (FF)
-  Requirement:          0.000ns
-  Data Path Delay:      0.392ns (Levels of Logic = 1)
-  Clock Path Skew:      0.000ns
-  Source Clock:         l_clk_BUFG rising at 5.000ns
-  Destination Clock:    l_clk_BUFG rising at 5.000ns
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path at Fast Process Corner: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_5 to cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_5
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X24Y38.BQ      Tcko                  0.200   cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg<7>
-                                                       cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_5
-    SLICE_X24Y38.B5      net (fanout=1)        0.071   cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg<5>
-    SLICE_X24Y38.CLK     Tah         (-Th)    -0.121   cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg<7>
-                                                       cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg<5>_rt
-                                                       cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_5
-    -------------------------------------------------  ---------------------------
-    Total                                      0.392ns (0.321ns logic, 0.071ns route)
-                                                       (81.9% logic, 18.1% route)
-
---------------------------------------------------------------------------------
-
-Component Switching Limit Checks: TS_l_clkp = PERIOD TIMEGRP "l_clkp_grp" 5 ns HIGH 50%;
---------------------------------------------------------------------------------
-Slack: 1.430ns (period - min period limit)
-  Period: 5.000ns
-  Min period limit: 3.570ns (280.112MHz) (Trper_CLKA(Fmax))
-  Physical resource: cmp_test_ram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/SP.SIMPLE_PRIM18.ram/CLKA
-  Logical resource: cmp_test_ram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/SP.SIMPLE_PRIM18.ram/CLKA
-  Location pin: RAMB16_X3Y34.CLKA
-  Clock network: l_clk_BUFG
---------------------------------------------------------------------------------
-Slack: 1.430ns (period - min period limit)
-  Period: 5.000ns
-  Min period limit: 3.570ns (280.112MHz) (Trper_CLKA(Fmax))
-  Physical resource: cmp_test_ram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/SP.SIMPLE_PRIM18.ram/CLKA
-  Logical resource: cmp_test_ram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/SP.SIMPLE_PRIM18.ram/CLKA
-  Location pin: RAMB16_X3Y38.CLKA
-  Clock network: l_clk_BUFG
---------------------------------------------------------------------------------
-Slack: 1.430ns (period - min period limit)
-  Period: 5.000ns
-  Min period limit: 3.570ns (280.112MHz) (Trper_CLKA(Fmax))
-  Physical resource: cmp_test_ram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SP.SIMPLE_PRIM18.ram/CLKA
-  Logical resource: cmp_test_ram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SP.SIMPLE_PRIM18.ram/CLKA
-  Location pin: RAMB16_X3Y36.CLKA
-  Clock network: l_clk_BUFG
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TS_p2l_clkp = PERIOD TIMEGRP "p2l_clkp_grp" 5 ns HIGH 50%;
-
- 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 component switching limit errors)
- Minimum period is   1.904ns.
---------------------------------------------------------------------------------
-
-Component Switching Limit Checks: TS_p2l_clkp = PERIOD TIMEGRP "p2l_clkp_grp" 5 ns HIGH 50%;
---------------------------------------------------------------------------------
-Slack: 3.096ns (period - min period limit)
-  Period: 5.000ns
-  Min period limit: 1.904ns (525.210MHz) (Tbufper_I)
-  Physical resource: cmp_gn4124_core/cmp_clk_in/P_clk_bufio2_inst/I
-  Logical resource: cmp_gn4124_core/cmp_clk_in/P_clk_bufio2_inst/I
-  Location pin: BUFIO2_X1Y9.I
-  Clock network: cmp_gn4124_core/cmp_clk_in/P_clk
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TS_p2l_clkn = PERIOD TIMEGRP "p2l_clkn_grp" 5 ns HIGH 50%;
-
- 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 component switching limit errors)
- Minimum period is   1.904ns.
---------------------------------------------------------------------------------
-
-Component Switching Limit Checks: TS_p2l_clkn = PERIOD TIMEGRP "p2l_clkn_grp" 5 ns HIGH 50%;
---------------------------------------------------------------------------------
-Slack: 3.096ns (period - min period limit)
-  Period: 5.000ns
-  Min period limit: 1.904ns (525.210MHz) (Tbufper_I)
-  Physical resource: cmp_gn4124_core/cmp_clk_in/P_clk_bufio2_inst/I
-  Logical resource: cmp_gn4124_core/cmp_clk_in/P_clk_bufio2_inst/I
-  Location pin: BUFIO2_X1Y9.I
-  Clock network: cmp_gn4124_core/cmp_clk_in/P_clk
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk = PERIOD TIMEGRP     
-    "cmp_gn4124_core_cmp_clk_in_buf_P_clk" TS_p2l_clkp HIGH 50%;
-
- 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 component switching limit errors)
- Minimum period is   2.800ns.
---------------------------------------------------------------------------------
-
-Component Switching Limit Checks: TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk = PERIOD TIMEGRP
-        "cmp_gn4124_core_cmp_clk_in_buf_P_clk" TS_p2l_clkp HIGH 50%;
---------------------------------------------------------------------------------
-Slack: 1.549ns (period - min period limit)
-  Period: 2.500ns
-  Min period limit: 0.951ns (1051.525MHz) (Tpllper_CLKOUT(Foutmax))
-  Physical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKOUT0
-  Logical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKOUT0
-  Location pin: PLL_ADV_X0Y0.CLKOUT0
-  Clock network: cmp_gn4124_core/cmp_clk_in/rx_pllout_xs_int
---------------------------------------------------------------------------------
-Slack: 2.200ns (period - (min low pulse limit / (low pulse / period)))
-  Period: 5.000ns
-  Low pulse: 2.500ns
-  Low pulse limit: 1.400ns (Tdcmpw_CLKIN_200_250)
-  Physical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKIN1
-  Logical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKIN1
-  Location pin: PLL_ADV_X0Y0.CLKIN2
-  Clock network: cmp_gn4124_core/cmp_clk_in/buf_P_clk
---------------------------------------------------------------------------------
-Slack: 2.200ns (period - (min high pulse limit / (high pulse / period)))
-  Period: 5.000ns
-  High pulse: 2.500ns
-  High pulse limit: 1.400ns (Tdcmpw_CLKIN_200_250)
-  Physical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKIN1
-  Logical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKIN1
-  Location pin: PLL_ADV_X0Y0.CLKIN2
-  Clock network: cmp_gn4124_core/cmp_clk_in/buf_P_clk
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk_0 = PERIOD TIMEGRP   
-      "cmp_gn4124_core_cmp_clk_in_buf_P_clk_0" TS_p2l_clkn HIGH 50%;
-
- 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 component switching limit errors)
- Minimum period is   2.800ns.
---------------------------------------------------------------------------------
-
-Component Switching Limit Checks: TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk_0 = PERIOD TIMEGRP
-        "cmp_gn4124_core_cmp_clk_in_buf_P_clk_0" TS_p2l_clkn HIGH 50%;
---------------------------------------------------------------------------------
-Slack: 1.549ns (period - min period limit)
-  Period: 2.500ns
-  Min period limit: 0.951ns (1051.525MHz) (Tpllper_CLKOUT(Foutmax))
-  Physical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKOUT0
-  Logical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKOUT0
-  Location pin: PLL_ADV_X0Y0.CLKOUT0
-  Clock network: cmp_gn4124_core/cmp_clk_in/rx_pllout_xs_int
---------------------------------------------------------------------------------
-Slack: 2.200ns (period - (min low pulse limit / (low pulse / period)))
-  Period: 5.000ns
-  Low pulse: 2.500ns
-  Low pulse limit: 1.400ns (Tdcmpw_CLKIN_200_250)
-  Physical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKIN1
-  Logical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKIN1
-  Location pin: PLL_ADV_X0Y0.CLKIN2
-  Clock network: cmp_gn4124_core/cmp_clk_in/buf_P_clk
---------------------------------------------------------------------------------
-Slack: 2.200ns (period - (min high pulse limit / (high pulse / period)))
-  Period: 5.000ns
-  High pulse: 2.500ns
-  High pulse limit: 1.400ns (Tdcmpw_CLKIN_200_250)
-  Physical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKIN1
-  Logical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKIN1
-  Location pin: PLL_ADV_X0Y0.CLKIN2
-  Clock network: cmp_gn4124_core/cmp_clk_in/buf_P_clk
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_xs_int = PERIOD 
-TIMEGRP         "cmp_gn4124_core_cmp_clk_in_rx_pllout_xs_int"         
-TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk / 2 HIGH 50%;
-
- 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 component switching limit errors)
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x1 = PERIOD TIMEGRP  
-       "cmp_gn4124_core_cmp_clk_in_rx_pllout_x1"         
-TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk PHASE 1.25 ns HIGH 50%;
-
- 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 component switching limit errors)
- Minimum period is   3.570ns.
---------------------------------------------------------------------------------
-
-Component Switching Limit Checks: TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x1 = PERIOD TIMEGRP
-        "cmp_gn4124_core_cmp_clk_in_rx_pllout_x1"
-        TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk PHASE 1.25 ns HIGH 50%;
---------------------------------------------------------------------------------
-Slack: 1.430ns (period - min period limit)
-  Period: 5.000ns
-  Min period limit: 3.570ns (280.112MHz) (Trper_CLKA(Fmax))
-  Physical resource: cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA
-  Logical resource: cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA
-  Location pin: RAMB16_X3Y20.CLKA
-  Clock network: cmp_gn4124_core/sys_clk
---------------------------------------------------------------------------------
-Slack: 1.430ns (period - min period limit)
-  Period: 5.000ns
-  Min period limit: 3.570ns (280.112MHz) (Trper_CLKA(Fmax))
-  Physical resource: cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA
-  Logical resource: cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA
-  Location pin: RAMB16_X3Y22.CLKA
-  Clock network: cmp_gn4124_core/sys_clk
---------------------------------------------------------------------------------
-Slack: 1.430ns (period - min period limit)
-  Period: 5.000ns
-  Min period limit: 3.570ns (280.112MHz) (Trper_CLKA(Fmax))
-  Physical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA
-  Logical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA
-  Location pin: RAMB16_X2Y22.CLKA
-  Clock network: cmp_gn4124_core/sys_clk
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_xs_int_0 = PERIOD 
-TIMEGRP         "cmp_gn4124_core_cmp_clk_in_rx_pllout_xs_int_0"         
-TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk_0 / 2 HIGH 50%;
-
- 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 component switching limit errors)
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x1_0 = PERIOD 
-TIMEGRP         "cmp_gn4124_core_cmp_clk_in_rx_pllout_x1_0"         
-TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk_0 PHASE 1.25 ns HIGH 50%;
-
- 29021 paths analyzed, 8719 endpoints analyzed, 1 failing endpoint
- 1 timing error detected. (1 setup error, 0 hold errors, 0 component switching limit errors)
- Minimum period is   5.579ns.
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/l2p_rdy (SLICE_X32Y70.CX), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     -0.579ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               cmp_gn4124_core/l2p_rdy_t (FF)
-  Destination:          cmp_gn4124_core/l2p_rdy (FF)
-  Requirement:          5.000ns
-  Data Path Delay:      5.065ns (Levels of Logic = 0)
-  Clock Path Skew:      -0.439ns (0.892 - 1.331)
-  Source Clock:         cmp_gn4124_core/sys_clk rising at 1.250ns
-  Destination Clock:    cmp_gn4124_core/sys_clk rising at 6.250ns
-  Clock Uncertainty:    0.075ns
-
-  Clock Uncertainty:          0.075ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
-    Total System Jitter (TSJ):  0.070ns
-    Discrete Jitter (DJ):       0.132ns
-    Phase Error (PE):           0.000ns
-
-  Maximum Data Path at Slow Process Corner: cmp_gn4124_core/l2p_rdy_t to cmp_gn4124_core/l2p_rdy
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    ILOGIC_X0Y41.Q4      Tickq                 1.220   cmp_gn4124_core/l2p_rdy_t
-                                                       cmp_gn4124_core/l2p_rdy_t
-    SLICE_X32Y70.CX      net (fanout=1)        3.731   cmp_gn4124_core/l2p_rdy_t
-    SLICE_X32Y70.CLK     Tdick                 0.114   cmp_gn4124_core/l2p_rdy
-                                                       cmp_gn4124_core/l2p_rdy
-    -------------------------------------------------  ---------------------------
-    Total                                      5.065ns (1.334ns logic, 3.731ns route)
-                                                       (26.3% logic, 73.7% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/l_wr_rdy_0 (SLICE_X3Y59.DX), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.114ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               cmp_gn4124_core/l_wr_rdy_t_0 (FF)
-  Destination:          cmp_gn4124_core/l_wr_rdy_0 (FF)
-  Requirement:          5.000ns
-  Data Path Delay:      4.218ns (Levels of Logic = 0)
-  Clock Path Skew:      -0.593ns (0.823 - 1.416)
-  Source Clock:         cmp_gn4124_core/sys_clk rising at 1.250ns
-  Destination Clock:    cmp_gn4124_core/sys_clk rising at 6.250ns
-  Clock Uncertainty:    0.075ns
-
-  Clock Uncertainty:          0.075ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
-    Total System Jitter (TSJ):  0.070ns
-    Discrete Jitter (DJ):       0.132ns
-    Phase Error (PE):           0.000ns
-
-  Maximum Data Path at Slow Process Corner: cmp_gn4124_core/l_wr_rdy_t_0 to cmp_gn4124_core/l_wr_rdy_0
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    ILOGIC_X0Y21.Q4      Tickq                 1.220   cmp_gn4124_core/l_wr_rdy_t<0>
-                                                       cmp_gn4124_core/l_wr_rdy_t_0
-    SLICE_X3Y59.DX       net (fanout=1)        2.884   cmp_gn4124_core/l_wr_rdy_t<0>
-    SLICE_X3Y59.CLK      Tdick                 0.114   cmp_gn4124_core/l_wr_rdy<0>
-                                                       cmp_gn4124_core/l_wr_rdy_0
-    -------------------------------------------------  ---------------------------
-    Total                                      4.218ns (1.334ns logic, 2.884ns route)
-                                                       (31.6% logic, 68.4% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_24 (SLICE_X44Y80.C6), 1 path
---------------------------------------------------------------------------------
-Slack (setup path):     0.128ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram (RAM)
-  Destination:          cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_24 (FF)
-  Requirement:          5.000ns
-  Data Path Delay:      4.957ns (Levels of Logic = 1)
-  Clock Path Skew:      0.160ns (0.956 - 0.796)
-  Source Clock:         cmp_gn4124_core/sys_clk rising at 1.250ns
-  Destination Clock:    cmp_gn4124_core/sys_clk rising at 6.250ns
-  Clock Uncertainty:    0.075ns
-
-  Clock Uncertainty:          0.075ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
-    Total System Jitter (TSJ):  0.070ns
-    Discrete Jitter (DJ):       0.132ns
-    Phase Error (PE):           0.000ns
-
-  Maximum Data Path at Slow Process Corner: cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram to cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_24
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    RAMB16_X3Y42.DOB24   Trcko_DOB             2.100   cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram
-    SLICE_X44Y80.C6      net (fanout=1)        2.518   cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_dout<24>
-    SLICE_X44Y80.CLK     Tas                   0.339   cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o<24>
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/Mmux_l2p_dma_current_state[2]_ldm_arb_data_o[31]_wide_mux_95_OUT17
-                                                       cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_24
-    -------------------------------------------------  ---------------------------
-    Total                                      4.957ns (2.439ns logic, 2.518ns route)
-                                                       (49.2% logic, 50.8% route)
-
---------------------------------------------------------------------------------
-
-Hold Paths: TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x1_0 = PERIOD TIMEGRP
-        "cmp_gn4124_core_cmp_clk_in_rx_pllout_x1_0"
-        TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk_0 PHASE 1.25 ns HIGH 50%;
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram (RAMB16_X2Y24.DIA19), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.274ns (requirement - (clock path skew + uncertainty - data path))
-  Source:               cmp_gn4124_core/cmp_wbmaster32/to_wb_fifo_din_21 (FF)
-  Destination:          cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram (RAM)
-  Requirement:          0.000ns
-  Data Path Delay:      0.277ns (Levels of Logic = 0)
-  Clock Path Skew:      0.003ns (0.076 - 0.073)
-  Source Clock:         cmp_gn4124_core/sys_clk rising at 6.250ns
-  Destination Clock:    cmp_gn4124_core/sys_clk rising at 6.250ns
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path at Fast Process Corner: cmp_gn4124_core/cmp_wbmaster32/to_wb_fifo_din_21 to cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X43Y50.BQ      Tcko                  0.198   cmp_gn4124_core/cmp_wbmaster32/to_wb_fifo_din<23>
-                                                       cmp_gn4124_core/cmp_wbmaster32/to_wb_fifo_din_21
-    RAMB16_X2Y24.DIA19   net (fanout=2)        0.132   cmp_gn4124_core/cmp_wbmaster32/to_wb_fifo_din<21>
-    RAMB16_X2Y24.CLKA    Trckd_DIA   (-Th)     0.053   cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram
-                                                       cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram
-    -------------------------------------------------  ---------------------------
-    Total                                      0.277ns (0.145ns logic, 0.132ns route)
-                                                       (52.3% logic, 47.7% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram (RAMB16_X2Y24.DIA21), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.274ns (requirement - (clock path skew + uncertainty - data path))
-  Source:               cmp_gn4124_core/cmp_wbmaster32/to_wb_fifo_din_23 (FF)
-  Destination:          cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram (RAM)
-  Requirement:          0.000ns
-  Data Path Delay:      0.277ns (Levels of Logic = 0)
-  Clock Path Skew:      0.003ns (0.076 - 0.073)
-  Source Clock:         cmp_gn4124_core/sys_clk rising at 6.250ns
-  Destination Clock:    cmp_gn4124_core/sys_clk rising at 6.250ns
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path at Fast Process Corner: cmp_gn4124_core/cmp_wbmaster32/to_wb_fifo_din_23 to cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X43Y50.DQ      Tcko                  0.198   cmp_gn4124_core/cmp_wbmaster32/to_wb_fifo_din<23>
-                                                       cmp_gn4124_core/cmp_wbmaster32/to_wb_fifo_din_23
-    RAMB16_X2Y24.DIA21   net (fanout=2)        0.132   cmp_gn4124_core/cmp_wbmaster32/to_wb_fifo_din<23>
-    RAMB16_X2Y24.CLKA    Trckd_DIA   (-Th)     0.053   cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram
-                                                       cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram
-    -------------------------------------------------  ---------------------------
-    Total                                      0.277ns (0.145ns logic, 0.132ns route)
-                                                       (52.3% logic, 47.7% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram (RAMB16_X2Y24.DIPA2), 1 path
---------------------------------------------------------------------------------
-Slack (hold path):      0.275ns (requirement - (clock path skew + uncertainty - data path))
-  Source:               cmp_gn4124_core/cmp_wbmaster32/to_wb_fifo_din_26 (FF)
-  Destination:          cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram (RAM)
-  Requirement:          0.000ns
-  Data Path Delay:      0.278ns (Levels of Logic = 0)
-  Clock Path Skew:      0.003ns (0.076 - 0.073)
-  Source Clock:         cmp_gn4124_core/sys_clk rising at 6.250ns
-  Destination Clock:    cmp_gn4124_core/sys_clk rising at 6.250ns
-  Clock Uncertainty:    0.000ns
-
-  Minimum Data Path at Fast Process Corner: cmp_gn4124_core/cmp_wbmaster32/to_wb_fifo_din_26 to cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X42Y50.CQ      Tcko                  0.200   cmp_gn4124_core/cmp_wbmaster32/to_wb_fifo_din<27>
-                                                       cmp_gn4124_core/cmp_wbmaster32/to_wb_fifo_din_26
-    RAMB16_X2Y24.DIPA2   net (fanout=2)        0.131   cmp_gn4124_core/cmp_wbmaster32/to_wb_fifo_din<26>
-    RAMB16_X2Y24.CLKA    Trckd_DIPA  (-Th)     0.053   cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram
-                                                       cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram
-    -------------------------------------------------  ---------------------------
-    Total                                      0.278ns (0.147ns logic, 0.131ns route)
-                                                       (52.9% logic, 47.1% route)
-
---------------------------------------------------------------------------------
-
-Component Switching Limit Checks: TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x1_0 = PERIOD TIMEGRP
-        "cmp_gn4124_core_cmp_clk_in_rx_pllout_x1_0"
-        TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk_0 PHASE 1.25 ns HIGH 50%;
---------------------------------------------------------------------------------
-Slack: 1.430ns (period - min period limit)
-  Period: 5.000ns
-  Min period limit: 3.570ns (280.112MHz) (Trper_CLKA(Fmax))
-  Physical resource: cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA
-  Logical resource: cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA
-  Location pin: RAMB16_X3Y20.CLKA
-  Clock network: cmp_gn4124_core/sys_clk
---------------------------------------------------------------------------------
-Slack: 1.430ns (period - min period limit)
-  Period: 5.000ns
-  Min period limit: 3.570ns (280.112MHz) (Trper_CLKA(Fmax))
-  Physical resource: cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA
-  Logical resource: cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA
-  Location pin: RAMB16_X3Y22.CLKA
-  Clock network: cmp_gn4124_core/sys_clk
---------------------------------------------------------------------------------
-Slack: 1.430ns (period - min period limit)
-  Period: 5.000ns
-  Min period limit: 3.570ns (280.112MHz) (Trper_CLKA(Fmax))
-  Physical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA
-  Logical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA
-  Location pin: RAMB16_X2Y22.CLKA
-  Clock network: cmp_gn4124_core/sys_clk
---------------------------------------------------------------------------------
-
-
-Derived Constraint Report
-Derived Constraints for TS_p2l_clkp
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
-|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
-|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-|TS_p2l_clkp                    |      5.000ns|      1.904ns|      3.570ns|            0|            0|            0|            0|
-| TS_cmp_gn4124_core_cmp_clk_in_|      5.000ns|      2.800ns|      3.570ns|            0|            0|            0|            0|
-| buf_P_clk                     |             |             |             |             |             |             |             |
-|  TS_cmp_gn4124_core_cmp_clk_in|      2.500ns|          N/A|          N/A|            0|            0|            0|            0|
-|  _rx_pllout_xs_int            |             |             |             |             |             |             |             |
-|  TS_cmp_gn4124_core_cmp_clk_in|      5.000ns|      3.570ns|          N/A|            0|            0|            0|            0|
-|  _rx_pllout_x1                |             |             |             |             |             |             |             |
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-
-Derived Constraints for TS_p2l_clkn
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
-|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
-|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-|TS_p2l_clkn                    |      5.000ns|      1.904ns|      5.579ns|            0|            1|            0|        29021|
-| TS_cmp_gn4124_core_cmp_clk_in_|      5.000ns|      2.800ns|      5.579ns|            0|            1|            0|        29021|
-| buf_P_clk_0                   |             |             |             |             |             |             |             |
-|  TS_cmp_gn4124_core_cmp_clk_in|      2.500ns|          N/A|          N/A|            0|            0|            0|            0|
-|  _rx_pllout_xs_int_0          |             |             |             |             |             |             |             |
-|  TS_cmp_gn4124_core_cmp_clk_in|      5.000ns|      5.579ns|          N/A|            1|            0|        29021|            0|
-|  _rx_pllout_x1_0              |             |             |             |             |             |             |             |
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-
-1 constraint not met.
-
-
-Data Sheet report:
------------------
-All values displayed in nanoseconds (ns)
-
-Clock to Setup on destination clock L_CLKn
----------------+---------+---------+---------+---------+
-               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
-Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
----------------+---------+---------+---------+---------+
-L_CLKn         |    4.795|         |         |         |
-L_CLKp         |    4.795|         |         |         |
----------------+---------+---------+---------+---------+
-
-Clock to Setup on destination clock L_CLKp
----------------+---------+---------+---------+---------+
-               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
-Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
----------------+---------+---------+---------+---------+
-L_CLKn         |    4.795|         |         |         |
-L_CLKp         |    4.795|         |         |         |
----------------+---------+---------+---------+---------+
-
-Clock to Setup on destination clock P2L_CLKn
----------------+---------+---------+---------+---------+
-               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
-Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
----------------+---------+---------+---------+---------+
-P2L_CLKn       |    5.579|         |         |         |
-P2L_CLKp       |    5.579|         |         |         |
----------------+---------+---------+---------+---------+
-
-Clock to Setup on destination clock P2L_CLKp
----------------+---------+---------+---------+---------+
-               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
-Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
----------------+---------+---------+---------+---------+
-P2L_CLKn       |    5.579|         |         |         |
-P2L_CLKp       |    5.579|         |         |         |
----------------+---------+---------+---------+---------+
-
-
-Timing summary:
----------------
-
-Timing errors: 1  Score: 579  (Setup/Max: 579, Hold: 0)
-
-Constraints cover 38330 paths, 7 nets, and 11571 connections
-
-Design statistics:
-   Minimum period:   5.579ns{1}   (Maximum frequency: 179.244MHz)
-   Maximum net delay:   0.324ns
-
-
-------------------------------------Footnotes-----------------------------------
-1)  The minimum period statistic assumes all single cycle delays.
-
-Analysis completed Fri Dec 10 09:50:59 2010 
---------------------------------------------------------------------------------
-
-Trace Settings:
--------------------------
-Trace Settings 
-
-Peak Memory Usage: 300 MB
-
-
-
diff --git a/hdl/pfc/ise_project/pfc_wrapper.xise b/hdl/pfc/ise_project/pfc_wrapper.xise
deleted file mode 100644
index 1da4254271110dfaf0ef5fbc9ead27d3bb61558a..0000000000000000000000000000000000000000
--- a/hdl/pfc/ise_project/pfc_wrapper.xise
+++ /dev/null
@@ -1,444 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <header>
-    <!-- ISE source project file created by Project Navigator.             -->
-    <!--                                                                   -->
-    <!-- This file contains project source information including a list of -->
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-    <!-- implement in ISE Project Navigator.                               -->
-    <!--                                                                   -->
-    <!-- Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved. -->
-  </header>
-
-  <version xil_pn:ise_version="12.2" xil_pn:schema_version="2"/>
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-    <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
-    <property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
-    <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
-    <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
-    <property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Detailed Package Parasitics" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Optimization map" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
-    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|pfc_wrapper|rtl" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="../rtl/pfc_wrapper.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/pfc_wrapper" xil_pn:valueState="non-default"/>
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-    <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
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-    <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
-    <property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
-    <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
-    <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
-    <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
-    <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
-    <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
-    <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output File Name" xil_pn:value="pfc_wrapper" xil_pn:valueState="default"/>
-    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Package" xil_pn:value="fgg676" xil_pn:valueState="default"/>
-    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
-    <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="pfc_wrapper_map.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="pfc_wrapper_timesim.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="pfc_wrapper_synthesis.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="pfc_wrapper_translate.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Produce Advanced Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
-    <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="pfc_wrapper" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Retiming Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
-    <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
-    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
-    <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
-    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
-    <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
-    <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
-    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <!--                                                                                  -->
-    <!-- The following properties are for internal use only. These should not be modified.-->
-    <!--                                                                                  -->
-    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_DesignName" xil_pn:value="pfc_wrapper" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2010-11-17T14:47:20" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="7B4AC96A57FD2BFE22200AEB343F87BA" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
-  </properties>
-
-  <bindings/>
-
-  <libraries/>
-
-  <autoManagedFiles>
-    <!-- The following files are identified by `include statements in verilog -->
-    <!-- source files and are automatically managed by Project Navigator.     -->
-    <!--                                                                      -->
-    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
-    <!-- project is analyzed based on files automatically identified as       -->
-    <!-- include files.                                                       -->
-  </autoManagedFiles>
-
-</project>
diff --git a/hdl/pfc/pfc_wrapper.ucf b/hdl/pfc/pfc_wrapper.ucf
deleted file mode 100644
index fb54a34f6c553acff0a4eae2a0bdb9023c57d30e..0000000000000000000000000000000000000000
--- a/hdl/pfc/pfc_wrapper.ucf
+++ /dev/null
@@ -1,180 +0,0 @@
-
-#---------------------------------------------------------------------------------------------
-# IO standards
-#---------------------------------------------------------------------------------------------
-NET "l2p_data[0]"  IOSTANDARD = SSTL18_I;
-NET "l2p_data[1]"  IOSTANDARD = SSTL18_I;
-NET "l2p_data[2]"  IOSTANDARD = SSTL18_I;
-NET "l2p_data[3]"  IOSTANDARD = SSTL18_I;
-NET "l2p_data[4]"  IOSTANDARD = SSTL18_I;
-NET "l2p_data[5]"  IOSTANDARD = SSTL18_I;
-NET "l2p_data[6]"  IOSTANDARD = SSTL18_I;
-NET "l2p_data[7]"  IOSTANDARD = SSTL18_I;
-NET "l2p_data[8]"  IOSTANDARD = SSTL18_I;
-NET "l2p_data[9]"  IOSTANDARD = SSTL18_I;
-NET "l2p_data[10]" IOSTANDARD = SSTL18_I;
-NET "l2p_data[11]" IOSTANDARD = SSTL18_I;
-NET "l2p_data[12]" IOSTANDARD = SSTL18_I;
-NET "l2p_data[13]" IOSTANDARD = SSTL18_I;
-NET "l2p_data[14]" IOSTANDARD = SSTL18_I;
-NET "l2p_data[15]" IOSTANDARD = SSTL18_I;
-NET "l2p_clkp"     IOSTANDARD = DIFF_SSTL18_I;
-NET "l2p_clkn"     IOSTANDARD = DIFF_SSTL18_I;
-NET "l2p_rdy"      IOSTANDARD = SSTL18_I;
-NET "l_clkn"       IOSTANDARD = DIFF_SSTL18_I; #SSTL18_I;
-NET "l_clkp"       IOSTANDARD = DIFF_SSTL18_I; #SSTL18_I;
-NET "l_rst_n"      IOSTANDARD = SSTL18_I;
-NET "p2l_clkp"     IOSTANDARD = DIFF_SSTL18_I;
-NET "p2l_clkn"     IOSTANDARD = DIFF_SSTL18_I;
-NET "p2l_data[0]"  IOSTANDARD = SSTL18_I;
-NET "p2l_data[1]"  IOSTANDARD = SSTL18_I;
-NET "p2l_data[2]"  IOSTANDARD = SSTL18_I;
-NET "p2l_data[3]"  IOSTANDARD = SSTL18_I;
-NET "p2l_data[4]"  IOSTANDARD = SSTL18_I;
-NET "p2l_data[5]"  IOSTANDARD = SSTL18_I;
-NET "p2l_data[6]"  IOSTANDARD = SSTL18_I;
-NET "p2l_data[7]"  IOSTANDARD = SSTL18_I;
-NET "p2l_data[8]"  IOSTANDARD = SSTL18_I;
-NET "p2l_data[9]"  IOSTANDARD = SSTL18_I;
-NET "p2l_data[10]" IOSTANDARD = SSTL18_I;
-NET "p2l_data[11]" IOSTANDARD = SSTL18_I;
-NET "p2l_data[12]" IOSTANDARD = SSTL18_I;
-NET "p2l_data[13]" IOSTANDARD = SSTL18_I;
-NET "p2l_data[14]" IOSTANDARD = SSTL18_I;
-NET "p2l_data[15]" IOSTANDARD = SSTL18_I;
-NET "p2l_rdy"      IOSTANDARD = SSTL18_I;
-NET "l_wr_rdy[0]"    IOSTANDARD = SSTL18_I;
-NET "l_wr_rdy[1]"    IOSTANDARD = SSTL18_I;
-NET "p_rd_d_rdy[0]"  IOSTANDARD = SSTL18_I;
-NET "p_rd_d_rdy[1]"  IOSTANDARD = SSTL18_I;
-NET "l2p_dframe"   IOSTANDARD = SSTL18_I;
-NET "l2p_valid"    IOSTANDARD = SSTL18_I;
-NET "l2p_edb"      IOSTANDARD = SSTL18_I;
-NET "p2l_dframe"   IOSTANDARD = SSTL18_I;
-NET "p2l_valid"    IOSTANDARD = SSTL18_I;
-NET "p_wr_rdy[0]"    IOSTANDARD = SSTL18_I;
-NET "p_wr_rdy[1]"    IOSTANDARD = SSTL18_I;
-NET "rx_error"     IOSTANDARD = SSTL18_I;
-NET "tx_error"     IOSTANDARD = SSTL18_I;
-NET "vc_rdy[0]"    IOSTANDARD = SSTL18_I;
-NET "vc_rdy[1]"    IOSTANDARD = SSTL18_I;
-NET "p_wr_req[0]" IOSTANDARD = SSTL18_I;
-NET "p_wr_req[1]" IOSTANDARD = SSTL18_I;
-
-NET "l_rst_n"    IOSTANDARD = "LVCMOS18";
-
-# GPIO
-NET "gpio[*]" IOSTANDARD = "LVCMOS33";
-
-# Font panel LEDs
-NET "led_red"   IOSTANDARD = "LVCMOS15";
-NET "led_green"   IOSTANDARD = "LVCMOS15";
-
-# System clock
-NET "sys_clk_p" IOSTANDARD = "LVDS_33";
-
-# User IO (eSATA connector)
-NET "user_io_0_p" IOSTANDARD = "LVCMOS33";
-NET "user_io_0_n" IOSTANDARD = "LVCMOS33";
-NET "user_io_1_p" IOSTANDARD = "LVCMOS18";
-NET "user_io_1_n" IOSTANDARD = "LVCMOS18";
-
-
-#---------------------------------------------------------------------------------------------
-# Local clock from GN4124
-#---------------------------------------------------------------------------------------------
-NET "L_CLKp" TNM_NET = "l_clkp_grp";
-TIMESPEC TS_l_clkp = PERIOD "l_clkp_grp" 5 ns HIGH 50%;
-
-#---------------------------------------------------------------------------------------------
-# P2L source synchronous interface
-#---------------------------------------------------------------------------------------------
-# Period constraint on incomming clock
-NET "P2L_CLKp" TNM_NET = "p2l_clkp_grp";
-TIMESPEC TS_p2l_clkp = PERIOD "p2l_clkp_grp" 5 ns HIGH 50%;
-NET "P2L_CLKn" TNM_NET = "p2l_clkn_grp";
-TIMESPEC TS_p2l_clkn = PERIOD "p2l_clkn_grp" 5 ns HIGH 50%;
-
-#---------------------------------------------------------------------------------------------
-# False Path
-#---------------------------------------------------------------------------------------------
-NET "l_rst_n" TIG;
-NET "cmp_gn4124_core/rst_*" TIG;
-
-#---------------------------------------------------------------------------------------------
-# The IO Location Constraints
-#---------------------------------------------------------------------------------------------
-NET "sys_clk_p" LOC = AE15;
-NET "sys_clk_n" LOC = AF15;
-
-NET "l_rst_n" LOC = P8;
-NET "l_clkp" LOC = R2;
-NET "l_clkn" LOC = R1;
-
-NET "l2p_data[0]" LOC = U3;
-NET "l2p_data[1]" LOC = U4;
-NET "l2p_data[2]" LOC = N8;
-NET "l2p_data[3]" LOC = U8;
-NET "l2p_data[4]" LOC = P6;
-NET "l2p_data[5]" LOC = T9;
-NET "l2p_data[6]" LOC = N5;
-NET "l2p_data[7]" LOC = R9;
-NET "l2p_data[8]" LOC = V6;
-NET "l2p_data[9]" LOC = T4;
-NET "l2p_data[10]" LOC = U7;
-NET "l2p_data[11]" LOC = R5;
-NET "l2p_data[12]" LOC = P3;
-NET "l2p_data[13]" LOC = T8;
-NET "l2p_data[14]" LOC = N4;
-NET "l2p_data[15]" LOC = R8;
-NET "l2p_dframe" LOC = P1;
-NET "l2p_valid" LOC = R3;
-NET "l2p_edb" LOC = P5;
-NET "l2p_clkp" LOC = P10;
-NET "l2p_clkn" LOC = N9;
-NET "l_wr_rdy[0]" LOC = V7;
-NET "l_wr_rdy[1]" LOC = R4;
-NET "p_rd_d_rdy[0]" LOC = U2;
-NET "p_rd_d_rdy[1]" LOC = U5;
-NET "l2p_rdy" LOC = U9;
-NET "tx_error" LOC = Y6;
-
-NET "p2l_data[0]" LOC = AA1;
-NET "p2l_data[1]" LOC = AE1;
-NET "p2l_data[2]" LOC = AA3;
-NET "p2l_data[3]" LOC = Y1;
-NET "p2l_data[4]" LOC = AC1;
-NET "p2l_data[5]" LOC = AC2;
-NET "p2l_data[6]" LOC = AB1;
-NET "p2l_data[7]" LOC = AB3;
-NET "p2l_data[8]" LOC = AD1;
-NET "p2l_data[9]" LOC = AE2;
-NET "p2l_data[10]" LOC = AA2;
-NET "p2l_data[11]" LOC = AD3;
-NET "p2l_data[12]" LOC = AA4;
-NET "p2l_data[13]" LOC = AB5;
-NET "p2l_data[14]" LOC = Y5;
-NET "p2l_data[15]" LOC = AB4;
-NET "p2l_dframe" LOC = Y3;
-NET "p2l_valid" LOC = AC3;
-NET "p2l_clkp" LOC = T3;
-NET "p2l_clkn" LOC = T1;
-NET "p_wr_req[0]" LOC = V1;
-NET "p_wr_req[1]" LOC = V3;
-NET "p_wr_rdy[0]" LOC = M4;
-NET "p_wr_rdy[1]" LOC = N20;
-NET "vc_rdy[0]" LOC = U1;
-NET "vc_rdy[1]" LOC = V5;
-NET "p2l_rdy" LOC = W2;
-NET "rx_error" LOC = W1;
-
-NET "gpio[0]" LOC = AA18;
-NET "gpio[1]" LOC = W17;
-
-NET "led_red" LOC = L21;
-NET "led_green" LOC = L20;
-
-NET "user_io_0_p" LOC = AE13;
-NET "user_io_0_n" LOC = AF13;
-NET "user_io_1_p" LOC = Y26;
-NET "user_io_1_n" LOC = Y24;
diff --git a/hdl/pfc/rtl/pfc_wrapper.vhd b/hdl/pfc/rtl/pfc_wrapper.vhd
deleted file mode 100644
index 729a495799aad9e77b9e1a03d1ddf18d451a1fc0..0000000000000000000000000000000000000000
--- a/hdl/pfc/rtl/pfc_wrapper.vhd
+++ /dev/null
@@ -1,533 +0,0 @@
---------------------------------------------------------------------------------
---                                                                            --
--- CERN BE-CO-HT         GN4124 core for PCIe FMC carrier                     --
---                       http://www.ohwr.org/projects/gn4124-core             --
---------------------------------------------------------------------------------
---
--- unit name: pfc_wrapper (pfc_wrapper.vhd)
---
--- author: Matthieu Cattin (matthieu.cattin@cern.ch)
---
--- date: 20-10-2010
---
--- version: 0.1
---
--- description: Wrapper for the GN4124 core to drop into the FPGA on the
---              PFC (PCIe FMC Carrier) board
---
--- dependencies:
---
---------------------------------------------------------------------------------
--- last changes: see svn log.
---------------------------------------------------------------------------------
--- TODO: - 
---------------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.NUMERIC_STD.all;
-use work.gn4124_core_pkg.all;
-
-library UNISIM;
-use UNISIM.vcomponents.all;
-
-
-entity pfc_wrapper is
-  generic
-    (
-      TAR_ADDR_WDTH : integer := 13     -- not used for this project
-      );
-  port
-    (
-
-      -- Global ports
-      SYS_CLK_P : in std_logic;         -- 25MHz system clock
-      SYS_CLK_N : in std_logic;         -- 25MHz system clock
-
-      -- From GN4124 Local bus
-      L_CLKp : in std_logic;            -- Local bus clock (frequency set in GN4124 config registers)
-      L_CLKn : in std_logic;            -- Local bus clock (frequency set in GN4124 config registers)
-
-      L_RST_N : in std_logic;           -- Reset from GN4124 (RSTOUT18_N)
-
-      -- General Purpose Interface
-      GPIO : inout std_logic_vector(1 downto 0);  -- GPIO[0] -> GN4124 GPIO8
-                                                  -- GPIO[1] -> GN4124 GPIO9
-
-      -- PCIe to Local [Inbound Data] - RX
-      P2L_RDY    : out std_logic;                      -- Rx Buffer Full Flag
-      P2L_CLKn   : in  std_logic;                      -- Receiver Source Synchronous Clock-
-      P2L_CLKp   : in  std_logic;                      -- Receiver Source Synchronous Clock+
-      P2L_DATA   : in  std_logic_vector(15 downto 0);  -- Parallel receive data
-      P2L_DFRAME : in  std_logic;                      -- Receive Frame
-      P2L_VALID  : in  std_logic;                      -- Receive Data Valid
-
-      -- Inbound Buffer Request/Status
-      P_WR_REQ : in  std_logic_vector(1 downto 0);  -- PCIe Write Request
-      P_WR_RDY : out std_logic_vector(1 downto 0);  -- PCIe Write Ready
-      RX_ERROR : out std_logic;                     -- Receive Error
-
-      -- Local to Parallel [Outbound Data] - TX
-      L2P_DATA   : out std_logic_vector(15 downto 0);  -- Parallel transmit data
-      L2P_DFRAME : out std_logic;                      -- Transmit Data Frame
-      L2P_VALID  : out std_logic;                      -- Transmit Data Valid
-      L2P_CLKn   : out std_logic;                      -- Transmitter Source Synchronous Clock-
-      L2P_CLKp   : out std_logic;                      -- Transmitter Source Synchronous Clock+
-      L2P_EDB    : out std_logic;                      -- Packet termination and discard
-
-      -- Outbound Buffer Status
-      L2P_RDY    : in std_logic;                     -- Tx Buffer Full Flag
-      L_WR_RDY   : in std_logic_vector(1 downto 0);  -- Local-to-PCIe Write
-      P_RD_D_RDY : in std_logic_vector(1 downto 0);  -- PCIe-to-Local Read Response Data Ready
-      TX_ERROR   : in std_logic;                     -- Transmit Error
-      VC_RDY     : in std_logic_vector(1 downto 0);  -- Channel ready
-
-      -- Font panel LEDs
-      LED_RED   : out std_logic;
-      LED_GREEN : out std_logic;
-
-      -- User IO (eSATA connector)
-      USER_IO_0_P : out std_logic;
-      USER_IO_0_N : out std_logic;
-      USER_IO_1_P : out std_logic;
-      USER_IO_1_N : out std_logic
-      );
-end pfc_wrapper;
-
-architecture rtl of pfc_wrapper is
-
-  ------------------------------------------------------------------------------
-  -- Components declaration
-  ------------------------------------------------------------------------------
-
-  component gn4124_core
-    generic(
-      g_IS_SPARTAN6       : boolean := false;  -- This generic is used to instanciate spartan6 specific primitives
-      g_BAR0_APERTURE     : integer := 20;     -- BAR0 aperture, defined in GN4124 PCI_BAR_CONFIG register (0x80C)
-                                               -- => number of bits to address periph on the board
-      g_CSR_WB_SLAVES_NB  : integer := 1;      -- Number of CSR wishbone slaves
-      g_DMA_WB_SLAVES_NB  : integer := 1;      -- Number of DMA wishbone slaves
-      g_DMA_WB_ADDR_WIDTH : integer := 26      -- DMA wishbone address bus width
-      );
-    port
-      (
-        ---------------------------------------------------------
-        -- Control and status
-        --
-        -- Asynchronous reset from GN4124
-        rst_n_a_i      : in  std_logic;
-        -- P2L clock PLL locked
-        p2l_pll_locked : out std_logic;
-        -- Debug ouputs
-        debug_o        : out std_logic_vector(7 downto 0);
-
-        ---------------------------------------------------------
-        -- P2L Direction
-        --
-        -- Source Sync DDR related signals
-        p2l_clk_p_i  : in  std_logic;                      -- Receiver Source Synchronous Clock+
-        p2l_clk_n_i  : in  std_logic;                      -- Receiver Source Synchronous Clock-
-        p2l_data_i   : in  std_logic_vector(15 downto 0);  -- Parallel receive data
-        p2l_dframe_i : in  std_logic;                      -- Receive Frame
-        p2l_valid_i  : in  std_logic;                      -- Receive Data Valid
-        -- P2L Control
-        p2l_rdy_o    : out std_logic;                      -- Rx Buffer Full Flag
-        p_wr_req_i   : in  std_logic_vector(1 downto 0);   -- PCIe Write Request
-        p_wr_rdy_o   : out std_logic_vector(1 downto 0);   -- PCIe Write Ready
-        rx_error_o   : out std_logic;                      -- Receive Error
-
-        ---------------------------------------------------------
-        -- L2P Direction
-        --
-        -- Source Sync DDR related signals
-        l2p_clk_p_o  : out std_logic;                      -- Transmitter Source Synchronous Clock+
-        l2p_clk_n_o  : out std_logic;                      -- Transmitter Source Synchronous Clock-
-        l2p_data_o   : out std_logic_vector(15 downto 0);  -- Parallel transmit data
-        l2p_dframe_o : out std_logic;                      -- Transmit Data Frame
-        l2p_valid_o  : out std_logic;                      -- Transmit Data Valid
-        l2p_edb_o    : out std_logic;                      -- Packet termination and discard
-        -- L2P Control
-        l2p_rdy_i    : in  std_logic;                      -- Tx Buffer Full Flag
-        l_wr_rdy_i   : in  std_logic_vector(1 downto 0);   -- Local-to-PCIe Write
-        p_rd_d_rdy_i : in  std_logic_vector(1 downto 0);   -- PCIe-to-Local Read Response Data Ready
-        tx_error_i   : in  std_logic;                      -- Transmit Error
-        vc_rdy_i     : in  std_logic_vector(1 downto 0);   -- Channel ready
-
-        ---------------------------------------------------------
-        -- Interrupt interface
-        dma_irq_o : out std_logic_vector(1 downto 0);  -- Interrupts sources to IRQ manager
-        irq_p_i   : in  std_logic;                     -- Interrupt request pulse from IRQ manager
-        irq_p_o   : out std_logic;                     -- Interrupt request pulse to GN4124 GPIO
-
-        ---------------------------------------------------------
-        -- Target interface (CSR wishbone master)
-        wb_clk_i : in  std_logic;
-        wb_adr_o : out std_logic_vector(g_BAR0_APERTURE-log2_ceil(g_CSR_WB_SLAVES_NB+1)-1 downto 0);
-        wb_dat_o : out std_logic_vector(31 downto 0);                         -- Data out
-        wb_sel_o : out std_logic_vector(3 downto 0);                          -- Byte select
-        wb_stb_o : out std_logic;
-        wb_we_o  : out std_logic;
-        wb_cyc_o : out std_logic_vector(g_CSR_WB_SLAVES_NB-1 downto 0);
-        wb_dat_i : in  std_logic_vector((32*g_CSR_WB_SLAVES_NB)-1 downto 0);  -- Data in
-        wb_ack_i : in  std_logic_vector(g_CSR_WB_SLAVES_NB-1 downto 0);
-
-        ---------------------------------------------------------
-        -- DMA interface (Pipelined wishbone master)
-        dma_clk_i   : in  std_logic;
-        dma_adr_o   : out std_logic_vector(31 downto 0);
-        dma_dat_o   : out std_logic_vector(31 downto 0);                         -- Data out
-        dma_sel_o   : out std_logic_vector(3 downto 0);                          -- Byte select
-        dma_stb_o   : out std_logic;
-        dma_we_o    : out std_logic;
-        dma_cyc_o   : out std_logic;                                             --_vector(g_DMA_WB_SLAVES_NB-1 downto 0);
-        dma_dat_i   : in  std_logic_vector((32*g_DMA_WB_SLAVES_NB)-1 downto 0);  -- Data in
-        dma_ack_i   : in  std_logic;                                             --_vector(g_DMA_WB_SLAVES_NB-1 downto 0);
-        dma_stall_i : in  std_logic--_vector(g_DMA_WB_SLAVES_NB-1 downto 0)        -- for pipelined Wishbone
-        );
-  end component;  --  gn4124_core
-
-  component dummy_stat_regs_wb_slave
-    port (
-      rst_n_i                 : in  std_logic;
-      wb_clk_i                : in  std_logic;
-      wb_addr_i               : in  std_logic_vector(1 downto 0);
-      wb_data_i               : in  std_logic_vector(31 downto 0);
-      wb_data_o               : out std_logic_vector(31 downto 0);
-      wb_cyc_i                : in  std_logic;
-      wb_sel_i                : in  std_logic_vector(3 downto 0);
-      wb_stb_i                : in  std_logic;
-      wb_we_i                 : in  std_logic;
-      wb_ack_o                : out std_logic;
-      dummy_stat_reg_1_i      : in  std_logic_vector(31 downto 0);
-      dummy_stat_reg_2_i      : in  std_logic_vector(31 downto 0);
-      dummy_stat_reg_3_i      : in  std_logic_vector(31 downto 0);
-      dummy_stat_reg_switch_i : in  std_logic_vector(31 downto 0)
-      );
-  end component;
-
-  component dummy_ctrl_regs_wb_slave
-    port (
-      rst_n_i         : in  std_logic;
-      wb_clk_i        : in  std_logic;
-      wb_addr_i       : in  std_logic_vector(1 downto 0);
-      wb_data_i       : in  std_logic_vector(31 downto 0);
-      wb_data_o       : out std_logic_vector(31 downto 0);
-      wb_cyc_i        : in  std_logic;
-      wb_sel_i        : in  std_logic_vector(3 downto 0);
-      wb_stb_i        : in  std_logic;
-      wb_we_i         : in  std_logic;
-      wb_ack_o        : out std_logic;
-      dummy_reg_1_o   : out std_logic_vector(31 downto 0);
-      dummy_reg_2_o   : out std_logic_vector(31 downto 0);
-      dummy_reg_3_o   : out std_logic_vector(31 downto 0);
-      dummy_reg_led_o : out std_logic_vector(31 downto 0)
-      );
-  end component;
-
-  component ram_2048x32
-    port (
-      clka  : in  std_logic;
-      wea   : in  std_logic_vector(0 downto 0);
-      addra : in  std_logic_vector(10 downto 0);
-      dina  : in  std_logic_vector(31 downto 0);
-      douta : out std_logic_vector(31 downto 0)
-      );
-  end component;
-
-  ------------------------------------------------------------------------------
-  -- Constants declaration
-  ------------------------------------------------------------------------------
-  constant c_BAR0_APERTURE     : integer := 20;
-  constant c_CSR_WB_SLAVES_NB  : integer := 2;
-  constant c_DMA_WB_SLAVES_NB  : integer := 1;
-  constant c_DMA_WB_ADDR_WIDTH : integer := 26;
-
-  ------------------------------------------------------------------------------
-  -- Signals declaration
-  ------------------------------------------------------------------------------
-
-  -- System clock
-  signal sys_clk : std_logic;
-
-  -- LCLK from GN4124 used as system clock
-  signal l_clk : std_logic;
-
-  -- P2L colck PLL status
-  signal p2l_pll_locked : std_logic;
-
-  -- CSR wishbone bus
-  signal wb_adr   : std_logic_vector(c_BAR0_APERTURE-log2_ceil(c_CSR_WB_SLAVES_NB+1)-1 downto 0);
-  signal wb_dat_i : std_logic_vector((32*c_CSR_WB_SLAVES_NB)-1 downto 0);
-  signal wb_dat_o : std_logic_vector(31 downto 0);
-  signal wb_sel   : std_logic_vector(3 downto 0);
-  signal wb_cyc   : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0);
-  signal wb_stb   : std_logic;
-  signal wb_we    : std_logic;
-  signal wb_ack   : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0);
-
-  -- DMA wishbone bus
-  signal dma_adr_o   : std_logic_vector(31 downto 0);
-  signal dma_dat_i   : std_logic_vector((32*c_DMA_WB_SLAVES_NB)-1 downto 0);
-  signal dma_dat_o   : std_logic_vector(31 downto 0);
-  signal dma_sel_o   : std_logic_vector(3 downto 0);
-  signal dma_cyc_o   : std_logic;       --_vector(c_DMA_WB_SLAVES_NB-1 downto 0);
-  signal dma_stb_o   : std_logic;
-  signal dma_we_o    : std_logic;
-  signal dma_ack_i   : std_logic;       --_vector(c_DMA_WB_SLAVES_NB-1 downto 0);
-  signal dma_stall_i : std_logic;       --_vector(c_DMA_WB_SLAVES_NB-1 downto 0);
-  signal ram_we      : std_logic_vector(0 downto 0);
-
-  -- Interrupts stuff
-  signal irq_sources   : std_logic_vector(1 downto 0);
-  signal irq_to_gn4124 : std_logic;
-
-  -- CSR whisbone slaves for test
-  signal dummy_stat_reg_1      : std_logic_vector(31 downto 0);
-  signal dummy_stat_reg_2      : std_logic_vector(31 downto 0);
-  signal dummy_stat_reg_3      : std_logic_vector(31 downto 0);
-  signal dummy_stat_reg_switch : std_logic_vector(31 downto 0);
-
-  signal dummy_ctrl_reg_1   : std_logic_vector(31 downto 0);
-  signal dummy_ctrl_reg_2   : std_logic_vector(31 downto 0);
-  signal dummy_ctrl_reg_3   : std_logic_vector(31 downto 0);
-  signal dummy_ctrl_reg_led : std_logic_vector(31 downto 0);
-
-  -- FOR TESTS
-  signal debug : std_logic_vector(7 downto 0);
-  signal clk_div_cnt : unsigned(3 downto 0);
-  signal clk_div     : std_logic;
-
-
-begin
-
-  ------------------------------------------------------------------------------
-  -- System clock from 25MHz TCXO
-  ------------------------------------------------------------------------------
-  cmp_sysclk_buf : IBUFDS
-    generic map (
-      DIFF_TERM    => false,            -- Differential Termination
-      IBUF_LOW_PWR => true,             -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
-      IOSTANDARD   => "DEFAULT")
-    port map (
-      O  => sys_clk,                    -- Buffer output
-      I  => sys_clk_p,                  -- Diff_p buffer input (connect directly to top-level port)
-      IB => sys_clk_n                   -- Diff_n buffer input (connect directly to top-level port)
-      );
-
-  ------------------------------------------------------------------------------
-  -- Local clock from gennum LCLK
-  ------------------------------------------------------------------------------
-  cmp_l_clk_buf : IBUFDS
-    generic map (
-      DIFF_TERM    => false,            -- Differential Termination
-      IBUF_LOW_PWR => true,             -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
-      IOSTANDARD   => "DEFAULT")
-    port map (
-      O  => l_clk,                      -- Buffer output
-      I  => L_CLKp,                     -- Diff_p buffer input (connect directly to top-level port)
-      IB => L_CLKn                      -- Diff_n buffer input (connect directly to top-level port)
-      );
-
-  ------------------------------------------------------------------------------
-  -- GN4124 interface
-  ------------------------------------------------------------------------------
-  cmp_gn4124_core : gn4124_core
-    generic map (
-      g_IS_SPARTAN6       => true,
-      g_BAR0_APERTURE     => c_BAR0_APERTURE,
-      g_CSR_WB_SLAVES_NB  => c_CSR_WB_SLAVES_NB,
-      g_DMA_WB_SLAVES_NB  => c_DMA_WB_SLAVES_NB,
-      g_DMA_WB_ADDR_WIDTH => c_DMA_WB_ADDR_WIDTH
-      )
-    port map
-    (
-      ---------------------------------------------------------
-      -- Control and status
-      --
-      -- Asynchronous reset from GN4124
-      rst_n_a_i      => L_RST_N,
-      -- P2L clock PLL locked
-      p2l_pll_locked => p2l_pll_locked,
-      -- Debug outputs
-      debug_o => debug,
-
-      ---------------------------------------------------------
-      -- P2L Direction
-      --
-      -- Source Sync DDR related signals
-      p2l_clk_p_i  => P2L_CLKp,
-      p2l_clk_n_i  => P2L_CLKn,
-      p2l_data_i   => P2L_DATA,
-      p2l_dframe_i => P2L_DFRAME,
-      p2l_valid_i  => P2L_VALID,
-
-      -- P2L Control
-      p2l_rdy_o  => P2L_RDY,
-      p_wr_req_i => P_WR_REQ,
-      p_wr_rdy_o => P_WR_RDY,
-      rx_error_o => RX_ERROR,
-
-      ---------------------------------------------------------
-      -- L2P Direction
-      --
-      -- Source Sync DDR related signals
-      l2p_clk_p_o  => L2P_CLKp,
-      l2p_clk_n_o  => L2P_CLKn,
-      l2p_data_o   => L2P_DATA,
-      l2p_dframe_o => L2P_DFRAME,
-      l2p_valid_o  => L2P_VALID,
-      l2p_edb_o    => L2P_EDB,
-
-      -- L2P Control
-      l2p_rdy_i    => L2P_RDY,
-      l_wr_rdy_i   => L_WR_RDY,
-      p_rd_d_rdy_i => P_RD_D_RDY,
-      tx_error_i   => TX_ERROR,
-      vc_rdy_i     => VC_RDY,
-
-      ---------------------------------------------------------
-      -- Interrupt interface
-      dma_irq_o => irq_sources,
-      irq_p_i   => irq_to_gn4124,
-      irq_p_o   => GPIO(0),
-
-      ---------------------------------------------------------
-      -- Target Interface (Wishbone master)
-      wb_clk_i => l_clk,
-      wb_adr_o => wb_adr,
-      wb_dat_o => wb_dat_o,
-      wb_sel_o => wb_sel,
-      wb_stb_o => wb_stb,
-      wb_we_o  => wb_we,
-      wb_cyc_o => wb_cyc,
-      wb_dat_i => wb_dat_i,
-      wb_ack_i => wb_ack,
-
-      ---------------------------------------------------------
-      -- L2P DMA Interface (Pipelined Wishbone master)
-      dma_clk_i   => l_clk,
-      dma_adr_o   => dma_adr_o,
-      dma_dat_o   => dma_dat_o,
-      dma_sel_o   => dma_sel_o,
-      dma_stb_o   => dma_stb_o,
-      dma_we_o    => dma_we_o,
-      dma_cyc_o   => dma_cyc_o,
-      dma_dat_i   => dma_dat_i,
-      dma_ack_i   => dma_ack_i,
-      dma_stall_i => dma_stall_i
-      );
-
-
-  ------------------------------------------------------------------------------
-  -- CSR wishbone bus slaves
-  ------------------------------------------------------------------------------
-  cmp_dummy_stat_regs : dummy_stat_regs_wb_slave
-    port map(
-      rst_n_i                 => L_RST_N,
-      wb_clk_i                => l_clk,
-      wb_addr_i               => wb_adr(1 downto 0),
-      wb_data_i               => wb_dat_o,
-      wb_data_o               => wb_dat_i(31 downto 0),
-      wb_cyc_i                => wb_cyc(0),
-      wb_sel_i                => wb_sel,
-      wb_stb_i                => wb_stb,
-      wb_we_i                 => wb_we,
-      wb_ack_o                => wb_ack(0),
-      dummy_stat_reg_1_i      => dummy_stat_reg_1,
-      dummy_stat_reg_2_i      => dummy_stat_reg_2,
-      dummy_stat_reg_3_i      => dummy_stat_reg_3,
-      dummy_stat_reg_switch_i => dummy_stat_reg_switch
-      );
-
-  dummy_stat_reg_1      <= X"DEADBABE";
-  dummy_stat_reg_2      <= X"BEEFFACE";
-  dummy_stat_reg_3      <= X"12345678";
-  dummy_stat_reg_switch <= X"0000000" & "000" & p2l_pll_locked;
-
-  cmp_dummy_ctrl_regs : dummy_ctrl_regs_wb_slave
-    port map(
-      rst_n_i         => L_RST_N,
-      wb_clk_i        => l_clk,
-      wb_addr_i       => wb_adr(1 downto 0),
-      wb_data_i       => wb_dat_o,
-      wb_data_o       => wb_dat_i(63 downto 32),
-      wb_cyc_i        => wb_cyc(1),
-      wb_sel_i        => wb_sel,
-      wb_stb_i        => wb_stb,
-      wb_we_i         => wb_we,
-      wb_ack_o        => wb_ack(1),
-      dummy_reg_1_o   => dummy_ctrl_reg_1,
-      dummy_reg_2_o   => dummy_ctrl_reg_2,
-      dummy_reg_3_o   => dummy_ctrl_reg_3,
-      dummy_reg_led_o => dummy_ctrl_reg_led
-      );
-
-  LED_RED   <= dummy_ctrl_reg_led(0);
-  LED_GREEN <= dummy_ctrl_reg_led(1);
-  --LED_GREEN <= '1';
-  --LED_RED   <= p2l_pll_locked;
-
-  ------------------------------------------------------------------------------
-  -- DMA wishbone bus connected to a DPRAM
-  ------------------------------------------------------------------------------
-  process (l_clk, L_RST_N)
-  begin
-    if (L_RST_N = '0') then
-      dma_ack_i <= '0';
-    elsif rising_edge(l_clk) then
-      if (dma_cyc_o = '1' and dma_stb_o = '1') then
-        dma_ack_i <= '1';
-      else
-        dma_ack_i <= '0';
-      end if;
-    end if;
-  end process;
-
-  dma_stall_i <= '0';
-
-  ram_we(0) <= dma_we_o and dma_cyc_o and dma_stb_o;
-
-  cmp_test_ram : ram_2048x32
-    port map (
-      clka  => l_clk,
-      wea   => ram_we,
-      addra => dma_adr_o(10 downto 0),
-      dina  => dma_dat_o,
-      douta => dma_dat_i
-      );
-
-
-  ------------------------------------------------------------------------------
-  -- Interrupt stuff
-  ------------------------------------------------------------------------------
-  -- just forward irq pulses for test
-  irq_to_gn4124 <= irq_sources(1) or irq_sources(0);
-
-
-  ------------------------------------------------------------------------------
-  -- FOR TEST
-  ------------------------------------------------------------------------------
-  p_div_clk : process (l_clk, L_RST_N)
-  begin
-    if L_RST_N = '0' then
-      clk_div     <= '0';
-      clk_div_cnt <= (others => '0');
-    elsif rising_edge(l_clk) then
-      if clk_div_cnt = 4 then
-        clk_div     <= not (clk_div);
-        clk_div_cnt <= (others => '0');
-      else
-        clk_div_cnt <= clk_div_cnt + 1;
-      end if;
-    end if;
-  end process p_div_clk;
-
-
-  USER_IO_0_P <= clk_div;
-  USER_IO_0_N <= '0';
-  USER_IO_1_P <= '0';
-  USER_IO_1_N <= '0';
-
-end rtl;
-
-
diff --git a/hdl/pfc/rtl/pfc_wrapper_clk_test.vhd b/hdl/pfc/rtl/pfc_wrapper_clk_test.vhd
deleted file mode 100644
index ba40a809a29030b77119511a18b667ae42342cf5..0000000000000000000000000000000000000000
--- a/hdl/pfc/rtl/pfc_wrapper_clk_test.vhd
+++ /dev/null
@@ -1,217 +0,0 @@
---------------------------------------------------------------------------------
---                                                                            --
--- CERN BE-CO-HT         GN4124 core for PCIe FMC carrier                     --
---                       http://www.ohwr.org/projects/gn4124-core             --
---------------------------------------------------------------------------------
---
--- unit name: pfc_wrapper_clk_test (pfc_wrapper_clk_test.vhd)
---
--- author: Matthieu Cattin (matthieu.cattin@cern.ch)
---
--- date: 20-10-2010
---
--- version: 0.1
---
--- description: Wrapper for the GN4124 core to drop into the FPGA on the
---              PFC (PCIe FMC Carrier) board
---
--- dependencies:
---
---------------------------------------------------------------------------------
--- last changes: see svn log.
---------------------------------------------------------------------------------
--- TODO: - 
---------------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.NUMERIC_STD.all;
-
-library UNISIM;
-use UNISIM.vcomponents.all;
-
-
-entity pfc_wrapper_clk_test is
-  generic
-    (
-      TAR_ADDR_WDTH : integer := 13     -- not used for this project
-      );
-  port
-    (
-
-      -- Global ports
-      SYS_CLK_P : in std_logic;         -- 25MHz system clock
-      SYS_CLK_N : in std_logic;         -- 25MHz system clock
-
-      -- From GN4124 Local bus
-      L_CLKp : in std_logic;            -- Local bus clock (frequency set in GN4124 config registers)
-      L_CLKn : in std_logic;            -- Local bus clock (frequency set in GN4124 config registers)
-
-      L_RST_N : in std_logic;           -- Reset from GN4124 (RSTOUT18_N)
-
-      -- General Purpose Interface
-      GPIO : inout std_logic_vector(1 downto 0);  -- GPIO[0] -> GN4124 GPIO8
-                                                  -- GPIO[1] -> GN4124 GPIO9
-
-      -- PCIe to Local [Inbound Data] - RX
-      P2L_RDY    : out std_logic;                      -- Rx Buffer Full Flag
-      P2L_CLKn   : in  std_logic;                      -- Receiver Source Synchronous Clock-
-      P2L_CLKp   : in  std_logic;                      -- Receiver Source Synchronous Clock+
-      P2L_DATA   : in  std_logic_vector(15 downto 0);  -- Parallel receive data
-      P2L_DFRAME : in  std_logic;                      -- Receive Frame
-      P2L_VALID  : in  std_logic;                      -- Receive Data Valid
-
-      -- Inbound Buffer Request/Status
-      P_WR_REQ : in  std_logic_vector(1 downto 0);  -- PCIe Write Request
-      P_WR_RDY : out std_logic_vector(1 downto 0);  -- PCIe Write Ready
-      RX_ERROR : out std_logic;                     -- Receive Error
-
-      -- Local to Parallel [Outbound Data] - TX
-      L2P_DATA   : out std_logic_vector(15 downto 0);  -- Parallel transmit data
-      L2P_DFRAME : out std_logic;                      -- Transmit Data Frame
-      L2P_VALID  : out std_logic;                      -- Transmit Data Valid
-      L2P_CLKn   : out std_logic;                      -- Transmitter Source Synchronous Clock-
-      L2P_CLKp   : out std_logic;                      -- Transmitter Source Synchronous Clock+
-      L2P_EDB    : out std_logic;                      -- Packet termination and discard
-
-      -- Outbound Buffer Status
-      L2P_RDY    : in std_logic;                     -- Tx Buffer Full Flag
-      L_WR_RDY   : in std_logic_vector(1 downto 0);  -- Local-to-PCIe Write
-      P_RD_D_RDY : in std_logic_vector(1 downto 0);  -- PCIe-to-Local Read Response Data Ready
-      TX_ERROR   : in std_logic;                     -- Transmit Error
-      VC_RDY     : in std_logic_vector(1 downto 0);  -- Channel ready
-
-      -- Font panel LEDs
-      LED_RED   : out std_logic;
-      LED_GREEN : out std_logic;
-
-      -- User IO (eSATA connector)
-      USER_IO_0_P : out std_logic;
-      USER_IO_0_N : out std_logic;
-      USER_IO_1_P : out std_logic;
-      USER_IO_1_N : out std_logic
-      );
-end pfc_wrapper_clk_test;
-
-architecture rtl of pfc_wrapper_clk_test is
-
-
-  ------------------------------------------------------------------------------
-  -- Signals declaration
-  ------------------------------------------------------------------------------
-
-  -- System clock
-  signal sys_clk : std_logic;
-
-  -- LCLK from GN4124 used as system clock
-  signal l_clk : std_logic;
-
-  -- FOR TEST
-  signal p2l_clk         : std_logic;
-  signal p2l_clk_div_cnt : unsigned(3 downto 0);
-  signal p2l_clk_div     : std_logic;
-  signal l_clk_div_cnt   : unsigned(3 downto 0);
-  signal l_clk_div       : std_logic;
-
-
-begin
-
-
-  ------------------------------------------------------------------------------
-  -- System clock from 25MHz TCXO
-  ------------------------------------------------------------------------------
-  cmp_sysclk_buf : IBUFDS
-    generic map (
-      DIFF_TERM    => false,            -- Differential Termination
-      IBUF_LOW_PWR => true,             -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
-      IOSTANDARD   => "DEFAULT")
-    port map (
-      O  => sys_clk,                    -- Buffer output
-      I  => sys_clk_p,                  -- Diff_p buffer input (connect directly to top-level port)
-      IB => sys_clk_n                   -- Diff_n buffer input (connect directly to top-level port)
-      );
-
-  ------------------------------------------------------------------------------
-  -- Local clock from gennum LCLK
-  ------------------------------------------------------------------------------
-  cmp_l_clk_buf : IBUFDS
-    generic map (
-      DIFF_TERM    => false,            -- Differential Termination
-      IBUF_LOW_PWR => true,             -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
-      IOSTANDARD   => "DEFAULT")
-    port map (
-      O  => l_clk,                      -- Buffer output
-      I  => L_CLKp,                     -- Diff_p buffer input (connect directly to top-level port)
-      IB => L_CLKn                      -- Diff_n buffer input (connect directly to top-level port)
-      );
-
-  ------------------------------------------------------------------------------
-  -- FOR TEST
-  ------------------------------------------------------------------------------
-  cmp_p2lclk_buf : IBUFDS
-    generic map (
-      DIFF_TERM    => false,            -- Differential Termination
-      IBUF_LOW_PWR => true,             -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
-      IOSTANDARD   => "DEFAULT")
-    port map (
-      O  => p2l_clk,                    -- Buffer output
-      I  => P2L_CLKp,                   -- Diff_p buffer input (connect directly to top-level port)
-      IB => P2L_CLKn                    -- Diff_n buffer input (connect directly to top-level port)
-      );
-
-  p_div_p2l_clk : process (p2l_clk, L_RST_N)
-  begin
-    if L_RST_N = '0' then
-      p2l_clk_div     <= '0';
-      p2l_clk_div_cnt <= (others => '0');
-    elsif rising_edge(p2l_clk) then
-      if p2l_clk_div_cnt = 4 then
-        p2l_clk_div     <= not (p2l_clk_div);
-        p2l_clk_div_cnt <= (others => '0');
-      else
-        p2l_clk_div_cnt <= p2l_clk_div_cnt + 1;
-      end if;
-    end if;
-  end process p_div_p2l_clk;
-
-  p_div_l_clk : process (l_clk, L_RST_N)
-  begin
-    if L_RST_N = '0' then
-      l_clk_div     <= '0';
-      l_clk_div_cnt <= (others => '0');
-    elsif rising_edge(l_clk) then
-      if l_clk_div_cnt = 4 then
-        l_clk_div     <= not (l_clk_div);
-        l_clk_div_cnt <= (others => '0');
-      else
-        l_clk_div_cnt <= l_clk_div_cnt + 1;
-      end if;
-    end if;
-  end process p_div_l_clk;
-
-  USER_IO_0_P <= p2l_clk_div;
-  USER_IO_0_N <= l_clk_div;
-  USER_IO_1_P <= sys_clk;
-  USER_IO_1_N <= '0';
-
-  cmp_l2pclk_buf : OBUFDS
-    port map (
-      O  => L2P_CLKp,
-      OB => L2P_CLKn,
-      I  => p2l_clk
-      );
-
-  GPIO       <= "00";
-  P2L_RDY    <= '0';
-  P_WR_RDY   <= "00";
-  RX_ERROR   <= '0';
-  L2P_DATA   <= X"0000";
-  L2P_DFRAME <= '0';
-  L2P_VALID  <= '0';
-  L2P_EDB    <= '0';
-  LED_RED    <= '0';
-  LED_GREEN  <= '1';
-
-end rtl;
-
-
diff --git a/hdl/spec/rtl/generic_async_fifo_wrapper.vhd b/hdl/spec/rtl/generic_async_fifo_wrapper.vhd
deleted file mode 100644
index 47382cad39cb7050ffc93afe175440830f8a4146..0000000000000000000000000000000000000000
--- a/hdl/spec/rtl/generic_async_fifo_wrapper.vhd
+++ /dev/null
@@ -1,180 +0,0 @@
---------------------------------------------------------------------------------
--- CERN (BE-CO-HT)
--- Generic asynchronous FIFO wrapper
--- http://www.ohwr.org/projects/fmc-adc-100m14b4cha
---------------------------------------------------------------------------------
---
--- unit name: generic_async_fifo (generic_async_fifo_wrapper.vhd)
---
--- author: Matthieu Cattin (matthieu.cattin@cern.ch)
---
--- date: 05-12-2011
---
--- version: 1.0
---
--- description: Wrapper to use Xilinx Coregen FIFOs instead of generic FIFOs
---              from Generics RAMs and FIFOs collection.
---
--- dependencies:
---
---------------------------------------------------------------------------------
--- last changes: see svn log.
---------------------------------------------------------------------------------
--- TODO: - 
---------------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.NUMERIC_STD.all;
-
-library XilinxCoreLib;
-
-use work.gn4124_core_pkg.all;
-
-
-entity generic_async_fifo is
-
-  generic (
-    g_data_width : natural;
-    g_size       : natural;
-    g_show_ahead : boolean := false;
-
-    -- Read-side flag selection
-    g_with_rd_empty        : boolean := true;   -- with empty flag
-    g_with_rd_full         : boolean := false;  -- with full flag
-    g_with_rd_almost_empty : boolean := false;
-    g_with_rd_almost_full  : boolean := false;
-    g_with_rd_count        : boolean := false;  -- with words counter
-
-    g_with_wr_empty        : boolean := false;
-    g_with_wr_full         : boolean := true;
-    g_with_wr_almost_empty : boolean := false;
-    g_with_wr_almost_full  : boolean := false;
-    g_with_wr_count        : boolean := false;
-
-    g_almost_empty_threshold : integer;  -- threshold for almost empty flag
-    g_almost_full_threshold  : integer   -- threshold for almost full flag
-    );
-
-  port (
-    rst_n_i : in std_logic := '1';
-
-    -- write port
-    clk_wr_i : in std_logic;
-    d_i      : in std_logic_vector(g_data_width-1 downto 0);
-    we_i     : in std_logic;
-
-    wr_empty_o        : out std_logic;
-    wr_full_o         : out std_logic;
-    wr_almost_empty_o : out std_logic;
-    wr_almost_full_o  : out std_logic;
-    wr_count_o        : out std_logic_vector(log2_ceil(g_size)-1 downto 0);
-
-    -- read port
-    clk_rd_i : in  std_logic;
-    q_o      : out std_logic_vector(g_data_width-1 downto 0);
-    rd_i     : in  std_logic;
-
-    rd_empty_o        : out std_logic;
-    rd_full_o         : out std_logic;
-    rd_almost_empty_o : out std_logic;
-    rd_almost_full_o  : out std_logic;
-    rd_count_o        : out std_logic_vector(log2_ceil(g_size)-1 downto 0)
-    );
-
-end generic_async_fifo;
-
-
-architecture syn of generic_async_fifo is
-
-
-  component fifo_32x512
-    port (
-      rst                     : in  std_logic;
-      wr_clk                  : in  std_logic;
-      rd_clk                  : in  std_logic;
-      din                     : in  std_logic_vector(31 downto 0);
-      wr_en                   : in  std_logic;
-      rd_en                   : in  std_logic;
-      prog_full_thresh_assert : in  std_logic_vector(8 downto 0);
-      prog_full_thresh_negate : in  std_logic_vector(8 downto 0);
-      dout                    : out std_logic_vector(31 downto 0);
-      full                    : out std_logic;
-      empty                   : out std_logic;
-      valid                   : out std_logic;
-      prog_full               : out std_logic);
-  end component fifo_32x512;
-
-  component fifo_64x512
-    port (
-      rst                     : in  std_logic;
-      wr_clk                  : in  std_logic;
-      rd_clk                  : in  std_logic;
-      din                     : in  std_logic_vector(63 downto 0);
-      wr_en                   : in  std_logic;
-      rd_en                   : in  std_logic;
-      prog_full_thresh_assert : in  std_logic_vector(8 downto 0);
-      prog_full_thresh_negate : in  std_logic_vector(8 downto 0);
-      dout                    : out std_logic_vector(63 downto 0);
-      full                    : out std_logic;
-      empty                   : out std_logic;
-      valid                   : out std_logic;
-      prog_full               : out std_logic);
-  end component fifo_64x512;
-
-
-  signal rst : std_logic;
-
-
-begin
-
-  -- Active high reset for FIFOs
-  rst <= not(rst_n_i);
-
-  -- Assign unused outputs
-  wr_empty_o <= '0';
-  wr_almost_empty_o <= '0';
-  wr_count_o <= (others => '0');
-  rd_full_o <= '0';
-  rd_almost_full_o <= '0';
-  rd_almost_empty_o <= '0';
-  rd_count_o <= (others => '0');
-
-  gen_fifo_32bit : if g_data_width = 32 generate
-    cmp_fifo_32x512 : fifo_32x512
-      port map (
-        rst                     => rst,
-        wr_clk                  => clk_wr_i,
-        rd_clk                  => clk_rd_i,
-        din                     => d_i,
-        wr_en                   => we_i,
-        rd_en                   => rd_i,
-        prog_full_thresh_assert => std_logic_vector(to_unsigned(g_almost_full_threshold, 9)),
-        prog_full_thresh_negate => std_logic_vector(to_unsigned(g_almost_full_threshold, 9)),
-        dout                    => q_o,
-        full                    => wr_full_o,
-        empty                   => rd_empty_o,
-        valid                   => open,
-        prog_full               => wr_almost_full_o);
-  end generate gen_fifo_32bit;
-
-  gen_fifo_64bit : if g_data_width = 64 generate
-    cmp_fifo_64x512 : fifo_64x512
-      port map (
-        rst                     => rst,
-        wr_clk                  => clk_wr_i,
-        rd_clk                  => clk_rd_i,
-        din                     => d_i,
-        wr_en                   => we_i,
-        rd_en                   => rd_i,
-        prog_full_thresh_assert => std_logic_vector(to_unsigned(g_almost_full_threshold, 9)),
-        prog_full_thresh_negate => std_logic_vector(to_unsigned(g_almost_full_threshold, 9)),
-        dout                    => q_o,
-        full                    => wr_full_o,
-        empty                   => rd_empty_o,
-        valid                   => open,
-        prog_full               => wr_almost_full_o);
-  end generate gen_fifo_64bit;
-
-
-end syn;