From 4a430afae7cb37702b7c19f9e7f9934a7f252ed1 Mon Sep 17 00:00:00 2001
From: Matthieu Cattin <matthieu.cattin@cern.ch>
Date: Thu, 20 Mar 2014 10:00:28 +0100
Subject: [PATCH] Reduce the sync fifo depth (csr wishbone master).
---
hdl/gn4124core/rtl/wbmaster32.vhd | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hdl/gn4124core/rtl/wbmaster32.vhd b/hdl/gn4124core/rtl/wbmaster32.vhd
index 16555c2..96fc322 100644
--- a/hdl/gn4124core/rtl/wbmaster32.vhd
+++ b/hdl/gn4124core/rtl/wbmaster32.vhd
@@ -315,7 +315,7 @@ begin
cmp_fifo_to_wb : generic_async_fifo
generic map (
g_data_width => 64,
- g_size => 512,
+ g_size => 128,
g_show_ahead => false,
g_with_rd_empty => true,
g_with_rd_full => false,
@@ -356,7 +356,7 @@ begin
cmp_from_wb_fifo : generic_async_fifo
generic map (
g_data_width => 32,
- g_size => 512,
+ g_size => 128,
g_show_ahead => false,
g_with_rd_empty => true,
g_with_rd_full => false,
--
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