Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
P
Platform-independent core collection
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
18
Issues
18
List
Board
Labels
Milestones
Merge Requests
5
Merge Requests
5
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
Platform-independent core collection
Issues
Open
18
Closed
36
All
54
New issue
Recent searches
Press Enter or click to search
{{hint}}
{{tag}}
{{name}}
@{{username}}
No Assignee
{{name}}
@{{username}}
No Milestone
Upcoming
Started
{{title}}
No Label
{{title}}
{{name}}
Yes
No
Created date
Priority
Created date
Last updated
Milestone
Due date
Popularity
Label priority
gc_sync/gc_sync_register fail simulation under GHDL
#55
· opened
Mar 14, 2024
by
Adrian Byszuk
bug
CLOSED
2
updated
Mar 19, 2024
Support Verilog output with gen_sourceid tool
#54
· opened
Jan 30, 2024
by
Dimitris Lampridis
0
updated
Jan 30, 2024
Linux driver for wb simple uart
#53
· opened
Jan 23, 2024
by
Piotr Klasa
0
updated
Jan 24, 2024
possible_fix_in_wb_uart_rx_fifo
#52
· opened
Jan 23, 2024
by
Konstantinos Blantos
CLOSED
0
updated
Jan 26, 2024
inferred_async_fifo_dual_reset : spurious pulse on almost_full_int after reset
#51
· opened
Jan 22, 2024
by
Alexis Marquet
0
updated
Jan 22, 2024
add rx/tx interrupt enable in wb_uart
#50
· opened
Jan 15, 2024
by
Konstantinos Blantos
0
updated
Jan 15, 2024
add a fifo with mixed width
#49
· opened
Dec 21, 2023
by
Tristan Gingold
0
updated
Dec 21, 2023
fifo: minor cleanup
#48
· opened
Dec 20, 2023
by
Tristan Gingold
CLOSED
0
updated
Dec 21, 2023
revert version of wb_uart
#47
· opened
Dec 15, 2023
by
Konstantinos Blantos
0
updated
Dec 15, 2023
demo_vunit_ghdl_testbench
#46
· opened
Dec 12, 2023
by
Konstantinos Blantos
0
updated
Dec 12, 2023
Addition of a register in wb_uart to show the endianess
#45
· opened
Dec 08, 2023
by
Konstantinos Blantos
CLOSED
0
updated
Jan 15, 2024
wb_uart new features
#44
· opened
Dec 04, 2023
by
Konstantinos Blantos
CLOSED
0
updated
Dec 08, 2023
generate_cdc_constraints.tcl creates faulty constraints with path segmentation
#43
· opened
Sep 27, 2023
by
Adrian Byszuk
bug
1
0
updated
Sep 27, 2023
generate_cdc_constraints.tcl fails when using gc_sync_word* if some of Q[?] have been optimized out after synth
#42
· opened
Sep 01, 2023
by
Alexis Marquet
CLOSED
1
updated
Sep 05, 2023
fine_pulse_gen: tune clocking
#41
· opened
Jun 01, 2023
by
Tristan Gingold
CLOSED
0
updated
Jun 01, 2023
genram_pkg: disable bound checking in synthesis
#40
· opened
Jun 01, 2023
by
Tristan Gingold
CLOSED
0
updated
Jun 01, 2023
gc_serial_dac avoid overwrite
#39
· opened
Jun 01, 2023
by
Tristan Gingold
CLOSED
0
updated
Jun 01, 2023
add keep attributes
#38
· opened
Jun 01, 2023
by
Tristan Gingold
CLOSED
0
updated
Jun 01, 2023
gc_pulse_synchronizer2 use async reset
#37
· opened
Jun 01, 2023
by
Tristan Gingold
CLOSED
0
updated
Jun 01, 2023
gc_sync (and other CDC constraints) not recognized by Vivado
#36
· opened
May 22, 2023
by
Tomasz Wlostowski
CLOSED
2
updated
Jun 01, 2023
Prev
1
2
3
Next