The BVALID signal must be asserted once the write operation is
completed.  The master is not required to assert BREADY before this
happens.  The old code happened to work if the master tied BREADY
high, which is allowed but not required.

The response should not be EXOKAY unless an atomic access is requested
by the master using the LOCK signals.  This bridge does not even
support atomic accesses (it's an AXI4-Lite slave and does not have the
LOCK signals) so it's required to respond OKAY even if the master
does attempt an atomic access (this is how the master knows that the
slave does not support atomic accesses).  The AXI4-Lite specification
clearly states that the EXOKAY response is not supported in AXI4-Lite.

This bugfix has been tested by myself on the latest development version of SPEC-based FMC-ADC, as
well as by M. Lipinski on BTrain test setup.

Closes #23.

The only reason for this is to improve readability and reduce the usage of gc_posedge/gc_negedge, in
case we want to deprecate them in the near future.
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

The main reason for doing this is so that all our sync modules are based directly on
gc_sync (instead of using it indirectly through gc_sync_ffs).

Another benefit of this is that the feedback loop of the pulse synchroniser will now be two clock
cycles shorter (one input clock cycle + one output clock cycle), since gc_sync_ffs is using one
more flip-flop compared to gc_sync.

This will also reduce the number of warnings in various synthesis and simulation tools, since
gc_pulse_syncrhonizer is also used by the gc_sync_word modules, as well as the async dual clock
FIFOs.
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

This was recently introduced by T. Gingold and we both agreed that it is not really adding much
value, as it can be easily replaced by the more versatile combination ofgc_sync + gc_edge_detect.
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

This is necessary in order to properly "emulate" the previous implementation
of the gc_sync_ffs module.

Furthermore, a "new" module has been introduced, the gc_edge_detect, which
combines positive and negative pulse edge detection. gc_negedge and gc_posedge
have been rewritten to use internally the new gc_edge_detect.
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

This is to avoid any confusion caused by g_SYNC_EDGE and g_EDGE
generics used in gc_sync, gc_sync_ffs and gc_sync_edge modules.

Also use capitals for generics as defined by our coding style.
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

This generic is dummy (does nothing), yet it is needed since the
generic component declaration in genram_pkg.vhd has such generic.
It has it, because the xilinx generic_dpram.vhd has such generic
and uses it.
TBD whether we want to attempt at providing similar functionality
for altera

Reported by Olof Kindgren (@olofk). See also merge request !4.
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

1.0.4 - 2020-03-26
==================
https://www.ohwr.org/project/general-cores/tags/v1.0.4

Added
-----
- [hdl] VHDL functions to convert characters and strings to upper/lower case.
- [sw][i2c] Support for kernel greater than 4.7.
- [hdl] Separate synchroniser and edge detection modules.
- [hdl] 8b10b encoder.

Changed
-------
- [hdl] Rewritten the WB master interface used in simulations.
- [hdl] Reimplement gc_sync_ffs using new synchroniser and edge detectors.

Fixed
-----
- [sw][spi] Align polarity and phase for Rx and Tx.
- [hdl][i2c] Fix reset lock for I2C master.
- [hdl] Avoid cyclic dependencies for log2 ceiling functions.

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Using the guidelines from here:
https://gitlab.cern.ch/be-co-ht-documents/project-management-guidelines/-/blob/master/how-to-write-changelog.rstSigned-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Instead of check for version here and there, the main code always uses
the latest API, and in a preprocessor ``if`` statement I implemented
the compatibility layer.

Like this it will be easier to apply patches from the kernel to our
local driver
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

sw:  Update spi-ocores

See merge request !3

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Also perform cleanup of sync and edge modules.
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Reported by Olof Olof Kindgren (@olofk). See also merge request !4.
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

This allows them to be used right after in component declarations.
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>