Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Using the guidelines from here:
https://gitlab.cern.ch/be-co-ht-documents/project-management-guidelines/-/blob/master/how-to-write-changelog.rstSigned-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Instead of check for version here and there, the main code always uses
the latest API, and in a preprocessor ``if`` statement I implemented
the compatibility layer.

Like this it will be easier to apply patches from the kernel to our
local driver
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

sw:  Update spi-ocores

See merge request !3

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Also perform cleanup of sync and edge modules.
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Reported by Olof Olof Kindgren (@olofk). See also merge request !4.
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

This allows them to be used right after in component declarations.
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

This is especially beneficial when trying to meet timing in the GN4124 core (on Spartan6), where the
async FIFOs are clocked on one side at 200MHz. Apparently, the KEEP_HIERARCHY attribute makes it
much easier for ISE 14.7 to reach timing closure.

It also helps in general to ensure that the synchronisation structures remain intact and do not get
merged in unpredictable ways with other parts of the design.
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Align polarity and phase for SPI_OCORES_CTRL_Tx_NEG and SPI_OCORES_CTRL_Rx_NEG
with check for SPI_CPHA and mode(CPOL).
Signed-off-by: Mamta Shukla <mamta.ramendra.shukla@cern.ch>

Signed-off-by: Mamta Shukla <mamta.ramendra.shukla@cern.ch>

The WB master interface has been re-written, in order to improve performance, compatibility with the
"standard" and code readability.

The new interface has been successfully verified with existing testbenches from the following
projects:

* wr-cores
* wr-switch-hdl
* mockturtle
* ddr3-sp6-core
* fmc-adc-100m14b4cha
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

Signed-off-by: Federico Vaga <federico.vaga@cern.ch>