- rework simdrv_defs into a package
- use SV queues instead of dynamic arrays in the APIs (as they resemble C++'s std::vector a bit more, hence are more convenient to use)
- added AXI4 BFMs from the PULP project library
- added a bunch of simulation drivers (for the VUART & LM32 MCS cores)
- added a trivial unit test/logging "framework" (see logger.svh)

Note these changes will break your legacy testbenches, here's how to fix the most common issues:
- Replace the includes of simdrv_defs.svh indo an include of "gencores_sim_defs.svh" followed by
  import of gencores_sim_pkg package
- If your code uses CBusAccessor::readm/writem, change the addr/data parameters to use SV queues instead of dynamic arrays

genrams: added g_implementation_hint RAM/FIFO attribute allowing to select the memory primitive used to implement the RAM.

Currently only works on Xilinx FPGAs (the choices being "ultra", "block", "distributed", and the default "auto") and is ignored in other platforms.

Wraps an LM32, DPRAM, UART and indirect memory loader.

inferred_async_fifo: avoid nested 'others' clause in signal initialization to keep ISE (Virtex5) happy