dsp/gc_pi_regulator.vhd : limit is a reserved word in AMS-VHDL (ghdl warning), changing to lim and removing unused signal.

dsp/gc_pi_regulator: synthesis fails when g_INTEGRATOR_BITS is bigger than 32 as the vhdl integer type is only 32 bits wide. Removing unused constants.

genrams: added g_implementation_hint RAM/FIFO attribute allowing to select the memory primitive used to implement the RAM.

Currently only works on Xilinx FPGAs (the choices being "ultra", "block", "distributed", and the default "auto") and is ignored in other platforms.

Wraps an LM32, DPRAM, UART and indirect memory loader.

inferred_async_fifo: avoid nested 'others' clause in signal initialization to keep ISE (Virtex5) happy

modules/dsp: a collection of DSP modules ported from the CommonVisual library. Not yet tested. LICENSING TO BE FIXED!

Add scoped XDC constraints for CDC modules

See merge request !16

These XDC files can be used by Vivado projects to automatically infer
proper timing constraints for CDC paths.

Fix reset CDC issue in gc_sync_word_rd

See merge request !15

Fix wb_ack_o violation in wb_simple_timer

See merge request !14

The clk_out domain mistakenly used reset from clk_in domain.
Additionally, the data_out_o port had this reset signal connected mistakenly as clock enable.

Fixes issue #29

Logically it's exactly the same, but for some reason Synplify doesn't
like "/=" for file opening status.

sim/if_wb_master: fix wb classic broken in commit cbc1c428: [sim] rewrite of the WB master interface