Skip to content

P
Platform-independent core collection
Commit fa8df2bb authored by Dimitris Lampridis's avatar Dimitris Lampridis
Browse files
Options

Clean-up non-ASCII characters and fix line feeds and terminations in all affected files

parent 284373b7
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 1468 additions and 1468 deletions
doc/general-cores.in
View file @ fa8df2bb
......@@ -42,7 +42,7 @@
@titlepage
@title @code{general-cores} VHDL library
@subtitle Programmer's manual
@author CERN BE-CO-HT / Tomasz Włostowski
@author CERN BE-CO-HT / Tomasz Wlostowski
@end titlepage
@headings single
......
modules/axi/axi4_pkg.vhd
View file @ fa8df2bb
This diff is collapsed.
modules/common/gc_arbitrated_mux.vhd
View file @ fa8df2bb
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2012-02-21
-- Last update: 2019-09-09
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -17,13 +17,13 @@
-- Copyright (c) 2011 CERN / BE-CO-HT
--
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 0.51 (the “License”) (which enables you, at your option,
-- License, Version 0.51 (the "License") (which enables you, at your option,
-- to treat this file as licensed under the Apache License 2.0); you may not
-- use this file except in compliance with the License. You may obtain a copy
-- of the License at http://solderpad.org/licenses/SHL-0.51.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--
......
modules/common/gc_async_signals_input_stage.vhd
View file @ fa8df2bb
......@@ -34,13 +34,13 @@
-- Copyright (c) 2016 CERN/TE-MS-MM
--
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 0.51 (the “License”) (which enables you, at your option,
-- License, Version 0.51 (the "License") (which enables you, at your option,
-- to treat this file as licensed under the Apache License 2.0); you may not
-- use this file except in compliance with the License. You may obtain a copy
-- of the License at http://solderpad.org/licenses/SHL-0.51.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--
......
modules/common/gc_bicolor_led_ctrl.vhd
View file @ fa8df2bb
......@@ -49,13 +49,13 @@
-- Copyright (c) 2012 - 2017 CERN
--
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 0.51 (the “License”) (which enables you, at your option,
-- License, Version 0.51 (the "License") (which enables you, at your option,
-- to treat this file as licensed under the Apache License 2.0); you may not
-- use this file except in compliance with the License. You may obtain a copy
-- of the License at http://solderpad.org/licenses/SHL-0.51.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--
......
modules/common/gc_extend_pulse.vhd
View file @ fa8df2bb
......@@ -18,13 +18,13 @@
-- Copyright (c) 2009-2011 CERN
--
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 0.51 (the “License”) (which enables you, at your option,
-- License, Version 0.51 (the "License") (which enables you, at your option,
-- to treat this file as licensed under the Apache License 2.0); you may not
-- use this file except in compliance with the License. You may obtain a copy
-- of the License at http://solderpad.org/licenses/SHL-0.51.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--
......
modules/common/gc_reset.vhd
View file @ fa8df2bb
......@@ -10,13 +10,13 @@
-- Copyright (c) 2012-2017 CERN
--
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 0.51 (the “License”) (which enables you, at your option,
-- License, Version 0.51 (the "License") (which enables you, at your option,
-- to treat this file as licensed under the Apache License 2.0); you may not
-- use this file except in compliance with the License. You may obtain a copy
-- of the License at http://solderpad.org/licenses/SHL-0.51.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
-------------------------------------------------------------------------------
......
modules/common/gc_serial_dac.vhd
View file @ fa8df2bb
......@@ -6,7 +6,7 @@
-- Author : Pablo Alvarez Sanchez
-- Company : CERN BE-Co-HT
-- Created : 2010-02-25
-- Last update: 2011-04-29
-- Last update: 2019-09-09
-- Platform : FPGA-generic
-- Standard : VHDL '87
-------------------------------------------------------------------------------
......@@ -17,13 +17,13 @@
-- Copyright (c) 2009 - 2010 CERN
--
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 0.51 (the “License”) (which enables you, at your option,
-- License, Version 0.51 (the "License") (which enables you, at your option,
-- to treat this file as licensed under the Apache License 2.0); you may not
-- use this file except in compliance with the License. You may obtain a copy
-- of the License at http://solderpad.org/licenses/SHL-0.51.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--
......
modules/genrams/xilinx/generic_simple_dpram.vhd
View file @ fa8df2bb
......@@ -21,13 +21,13 @@
-- Copyright (c) 2011 CERN
--
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 0.51 (the “License”) (which enables you, at your option,
-- License, Version 0.51 (the "License") (which enables you, at your option,
-- to treat this file as licensed under the Apache License 2.0); you may not
-- use this file except in compliance with the License. You may obtain a copy
-- of the License at http://solderpad.org/licenses/SHL-0.51.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--
......
modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd
View file @ fa8df2bb
-------------------------------------------------------------------------------
-- Title : AXI4Lite-to-WB bridge
-- Project : General Cores
-------------------------------------------------------------------------------
-- File : wb_axi4lite_bridge.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Platform : FPGA-generics
-- Standard : VHDL '93
-------------------------------------------------------------------------------
-- Copyright (c) 2017 CERN
--
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 0.51 (the “License”) (which enables you, at your option,
-- to treat this file as licensed under the Apache License 2.0); you may not
-- use this file except in compliance with the License. You may obtain a copy
-- of the License at http://solderpad.org/licenses/SHL-0.51.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.axi4_pkg.all;
use work.wishbone_pkg.all;
entity wb_axi4lite_bridge is
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
ARVALID : in std_logic;
AWVALID : in std_logic;
BREADY : in std_logic;
RREADY : in std_logic;
WLAST : in std_logic;
WVALID : in std_logic;
ARADDR : in std_logic_vector (31 downto 0);
AWADDR : in std_logic_vector (31 downto 0);
WDATA : in std_logic_vector (31 downto 0);
WSTRB : in std_logic_vector (3 downto 0);
ARREADY : out std_logic;
AWREADY : out std_logic;
BVALID : out std_logic;
RLAST : out std_logic;
RVALID : out std_logic;
WREADY : out std_logic;
BRESP : out std_logic_vector (1 downto 0);
RRESP : out std_logic_vector (1 downto 0);
RDATA : out std_logic_vector (31 downto 0);
wb_adr : out std_logic_vector(c_wishbone_address_width-1 downto 0);
wb_dat_m2s : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_sel : out std_logic_vector(c_wishbone_data_width/8-1 downto 0);
wb_cyc : out std_logic;
wb_stb : out std_logic;
wb_we : out std_logic;
wb_dat_s2m : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_err : in std_logic := '0';
wb_rty : in std_logic := '0';
wb_ack : in std_logic;
wb_stall : in std_logic
);
end wb_axi4lite_bridge;
architecture rtl of wb_axi4lite_bridge is
signal axi_in : t_axi4_lite_master_out_32;
signal axi_out : t_axi4_lite_master_in_32;
signal wb_in : t_wishbone_master_in;
signal wb_out : t_wishbone_master_out;
begin
axi_in.ARVALID <= ARVALID;
axi_in.AWVALID <= AWVALID;
axi_in.BREADY <= BREADY;
axi_in.RREADY <= RREADY;
axi_in.WLAST <= WLAST;
axi_in.WVALID <= WVALID;
axi_in.ARADDR <= ARADDR;
axi_in.AWADDR <= AWADDR;
axi_in.WDATA <= WDATA;
axi_in.WSTRB <= WSTRB;
ARREADY <= axi_out.ARREADY;
AWREADY <= axi_out.AWREADY;
BVALID <= axi_out.BVALID;
RLAST <= axi_out.RLAST;
RVALID <= axi_out.RVALID;
WREADY <= axi_out.WREADY;
BRESP <= axi_out.BRESP;
RRESP <= axi_out.RRESP;
RDATA <= axi_out.RDATA;
wb_adr <= wb_out.adr;
wb_dat_m2s <= wb_out.dat;
wb_stb <= wb_out.stb;
wb_sel <= wb_out.sel;
wb_cyc <= wb_out.cyc;
wb_we <= wb_out.we;
wb_in.err <= wb_err;
wb_in.rty <= wb_rty;
wb_in.ack <= wb_ack;
wb_in.stall <= wb_stall;
wb_in.dat <= wb_dat_s2m;
U_Wrapped_Bridge : xwb_axi4lite_bridge
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
axi4_slave_i => axi_in,
axi4_slave_o => axi_out,
wb_master_o => wb_out,
wb_master_i => wb_in);
end rtl;
-------------------------------------------------------------------------------
-- Title : AXI4Lite-to-WB bridge
-- Project : General Cores
-------------------------------------------------------------------------------
-- File : wb_axi4lite_bridge.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Platform : FPGA-generics
-- Standard : VHDL '93
-------------------------------------------------------------------------------
-- Copyright (c) 2017 CERN
--
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 0.51 (the "License") (which enables you, at your option,
-- to treat this file as licensed under the Apache License 2.0); you may not
-- use this file except in compliance with the License. You may obtain a copy
-- of the License at http://solderpad.org/licenses/SHL-0.51.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.axi4_pkg.all;
use work.wishbone_pkg.all;
entity wb_axi4lite_bridge is
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
ARVALID : in std_logic;
AWVALID : in std_logic;
BREADY : in std_logic;
RREADY : in std_logic;
WLAST : in std_logic;
WVALID : in std_logic;
ARADDR : in std_logic_vector (31 downto 0);
AWADDR : in std_logic_vector (31 downto 0);
WDATA : in std_logic_vector (31 downto 0);
WSTRB : in std_logic_vector (3 downto 0);
ARREADY : out std_logic;
AWREADY : out std_logic;
BVALID : out std_logic;
RLAST : out std_logic;
RVALID : out std_logic;
WREADY : out std_logic;
BRESP : out std_logic_vector (1 downto 0);
RRESP : out std_logic_vector (1 downto 0);
RDATA : out std_logic_vector (31 downto 0);
wb_adr : out std_logic_vector(c_wishbone_address_width-1 downto 0);
wb_dat_m2s : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_sel : out std_logic_vector(c_wishbone_data_width/8-1 downto 0);
wb_cyc : out std_logic;
wb_stb : out std_logic;
wb_we : out std_logic;
wb_dat_s2m : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_err : in std_logic := '0';
wb_rty : in std_logic := '0';
wb_ack : in std_logic;
wb_stall : in std_logic
);
end wb_axi4lite_bridge;
architecture rtl of wb_axi4lite_bridge is
signal axi_in : t_axi4_lite_master_out_32;
signal axi_out : t_axi4_lite_master_in_32;
signal wb_in : t_wishbone_master_in;
signal wb_out : t_wishbone_master_out;
begin
axi_in.ARVALID <= ARVALID;
axi_in.AWVALID <= AWVALID;
axi_in.BREADY <= BREADY;
axi_in.RREADY <= RREADY;
axi_in.WLAST <= WLAST;
axi_in.WVALID <= WVALID;
axi_in.ARADDR <= ARADDR;
axi_in.AWADDR <= AWADDR;
axi_in.WDATA <= WDATA;
axi_in.WSTRB <= WSTRB;
ARREADY <= axi_out.ARREADY;
AWREADY <= axi_out.AWREADY;
BVALID <= axi_out.BVALID;
RLAST <= axi_out.RLAST;
RVALID <= axi_out.RVALID;
WREADY <= axi_out.WREADY;
BRESP <= axi_out.BRESP;
RRESP <= axi_out.RRESP;
RDATA <= axi_out.RDATA;
wb_adr <= wb_out.adr;
wb_dat_m2s <= wb_out.dat;
wb_stb <= wb_out.stb;
wb_sel <= wb_out.sel;
wb_cyc <= wb_out.cyc;
wb_we <= wb_out.we;
wb_in.err <= wb_err;
wb_in.rty <= wb_rty;
wb_in.ack <= wb_ack;
wb_in.stall <= wb_stall;
wb_in.dat <= wb_dat_s2m;
U_Wrapped_Bridge : xwb_axi4lite_bridge
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
axi4_slave_i => axi_in,
axi4_slave_o => axi_out,
wb_master_o => wb_out,
wb_master_i => wb_in);
end rtl;
modules/wishbone/wb_irq/msidemo/crt0.S
View file @ fa8df2bb
This diff is collapsed.
modules/wishbone/wb_lm32/platform/kintex7/jtag_tap.v
View file @ fa8df2bb
module jtag_tap(
output tck,
output tdi,
input tdo,
output capture,
output shift,
output e1dr,
output update,
output reset
);
// Unfortunately the exit1 state for DR (e1dr) is mising
// We can simulate it by interpretting 'update' as e1dr and delaying 'update'
wire sel;
wire g_capture;
wire g_shift;
wire g_update;
reg update_delay;
assign capture = g_capture & sel;
assign shift = g_shift & sel;
assign e1dr = g_update & sel;
assign update = update_delay;
BSCANE2 #(
.JTAG_CHAIN(1)
) bscan (
.CAPTURE(g_capture),
.DRCK(tck),
.RESET(reset),
.RUNTEST(),
.SEL(sel),
.SHIFT(g_shift),
.TCK(),
.TDI(tdi),
.TMS(),
.UPDATE(g_update),
.TDO(tdo)
);
always@(posedge tck)
update_delay <= g_update;
endmodule
module jtag_tap(
output tck,
output tdi,
input tdo,
output capture,
output shift,
output e1dr,
output update,
output reset
);
// Unfortunately the exit1 state for DR (e1dr) is mising
// We can simulate it by interpretting 'update' as e1dr and delaying 'update'
wire sel;
wire g_capture;
wire g_shift;
wire g_update;
reg update_delay;
assign capture = g_capture & sel;
assign shift = g_shift & sel;
assign e1dr = g_update & sel;
assign update = update_delay;
BSCANE2 #(
.JTAG_CHAIN(1)
) bscan (
.CAPTURE(g_capture),
.DRCK(tck),
.RESET(reset),
.RUNTEST(),
.SEL(sel),
.SHIFT(g_shift),
.TCK(),
.TDI(tdi),
.TMS(),
.UPDATE(g_update),
.TDO(tdo)
);
always@(posedge tck)
update_delay <= g_update;
endmodule
modules/wishbone/wb_lm32/platform/kintex7/lm32_multiplier.v
View file @ fa8df2bb
// =============================================================================
// COPYRIGHT NOTICE
// Copyright 2006 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// This confidential and proprietary software may be used only as authorised by
// a licensing agreement from Lattice Semiconductor Corporation.
// The entire notice above must be reproduced on all authorized copies and
// copies may only be made to the extent permitted by a licensing agreement from
// Lattice Semiconductor Corporation.
//
// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
// 5555 NE Moore Court 408-826-6000 (other locations)
// Hillsboro, OR 97124 web : http://www.latticesemi.com/
// U.S.A email: techsupport@latticesemi.com
// =============================================================================/
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_multiplier.v
// Title : Pipelined multiplier.
// Dependencies : lm32_include.v
// Version : 6.1.17
// : Initial Release
// Version : 7.0SP2, 3.0
// : No Change
// Version : 3.1
// : No Change
// =============================================================================
`include "../../src/lm32_include.v"
//`include "lm32_include.v"
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
module lm32_multiplier (
// ----- Inputs -----
clk_i,
rst_i,
stall_x,
stall_m,
operand_0,
operand_1,
// ----- Ouputs -----
result
);
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
input clk_i; // Clock
input rst_i; // Reset
input stall_x; // Stall instruction in X stage
input stall_m; // Stall instruction in M stage
input [`LM32_WORD_RNG] operand_0; // Muliplicand
input [`LM32_WORD_RNG] operand_1; // Multiplier
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
output [`LM32_WORD_RNG] result; // Product of multiplication
wire [`LM32_WORD_RNG] result;
/////////////////////////////////////////////////////
// Internal nets and registers
/////////////////////////////////////////////////////
// Divide multiplicands into high and low
`define HALF_WORD_WIDTH (`LM32_WORD_WIDTH/2)
`define HALF_WORD_RNG (`HALF_WORD_WIDTH-1):0
// Result = c+d+e = a*b
reg [`HALF_WORD_RNG] a0, a1, b0, b1;
reg [`HALF_WORD_RNG] c0, c1;
reg [`HALF_WORD_RNG] d1, e1;
reg [`HALF_WORD_RNG] result0, result1;
assign result = {result1, result0};
/////////////////////////////////////////////////////
// Sequential logic
/////////////////////////////////////////////////////
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
a0 <= {`HALF_WORD_WIDTH{1'b0}};
a1 <= {`HALF_WORD_WIDTH{1'b0}};
b0 <= {`HALF_WORD_WIDTH{1'b0}};
b1 <= {`HALF_WORD_WIDTH{1'b0}};
c0 <= {`HALF_WORD_WIDTH{1'b0}};
c1 <= {`HALF_WORD_WIDTH{1'b0}};
d1 <= {`HALF_WORD_WIDTH{1'b0}};
e1 <= {`HALF_WORD_WIDTH{1'b0}};
result0 <= {`HALF_WORD_WIDTH{1'b0}};
result1 <= {`HALF_WORD_WIDTH{1'b0}};
end
else
begin
if (stall_x == `FALSE)
begin
{a1, a0} <= operand_0;
{b1, b0} <= operand_1;
end
if (stall_m == `FALSE)
begin
{c1, c0} <= a0 * b0;
d1 <= a0 * b1;
e1 <= a1 * b0;
end
result0 <= c0;
result1 <= c1 + d1 + e1;
end
end
endmodule
// =============================================================================
// COPYRIGHT NOTICE
// Copyright 2006 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// This confidential and proprietary software may be used only as authorised by
// a licensing agreement from Lattice Semiconductor Corporation.
// The entire notice above must be reproduced on all authorized copies and
// copies may only be made to the extent permitted by a licensing agreement from
// Lattice Semiconductor Corporation.
//
// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
// 5555 NE Moore Court 408-826-6000 (other locations)
// Hillsboro, OR 97124 web : http://www.latticesemi.com/
// U.S.A email: techsupport@latticesemi.com
// =============================================================================/
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_multiplier.v
// Title : Pipelined multiplier.
// Dependencies : lm32_include.v
// Version : 6.1.17
// : Initial Release
// Version : 7.0SP2, 3.0
// : No Change
// Version : 3.1
// : No Change
// =============================================================================
`include "../../src/lm32_include.v"
//`include "lm32_include.v"
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
module lm32_multiplier (
// ----- Inputs -----
clk_i,
rst_i,
stall_x,
stall_m,
operand_0,
operand_1,
// ----- Ouputs -----
result
);
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
input clk_i; // Clock
input rst_i; // Reset
input stall_x; // Stall instruction in X stage
input stall_m; // Stall instruction in M stage
input [`LM32_WORD_RNG] operand_0; // Muliplicand
input [`LM32_WORD_RNG] operand_1; // Multiplier
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
output [`LM32_WORD_RNG] result; // Product of multiplication
wire [`LM32_WORD_RNG] result;
/////////////////////////////////////////////////////
// Internal nets and registers
/////////////////////////////////////////////////////
// Divide multiplicands into high and low
`define HALF_WORD_WIDTH (`LM32_WORD_WIDTH/2)
`define HALF_WORD_RNG (`HALF_WORD_WIDTH-1):0
// Result = c+d+e = a*b
reg [`HALF_WORD_RNG] a0, a1, b0, b1;
reg [`HALF_WORD_RNG] c0, c1;
reg [`HALF_WORD_RNG] d1, e1;
reg [`HALF_WORD_RNG] result0, result1;
assign result = {result1, result0};
/////////////////////////////////////////////////////
// Sequential logic
/////////////////////////////////////////////////////
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
a0 <= {`HALF_WORD_WIDTH{1'b0}};
a1 <= {`HALF_WORD_WIDTH{1'b0}};
b0 <= {`HALF_WORD_WIDTH{1'b0}};
b1 <= {`HALF_WORD_WIDTH{1'b0}};
c0 <= {`HALF_WORD_WIDTH{1'b0}};
c1 <= {`HALF_WORD_WIDTH{1'b0}};
d1 <= {`HALF_WORD_WIDTH{1'b0}};
e1 <= {`HALF_WORD_WIDTH{1'b0}};
result0 <= {`HALF_WORD_WIDTH{1'b0}};
result1 <= {`HALF_WORD_WIDTH{1'b0}};
end
else
begin
if (stall_x == `FALSE)
begin
{a1, a0} <= operand_0;
{b1, b0} <= operand_1;
end
if (stall_m == `FALSE)
begin
{c1, c0} <= a0 * b0;
d1 <= a0 * b1;
e1 <= a1 * b0;
end
result0 <= c0;
result1 <= c1 + d1 + e1;
end
end
endmodule
modules/wishbone/wb_simple_pwm/simple_pwm_wb.wb
View file @ fa8df2bb
......@@ -5,7 +5,7 @@
-- Project : General Cores Collection
-------------------------------------------------------------------------------
-- File : simple_pwm_wb.wb
-- Author : Tomasz Włostowski
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2012-12-10
-- Last update: 2013-01-09
......
modules/wishbone/wb_simple_timer/Manifest.py
View file @ fa8df2bb
files = ["wb_tics.vhd", "xwb_tics.vhd"];
\ No newline at end of file
files = ["wb_tics.vhd", "xwb_tics.vhd"];
modules/wishbone/wb_uart/uart_async_rx.vhd
View file @ fa8df2bb
This diff is collapsed.
modules/wishbone/wbgen2/wbgen2_dpssram.vhd
View file @ fa8df2bb
......@@ -11,13 +11,13 @@
-- Copyright (c) 2011 CERN
--
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 0.51 (the “License”) (which enables you, at your option,
-- License, Version 0.51 (the "License") (which enables you, at your option,
-- to treat this file as licensed under the Apache License 2.0); you may not
-- use this file except in compliance with the License. You may obtain a copy
-- of the License at http://solderpad.org/licenses/SHL-0.51.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
-------------------------------------------------------------------------------
......
modules/wishbone/wbgen2/wbgen2_eic.vhd
View file @ fa8df2bb
......@@ -11,13 +11,13 @@
-- Copyright (c) 2011 CERN
--
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 0.51 (the “License”) (which enables you, at your option,
-- License, Version 0.51 (the "License") (which enables you, at your option,
-- to treat this file as licensed under the Apache License 2.0); you may not
-- use this file except in compliance with the License. You may obtain a copy
-- of the License at http://solderpad.org/licenses/SHL-0.51.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
-------------------------------------------------------------------------------
......
modules/wishbone/wbgen2/wbgen2_fifo_async.vhd
View file @ fa8df2bb
......@@ -11,13 +11,13 @@
-- Copyright (c) 2011 CERN
--
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 0.51 (the “License”) (which enables you, at your option,
-- License, Version 0.51 (the "License") (which enables you, at your option,
-- to treat this file as licensed under the Apache License 2.0); you may not
-- use this file except in compliance with the License. You may obtain a copy
-- of the License at http://solderpad.org/licenses/SHL-0.51.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
-------------------------------------------------------------------------------
......
modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd
View file @ fa8df2bb
......@@ -11,13 +11,13 @@
-- Copyright (c) 2011 CERN
--
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 0.51 (the “License”) (which enables you, at your option,
-- License, Version 0.51 (the "License") (which enables you, at your option,
-- to treat this file as licensed under the Apache License 2.0); you may not
-- use this file except in compliance with the License. You may obtain a copy
-- of the License at http://solderpad.org/licenses/SHL-0.51.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
-------------------------------------------------------------------------------
......
platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd
View file @ fa8df2bb
......@@ -3,7 +3,7 @@
-- Project : General Cores Library
-------------------------------------------------------------------------------
-- File : wb_xilinx_fpga_loader.vhd
-- Author : Tomasz Włostowski
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2012-01-30
-- Last update : 2012-01-30
......
platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.wb
View file @ fa8df2bb
......@@ -5,7 +5,7 @@
-- Project : General Cores Library
-------------------------------------------------------------------------------
-- File : xloader_wb.wb
-- Author : Tomasz Włostowski
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2012-01-30
-- Last update : 2012-01-30
......
platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd
View file @ fa8df2bb
......@@ -3,7 +3,7 @@
-- Project : General Cores Library
-------------------------------------------------------------------------------
-- File : xwb_xilinx_fpga_loader.vhd
-- Author : Tomasz Włostowski
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2012-01-30
-- Last update : 2012-01-30
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment